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Apple SoC DT updates for 6.4.

Browse Source 
This time we have the M2 (t8112) device trees and compatible updates,
 as well as a minor fix for PCIe ports on the prior models.
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQSByI3Ki0mXziclZJcd+FPLCI8zYgUCZC5xWQAKCRAd+FPLCI8z
 YuYaAP9vBvdgyYbZ8t3V89SGjV2QlEd2w6uvvVI8LMJlkOTIGwD+Pz+DN1f/kF8P
 n2rjUQQiTvu/FGoI5HdTSIlAANLVkgs=
 =Ddc1
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmQ5Ut4ACgkQYKtH/8kJ
 UicrMQ/9Hw6DBX6NTjPa/EoYwg23eyDqSkamhyBAxnlWZ+LbUYj37YqSEcShzZpb
 hicxKEn9UnOhsSbOr+g/RcUjPc+F8Vw26sWrOjCmxRSnRGpLSVZP9ewTGcyRT8ek
 Sc/AQvmefNzqMCIiZTf63c/U4OdDmUirep5D6eviBU+Y5RkTK8qGJdJfd3LFR/Dj
 jfOUM+LEhRCq/YowaMSG0wr9WpxhURN+pCy0MfxouLOIaD+RHdrT6/5hdnjSix6r
 Jzsc+qm0FTXMCa7j9yUYa7op29cnNYf9Ne+xxVwND95QBP72OmZZHTbu50UknAqT
 34t5u+EHub854Lmjx2Ut2Y+HClj6/weFBrun1zyx5Flld1tCrsx7zTN6tbMKcTh/
 Ypw2tCbyUpiK3sKmMx1XWKY2f9fgyMP3KYlCpHJXxH66PKoYBumyrAfKPQwyTYqk
 Zo5snhgiXDdUHJLTh1ZforQjO57odcKfSsl92VdEWNrYKG38xNNnyb1g88tJCgWZ
 sPSjDy33ARHqC7ge+BenqP2K128agPVnLGKeYHduH/6UD4QMXgYcm/fwKM7+f8FD
 N4+3w1KqMT1G+T1cyx0xT5LfnTWouuB651y+SW595fOiQDEUzP/8k5uP/Gi/1tQX
 ZyNLKM13x9l6njtBuCZU+xO1AEtYDc01Tw2RNZL5VEdlScnzvNE=
 =hslk
 -----END PGP SIGNATURE-----

Merge tag 'asahi-soc-dt-6.4' of https://github.com/AsahiLinux/linux into soc/dt

Apple SoC DT updates for 6.4.

This time we have the M2 (t8112) device trees and compatible updates,
as well as a minor fix for PCIe ports on the prior models.

* tag 'asahi-soc-dt-6.4' of https://github.com/AsahiLinux/linux:
  arm64: dts: apple: t600x: Disable unused PCIe ports
  arm64: dts: apple: t8103: Disable unused PCIe ports
  arm64: dts: apple: t8112: Initial t8112 (M2) device trees
  dt-bindings: arm: apple: Add t8112 j413/j473/j493 compatibles
  dt-bindings: clock: apple,nco: Add t8112-nco compatible
  dt-bindings: i2c: apple,i2c: Add apple,t8112-i2c compatible
  dt-bindings: pinctrl: apple,pinctrl: Add apple,t8112-pinctrl compatible
  dt-bindings: pci: apple,pcie: Add t8112 support
  dt-bindings: nvme: apple: Add apple,t8112-nvme-ans2 compatible string
  dt-bindings: mailbox: apple,mailbox: Add t8112 compatibles
  dt-bindings: iommu: apple,sart: Add apple,t8112-sart compatible string
  dt-bindings: interrupt-controller: apple,aic2: Add apple,t8112-aic compatible
  dt-bindings: arm: cpus: Add apple,avalanche & blizzard compatibles
  dt-bindings: watchdog: apple,wdt: Add t8112-wdt compatible
  dt-bindings: arm: apple: apple,pmgr: Add t8112-pmgr compatible
  dt-bindings: power: apple,pmgr-pwrstate: Add t8112 compatible

Link: https://lore.kernel.org/r/7263df01-aebc-2db5-f074-4805e0ae9fbc@marcan.st
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-04-14 15:19:25 +02:00
commit 295954fefe
29 changed files with 2403 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
Documentation/devicetree/bindings/arm/apple.yaml
View File

@ -19,6 +19,12 @@ description: |
- MacBook Air (M1, 2020)
- iMac (24-inch, M1, 2021)
Devices based on the "M2" SoC:
- MacBook Air (M2, 2022)
- MacBook Pro (13-inch, M2, 2022)
- Mac mini (M2, 2023)
And devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs:
- MacBook Pro (14-inch, M1 Pro, 2021)
@ -70,6 +76,15 @@ properties:
- const: apple,t8103
- const: apple,arm-platform
- description: Apple M2 SoC based platforms
items:
- enum:
- apple,j413 # MacBook Air (M2, 2022)
- apple,j473 # Mac mini (M2, 2023)
- apple,j493 # MacBook Pro (13-inch, M2, 2022)
- const: apple,t8112
- const: apple,arm-platform
- description: Apple M1 Pro SoC based platforms
items:
- enum:

1
Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml
View File

@ -23,6 +23,7 @@ properties:
items:
- enum:
- apple,t8103-pmgr
- apple,t8112-pmgr
- apple,t6000-pmgr
- const: apple,pmgr
- const: syscon

2
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@ -85,6 +85,8 @@ properties:
compatible:
enum:
- apple,avalanche
- apple,blizzard
- apple,icestorm
- apple,firestorm
- arm,arm710t

1
Documentation/devicetree/bindings/clock/apple,nco.yaml
View File

@ -23,6 +23,7 @@ properties:
- enum:
- apple,t6000-nco
- apple,t8103-nco
- apple,t8112-nco
- const: apple,nco
clocks:

1
Documentation/devicetree/bindings/i2c/apple,i2c.yaml
View File

@ -23,6 +23,7 @@ properties:
items:
- enum:
- apple,t8103-i2c
- apple,t8112-i2c
- apple,t6000-i2c
- const: apple,i2c

22
Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml
View File

@ -31,19 +31,22 @@ description: |
properties:
compatible:
items:
- const: apple,t6000-aic
- enum:
- apple,t8112-aic
- apple,t6000-aic
- const: apple,aic2
interrupt-controller: true
'#interrupt-cells':
const: 4
minimum: 3
maximum: 4
description: |
The 1st cell contains the interrupt type:
- 0: Hardware IRQ
- 1: FIQ
The 2nd cell contains the die ID.
The 2nd cell contains the die ID (only present on apple,t6000-aic).
The next cell contains the interrupt number.
- HW IRQs: interrupt number
@ -109,6 +112,19 @@ additionalProperties: false
allOf:
- $ref: /schemas/interrupt-controller.yaml#
- if:
properties:
compatible:
contains:
const: apple,t8112-aic
then:
properties:
'#interrupt-cells':
const: 3
else:
properties:
'#interrupt-cells':
const: 4
examples:
- |

10
Documentation/devicetree/bindings/iommu/apple,sart.yaml
View File

@ -28,9 +28,13 @@ description:
properties:
compatible:
enum:
- apple,t6000-sart
- apple,t8103-sart
oneOf:
- items:
- const: apple,t8112-sart
- const: apple,t6000-sart
- enum:
- apple,t6000-sart
- apple,t8103-sart
reg:
maxItems: 1

2
Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml
View File

@ -29,6 +29,7 @@ properties:
items:
- enum:
- apple,t8103-asc-mailbox
- apple,t8112-asc-mailbox
- apple,t6000-asc-mailbox
- const: apple,asc-mailbox-v4
@ -39,6 +40,7 @@ properties:
items:
- enum:
- apple,t8103-m3-mailbox
- apple,t8112-m3-mailbox
- apple,t6000-m3-mailbox
- const: apple,m3-mailbox-v2

5
Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml
View File

@ -14,6 +14,7 @@ properties:
items:
- enum:
- apple,t8103-nvme-ans2
- apple,t8112-nvme-ans2
- apple,t6000-nvme-ans2
- const: apple,nvme-ans2
@ -65,7 +66,9 @@ if:
properties:
compatible:
contains:
const: apple,t8103-nvme-ans2
enum:
- apple,t8103-nvme-ans2
- apple,t8112-nvme-ans2
then:
properties:
power-domains:

1
Documentation/devicetree/bindings/pci/apple,pcie.yaml
View File

@ -33,6 +33,7 @@ properties:
items:
- enum:
- apple,t8103-pcie
- apple,t8112-pcie
- apple,t6000-pcie
- const: apple,pcie

1
Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml
View File

@ -19,6 +19,7 @@ properties:
items:
- enum:
- apple,t8103-pinctrl
- apple,t8112-pinctrl
- apple,t6000-pinctrl
- const: apple,pinctrl

1
Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml
View File

@ -32,6 +32,7 @@ properties:
items:
- enum:
- apple,t8103-pmgr-pwrstate
- apple,t8112-pmgr-pwrstate
- apple,t6000-pmgr-pwrstate
- const: apple,pmgr-pwrstate

1
Documentation/devicetree/bindings/watchdog/apple,wdt.yaml
View File

@ -17,6 +17,7 @@ properties:
items:
- enum:
- apple,t8103-wdt
- apple,t8112-wdt
- apple,t6000-wdt
- const: apple,wdt

3
arch/arm64/boot/dts/apple/Makefile
View File

@ -10,3 +10,6 @@ dtb-$(CONFIG_ARCH_APPLE) += t6000-j316s.dtb
dtb-$(CONFIG_ARCH_APPLE) += t6001-j316c.dtb
dtb-$(CONFIG_ARCH_APPLE) += t6001-j375c.dtb
dtb-$(CONFIG_ARCH_APPLE) += t6002-j375d.dtb
dtb-$(CONFIG_ARCH_APPLE) += t8112-j413.dtb
dtb-$(CONFIG_ARCH_APPLE) += t8112-j473.dtb
dtb-$(CONFIG_ARCH_APPLE) += t8112-j493.dtb

4
arch/arm64/boot/dts/apple/t600x-die0.dtsi
View File

@ -233,6 +233,7 @@
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 0 1277 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&ps_apcie_gp_sys>;
status = "disabled";
};
pcie0_dart_3: iommu@584008000 {
@ -242,6 +243,7 @@
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 0 1280 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&ps_apcie_gp_sys>;
status = "disabled";
};
pcie0: pcie@590000000 {
@ -338,6 +340,7 @@
<0 0 0 2 &port02 0 0 0 1>,
<0 0 0 3 &port02 0 0 0 2>,
<0 0 0 4 &port02 0 0 0 3>;
status = "disabled";
};
port03: pci@3,0 {
@ -357,5 +360,6 @@
<0 0 0 2 &port03 0 0 0 1>,
<0 0 0 3 &port03 0 0 0 2>,
<0 0 0 4 &port03 0 0 0 3>;
status = "disabled";
};
};

11
arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi
View File

@ -101,14 +101,3 @@
wp-inverted;
};
};
&pcie0_dart_2 {
status = "disabled";
};
&pcie0_dart_3 {
status = "disabled";
};
/delete-node/ &port02;
/delete-node/ &port03;

11
arch/arm64/boot/dts/apple/t600x-j375.dtsi
View File

@ -104,6 +104,7 @@
&port02 {
/* 10 Gbit Ethernet */
bus-range = <3 3>;
status = "okay";
ethernet0: ethernet@0,0 {
reg = <0x30000 0x0 0x0 0x0 0x0>;
/* To be filled by the loader */
@ -114,4 +115,14 @@
&port03 {
/* USB xHCI */
bus-range = <4 4>;
status = "okay";
};
&pcie0_dart_2 {
status = "okay";
};
&pcie0_dart_3 {
status = "okay";
};

10
arch/arm64/boot/dts/apple/t8103-j274.dts
View File

@ -37,10 +37,12 @@
&port01 {
bus-range = <2 2>;
status = "okay";
};
&port02 {
bus-range = <3 3>;
status = "okay";
ethernet0: ethernet@0,0 {
reg = <0x30000 0x0 0x0 0x0 0x0>;
/* To be filled by the loader */
@ -48,6 +50,14 @@
};
};
&pcie0_dart_1 {
status = "okay";
};
&pcie0_dart_2 {
status = "okay";
};
&i2c2 {
status = "okay";
};

15
arch/arm64/boot/dts/apple/t8103-j293.dts
View File

@ -25,21 +25,6 @@
brcm,board-type = "apple,honshu";
};
/*
* Remove unused PCIe ports and disable the associated DARTs.
*/
&pcie0_dart_1 {
status = "disabled";
};
&pcie0_dart_2 {
status = "disabled";
};
/delete-node/ &port01;
/delete-node/ &port02;
&i2c2 {
status = "okay";
};

15
arch/arm64/boot/dts/apple/t8103-j313.dts
View File

@ -24,18 +24,3 @@
&wifi0 {
brcm,board-type = "apple,shikoku";
};
/*
* Remove unused PCIe ports and disable the associated DARTs.
*/
&pcie0_dart_1 {
status = "disabled";
};
&pcie0_dart_2 {
status = "disabled";
};
/delete-node/ &port01;
/delete-node/ &port02;

10
arch/arm64/boot/dts/apple/t8103-j456.dts
View File

@ -55,13 +55,23 @@
&port01 {
bus-range = <2 2>;
status = "okay";
};
&port02 {
bus-range = <3 3>;
status = "okay";
ethernet0: ethernet@0,0 {
reg = <0x30000 0x0 0x0 0x0 0x0>;
/* To be filled by the loader */
local-mac-address = [00 10 18 00 00 00];
};
};
&pcie0_dart_1 {
status = "okay";
};
&pcie0_dart_2 {
status = "okay";
};

11
arch/arm64/boot/dts/apple/t8103-j457.dts
View File

@ -37,6 +37,7 @@
&port02 {
bus-range = <3 3>;
status = "okay";
ethernet0: ethernet@0,0 {
reg = <0x30000 0x0 0x0 0x0 0x0>;
/* To be filled by the loader */
@ -44,12 +45,6 @@
};
};
/*
* Remove unused PCIe port and disable the associated DART.
*/
&pcie0_dart_1 {
status = "disabled";
&pcie0_dart_2 {
status = "okay";
};
/delete-node/ &port01;

4
arch/arm64/boot/dts/apple/t8103.dtsi
View File

@ -724,6 +724,7 @@
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&ps_apcie_gp>;
status = "disabled";
};
pcie0_dart_2: iommu@683008000 {
@ -733,6 +734,7 @@
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&ps_apcie_gp>;
status = "disabled";
};
pcie0: pcie@690000000 {
@ -807,6 +809,7 @@
<0 0 0 2 &port01 0 0 0 1>,
<0 0 0 3 &port01 0 0 0 2>,
<0 0 0 4 &port01 0 0 0 3>;
status = "disabled";
};
port02: pci@2,0 {
@ -826,6 +829,7 @@
<0 0 0 2 &port02 0 0 0 1>,
<0 0 0 3 &port02 0 0 0 2>,
<0 0 0 4 &port02 0 0 0 3>;
status = "disabled";
};
};
};

63
arch/arm64/boot/dts/apple/t8112-j413.dts Normal file
View File

@ -0,0 +1,63 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple MacBook Air (M2, 2022)
*
* target-type: J413
*
* Copyright The Asahi Linux Contributors
*/
/dts-v1/;
#include "t8112.dtsi"
#include "t8112-jxxx.dtsi"
/ {
compatible = "apple,j413", "apple,t8112", "apple,arm-platform";
model = "Apple MacBook Air (13-inch, M2, 2022)";
aliases {
bluetooth0 = &bluetooth0;
wifi0 = &wifi0;
};
};
/*
* Force the bus number assignments so that we can declare some of the
* on-board devices and properties that are populated by the bootloader
* (such as MAC addresses).
*/
&port00 {
bus-range = <1 1>;
wifi0: wifi@0,0 {
compatible = "pci14e4,4433";
reg = <0x10000 0x0 0x0 0x0 0x0>;
/* To be filled by the loader */
local-mac-address = [00 10 18 00 00 10];
apple,antenna-sku = "XX";
brcm,board-type = "apple,hokkaido";
};
bluetooth0: bluetooth@0,1 {
compatible = "pci14e4,5f71";
reg = <0x10100 0x0 0x0 0x0 0x0>;
/* To be filled by the loader */
local-bd-address = [00 00 00 00 00 00];
brcm,board-type = "apple,hokkaido";
};
};
&i2c0 {
/* MagSafe port */
hpm5: usb-pd@3a {
compatible = "apple,cd321x";
reg = <0x3a>;
interrupt-parent = <&pinctrl_ap>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
};
};
&i2c4 {
status = "okay";
};

54
arch/arm64/boot/dts/apple/t8112-j473.dts Normal file
View File

@ -0,0 +1,54 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple Mac mini (M2, 2023)
*
* target-type: J473
*
* Copyright The Asahi Linux Contributors
*/
/dts-v1/;
#include "t8112.dtsi"
#include "t8112-jxxx.dtsi"
/ {
compatible = "apple,j473", "apple,t8112", "apple,arm-platform";
model = "Apple Mac mini (M2, 2023)";
aliases {
ethernet0 = &ethernet0;
};
};
/*
* Force the bus number assignments so that we can declare some of the
* on-board devices and properties that are populated by the bootloader
* (such as MAC addresses).
*/
&port00 {
bus-range = <1 1>;
};
&port01 {
bus-range = <2 2>;
status = "okay";
};
&port02 {
bus-range = <3 3>;
status = "okay";
ethernet0: ethernet@0,0 {
reg = <0x30000 0x0 0x0 0x0 0x0>;
/* To be filled by the loader */
local-mac-address = [00 10 18 00 00 00];
};
};
&pcie1_dart {
status = "okay";
};
&pcie2_dart {
status = "okay";
};

52
arch/arm64/boot/dts/apple/t8112-j493.dts Normal file
View File

@ -0,0 +1,52 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple MacBook Pro (13-inch, M1, 2022)
*
* target-type: J493
*
* Copyright The Asahi Linux Contributors
*/
/dts-v1/;
#include "t8112.dtsi"
#include "t8112-jxxx.dtsi"
/ {
compatible = "apple,j493", "apple,t8112", "apple,arm-platform";
model = "Apple MacBook Pro (13-inch, M2, 2022)";
aliases {
bluetooth0 = &bluetooth0;
wifi0 = &wifi0;
};
};
/*
* Force the bus number assignments so that we can declare some of the
* on-board devices and properties that are populated by the bootloader
* (such as MAC addresses).
*/
&port00 {
bus-range = <1 1>;
wifi0: wifi@0,0 {
compatible = "pci14e4,4425";
reg = <0x10000 0x0 0x0 0x0 0x0>;
/* To be filled by the loader */
local-mac-address = [00 00 00 00 00 00];
apple,antenna-sku = "XX";
brcm,board-type = "apple,kyushu";
};
bluetooth0: bluetooth@0,1 {
compatible = "pci14e4,5f69";
reg = <0x10100 0x0 0x0 0x0 0x0>;
/* To be filled by the loader */
local-bd-address = [00 00 00 00 00 00];
brcm,board-type = "apple,kyushu";
};
};
&i2c4 {
status = "okay";
};

81
arch/arm64/boot/dts/apple/t8112-jxxx.dtsi Normal file
View File

@ -0,0 +1,81 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple M2 MacBook Air/Pro (M2, 2022)
*
* This file contains parts common to all Apple M2 devices using the t8112.
*
* target-type: J493, J413
*
* Copyright The Asahi Linux Contributors
*/
/ {
aliases {
serial0 = &serial0;
serial2 = &serial2;
};
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
stdout-path = "serial0";
framebuffer0: framebuffer@0 {
compatible = "apple,simple-framebuffer", "simple-framebuffer";
reg = <0 0 0 0>; /* To be filled by loader */
/* Format properties will be added by loader */
status = "disabled";
};
};
memory@800000000 {
device_type = "memory";
reg = <0x8 0 0x2 0>; /* To be filled by loader */
};
};
&serial0 {
status = "okay";
};
&serial2 {
status = "okay";
};
&i2c0 {
status = "okay";
hpm0: usb-pd@38 {
compatible = "apple,cd321x";
reg = <0x38>;
interrupt-parent = <&pinctrl_ap>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
};
hpm1: usb-pd@3f {
compatible = "apple,cd321x";
reg = <0x3f>;
interrupt-parent = <&pinctrl_ap>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
};
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&nco_clkref {
clock-frequency = <900000000>;
};

1140
arch/arm64/boot/dts/apple/t8112-pmgr.dtsi Normal file
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912
arch/arm64/boot/dts/apple/t8112.dtsi Normal file
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@ -0,0 +1,912 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple T8112 "M2" SoC
*
* Other names: H14G
*
* Copyright The Asahi Linux Contributors
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
#include <dt-bindings/spmi/spmi.h>
/ {
compatible = "apple,t8112", "apple,arm-platform";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu_e0>;
};
core1 {
cpu = <&cpu_e1>;
};
core2 {
cpu = <&cpu_e2>;
};
core3 {
cpu = <&cpu_e3>;
};
};
cluster1 {
core0 {
cpu = <&cpu_p0>;
};
core1 {
cpu = <&cpu_p1>;
};
core2 {
cpu = <&cpu_p2>;
};
core3 {
cpu = <&cpu_p3>;
};
};
};
cpu_e0: cpu@0 {
compatible = "apple,blizzard";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
operating-points-v2 = <&ecluster_opp>;
capacity-dmips-mhz = <756>;
performance-domains = <&cpufreq_e>;
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x20000>;
d-cache-size = <0x10000>;
};
cpu_e1: cpu@1 {
compatible = "apple,blizzard";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
operating-points-v2 = <&ecluster_opp>;
capacity-dmips-mhz = <756>;
performance-domains = <&cpufreq_e>;
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x20000>;
d-cache-size = <0x10000>;
};
cpu_e2: cpu@2 {
compatible = "apple,blizzard";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
operating-points-v2 = <&ecluster_opp>;
capacity-dmips-mhz = <756>;
performance-domains = <&cpufreq_e>;
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x20000>;
d-cache-size = <0x10000>;
};
cpu_e3: cpu@3 {
compatible = "apple,blizzard";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
operating-points-v2 = <&ecluster_opp>;
capacity-dmips-mhz = <756>;
performance-domains = <&cpufreq_e>;
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x20000>;
d-cache-size = <0x10000>;
};
cpu_p0: cpu@10100 {
compatible = "apple,avalanche";
device_type = "cpu";
reg = <0x0 0x10100>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
operating-points-v2 = <&pcluster_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p>;
next-level-cache = <&l2_cache_1>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
};
cpu_p1: cpu@10101 {
compatible = "apple,avalanche";
device_type = "cpu";
reg = <0x0 0x10101>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
operating-points-v2 = <&pcluster_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p>;
next-level-cache = <&l2_cache_1>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
};
cpu_p2: cpu@10102 {
compatible = "apple,avalanche";
device_type = "cpu";
reg = <0x0 0x10102>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
operating-points-v2 = <&pcluster_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p>;
next-level-cache = <&l2_cache_1>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
};
cpu_p3: cpu@10103 {
compatible = "apple,avalanche";
device_type = "cpu";
reg = <0x0 0x10103>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
operating-points-v2 = <&pcluster_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p>;
next-level-cache = <&l2_cache_1>;
i-cache-size = <0x30000>;
d-cache-size = <0x20000>;
};
l2_cache_0: l2-cache-0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x400000>;
};
l2_cache_1: l2-cache-1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x1000000>;
};
};
ecluster_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp01 {
opp-hz = /bits/ 64 <600000000>;
opp-level = <1>;
clock-latency-ns = <7500>;
};
opp02 {
opp-hz = /bits/ 64 <912000000>;
opp-level = <2>;
clock-latency-ns = <20000>;
};
opp03 {
opp-hz = /bits/ 64 <1284000000>;
opp-level = <3>;
clock-latency-ns = <22000>;
};
opp04 {
opp-hz = /bits/ 64 <1752000000>;
opp-level = <4>;
clock-latency-ns = <30000>;
};
opp05 {
opp-hz = /bits/ 64 <2004000000>;
opp-level = <5>;
clock-latency-ns = <35000>;
};
opp06 {
opp-hz = /bits/ 64 <2256000000>;
opp-level = <6>;
clock-latency-ns = <39000>;
};
opp07 {
opp-hz = /bits/ 64 <2424000000>;
opp-level = <7>;
clock-latency-ns = <53000>;
};
};
pcluster_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
opp01 {
opp-hz = /bits/ 64 <660000000>;
opp-level = <1>;
clock-latency-ns = <9000>;
};
opp02 {
opp-hz = /bits/ 64 <924000000>;
opp-level = <2>;
clock-latency-ns = <19000>;
};
opp03 {
opp-hz = /bits/ 64 <1188000000>;
opp-level = <3>;
clock-latency-ns = <22000>;
};
opp04 {
opp-hz = /bits/ 64 <1452000000>;
opp-level = <4>;
clock-latency-ns = <24000>;
};
opp05 {
opp-hz = /bits/ 64 <1704000000>;
opp-level = <5>;
clock-latency-ns = <26000>;
};
opp06 {
opp-hz = /bits/ 64 <1968000000>;
opp-level = <6>;
clock-latency-ns = <28000>;
};
opp07 {
opp-hz = /bits/ 64 <2208000000>;
opp-level = <7>;
clock-latency-ns = <30000>;
};
opp08 {
opp-hz = /bits/ 64 <2400000000>;
opp-level = <8>;
clock-latency-ns = <33000>;
};
opp09 {
opp-hz = /bits/ 64 <2568000000>;
opp-level = <9>;
clock-latency-ns = <34000>;
};
opp10 {
opp-hz = /bits/ 64 <2724000000>;
opp-level = <10>;
clock-latency-ns = <36000>;
};
opp11 {
opp-hz = /bits/ 64 <2868000000>;
opp-level = <11>;
clock-latency-ns = <41000>;
};
opp12 {
opp-hz = /bits/ 64 <2988000000>;
opp-level = <12>;
clock-latency-ns = <42000>;
};
opp13 {
opp-hz = /bits/ 64 <3096000000>;
opp-level = <13>;
clock-latency-ns = <44000>;
};
opp14 {
opp-hz = /bits/ 64 <3204000000>;
opp-level = <14>;
clock-latency-ns = <46000>;
};
/* Not available until CPU deep sleep is implemented */
#if 0
opp15 {
opp-hz = /bits/ 64 <3324000000>;
opp-level = <15>;
clock-latency-ns = <62000>;
turbo-mode;
};
opp16 {
opp-hz = /bits/ 64 <3408000000>;
opp-level = <16>;
clock-latency-ns = <62000>;
turbo-mode;
};
opp17 {
opp-hz = /bits/ 64 <3504000000>;
opp-level = <17>;
clock-latency-ns = <62000>;
turbo-mode;
};
#endif
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&aic>;
interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
<AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
<AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
<AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
};
pmu-e {
compatible = "apple,blizzard-pmu";
interrupt-parent = <&aic>;
interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
};
pmu-p {
compatible = "apple,avalanche-pmu";
interrupt-parent = <&aic>;
interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
};
clkref: clock-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "clkref";
};
/*
* This is a fabulated representation of the input clock
* to NCO since we don't know the true clock tree.
*/
nco_clkref: clock-ref-nco {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "nco_ref";
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
nonposted-mmio;
cpufreq_e: cpufreq@210e20000 {
compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq";
reg = <0x2 0x10e20000 0 0x1000>;
#performance-domain-cells = <0>;
};
cpufreq_p: cpufreq@211e20000 {
compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq";
reg = <0x2 0x11e20000 0 0x1000>;
#performance-domain-cells = <0>;
};
sio_dart: iommu@235004000 {
compatible = "apple,t8110-dart";
reg = <0x2 0x35004000 0x0 0x4000>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 769 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
power-domains = <&ps_sio_cpu>;
};
i2c0: i2c@235010000 {
compatible = "apple,t8112-i2c", "apple,i2c";
reg = <0x2 0x35010000 0x0 0x4000>;
clocks = <&clkref>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 761 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
#address-cells = <0x1>;
#size-cells = <0x0>;
power-domains = <&ps_i2c0>;
status = "disabled";
};
i2c1: i2c@235014000 {
compatible = "apple,t8112-i2c", "apple,i2c";
reg = <0x2 0x35014000 0x0 0x4000>;
clocks = <&clkref>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 762 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
#address-cells = <0x1>;
#size-cells = <0x0>;
power-domains = <&ps_i2c1>;
status = "disabled";
};
i2c2: i2c@235018000 {
compatible = "apple,t8112-i2c", "apple,i2c";
reg = <0x2 0x35018000 0x0 0x4000>;
clocks = <&clkref>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 763 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
#address-cells = <0x1>;
#size-cells = <0x0>;
power-domains = <&ps_i2c2>;
status = "disabled";
};
i2c3: i2c@23501c000 {
compatible = "apple,t8112-i2c", "apple,i2c";
reg = <0x2 0x3501c000 0x0 0x4000>;
clocks = <&clkref>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 764 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
#address-cells = <0x1>;
#size-cells = <0x0>;
power-domains = <&ps_i2c3>;
status = "disabled";
};
i2c4: i2c@235020000 {
compatible = "apple,t8112-i2c", "apple,i2c";
reg = <0x2 0x35020000 0x0 0x4000>;
clocks = <&clkref>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 765 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
#address-cells = <0x1>;
#size-cells = <0x0>;
power-domains = <&ps_i2c4>;
status = "disabled";
};
serial0: serial@235200000 {
compatible = "apple,s5l-uart";
reg = <0x2 0x35200000 0x0 0x1000>;
reg-io-width = <4>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 739 IRQ_TYPE_LEVEL_HIGH>;
/*
* TODO: figure out the clocking properly, there may
* be a third selectable clock.
*/
clocks = <&clkref>, <&clkref>;
clock-names = "uart", "clk_uart_baud0";
power-domains = <&ps_uart0>;
status = "disabled";
};
serial2: serial@235208000 {
compatible = "apple,s5l-uart";
reg = <0x2 0x35208000 0x0 0x1000>;
reg-io-width = <4>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 741 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkref>, <&clkref>;
clock-names = "uart", "clk_uart_baud0";
power-domains = <&ps_uart2>;
status = "disabled";
};
admac: dma-controller@238200000 {
compatible = "apple,t8112-admac", "apple,admac";
reg = <0x2 0x38200000 0x0 0x34000>;
dma-channels = <24>;
interrupts-extended = <0>,
<&aic AIC_IRQ 760 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>;
#dma-cells = <1>;
iommus = <&sio_dart 2>;
power-domains = <&ps_sio_adma>;
resets = <&ps_audio_p>;
};
mca: i2s@238400000 {
compatible = "apple,t8112-mca", "apple,mca";
reg = <0x2 0x38400000 0x0 0x18000>,
<0x2 0x38300000 0x0 0x30000>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 753 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 754 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 755 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 756 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 757 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 758 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ps_audio_p>;
clocks = <&nco 0>, <&nco 1>, <&nco 2>,
<&nco 3>, <&nco 4>, <&nco 4>;
power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
<&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>;
dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>,
<&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>,
<&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>,
<&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>,
<&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>,
<&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>;
dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
"tx1a", "rx1a", "tx1b", "rx1b",
"tx2a", "rx2a", "tx2b", "rx2b",
"tx3a", "rx3a", "tx3b", "rx3b",
"tx4a", "rx4a", "tx4b", "rx4b",
"tx5a", "rx5a", "tx5b", "rx5b";
#sound-dai-cells = <1>;
};
nco: clock-controller@23b044000 {
compatible = "apple,t8112-nco", "apple,nco";
reg = <0x2 0x3b044000 0x0 0x14000>;
clocks = <&nco_clkref>;
#clock-cells = <1>;
};
aic: interrupt-controller@23b0c0000 {
compatible = "apple,t8112-aic", "apple,aic2";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x2 0x3b0c0000 0x0 0x8000>,
<0x2 0x3b0c8000 0x0 0x4>;
reg-names = "core", "event";
power-domains = <&ps_aic>;
affinities {
e-core-pmu-affinity {
apple,fiq-index = <AIC_CPU_PMU_E>;
cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>;
};
p-core-pmu-affinity {
apple,fiq-index = <AIC_CPU_PMU_P>;
cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>;
};
};
};
pmgr: power-management@23b700000 {
compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2 0x3b700000 0 0x14000>;
/* child nodes are added in t8103-pmgr.dtsi */
};
pinctrl_ap: pinctrl@23c100000 {
compatible = "apple,t8112-pinctrl", "apple,pinctrl";
reg = <0x2 0x3c100000 0x0 0x100000>;
power-domains = <&ps_gpio>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_ap 0 0 213>;
apple,npins = <213>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 202 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 203 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 204 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 205 IRQ_TYPE_LEVEL_HIGH>;
i2c0_pins: i2c0-pins {
pinmux = <APPLE_PINMUX(111, 1)>,
<APPLE_PINMUX(110, 1)>;
};
i2c1_pins: i2c1-pins {
pinmux = <APPLE_PINMUX(113, 1)>,
<APPLE_PINMUX(112, 1)>;
};
i2c2_pins: i2c2-pins {
pinmux = <APPLE_PINMUX(87, 1)>,
<APPLE_PINMUX(86, 1)>;
};
i2c3_pins: i2c3-pins {
pinmux = <APPLE_PINMUX(54, 1)>,
<APPLE_PINMUX(53, 1)>;
};
i2c4_pins: i2c4-pins {
pinmux = <APPLE_PINMUX(131, 1)>,
<APPLE_PINMUX(130, 1)>;
};
spi3_pins: spi3-pins {
pinmux = <APPLE_PINMUX(46, 1)>,
<APPLE_PINMUX(47, 1)>,
<APPLE_PINMUX(48, 1)>,
<APPLE_PINMUX(49, 1)>;
};
pcie_pins: pcie-pins {
pinmux = <APPLE_PINMUX(162, 1)>,
<APPLE_PINMUX(163, 1)>,
<APPLE_PINMUX(164, 1)>;
// TODO: 1 more CLKREQs
};
};
pinctrl_nub: pinctrl@23d1f0000 {
compatible = "apple,t8112-pinctrl", "apple,pinctrl";
reg = <0x2 0x3d1f0000 0x0 0x4000>;
power-domains = <&ps_nub_gpio>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_nub 0 0 24>;
apple,npins = <24>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 371 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 372 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 373 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 374 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 375 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 376 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 377 IRQ_TYPE_LEVEL_HIGH>;
};
pmgr_mini: power-management@23d280000 {
compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2 0x3d280000 0 0x4000>;
/* child nodes are added in t8103-pmgr.dtsi */
};
wdt: watchdog@23d2b0000 {
compatible = "apple,t8112-wdt", "apple,wdt";
reg = <0x2 0x3d2b0000 0x0 0x4000>;
clocks = <&clkref>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 379 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_smc: pinctrl@23e820000 {
compatible = "apple,t8112-pinctrl", "apple,pinctrl";
reg = <0x2 0x3e820000 0x0 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_smc 0 0 18>;
apple,npins = <18>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 490 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 491 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 492 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 493 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 494 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 495 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 496 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_aop: pinctrl@24a820000 {
compatible = "apple,t8112-pinctrl", "apple,pinctrl";
reg = <0x2 0x4a820000 0x0 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_aop 0 0 54>;
apple,npins = <54>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 301 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 302 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 303 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 304 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 305 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 306 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 307 IRQ_TYPE_LEVEL_HIGH>;
};
ans_mbox: mbox@277408000 {
compatible = "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4";
reg = <0x2 0x77408000 0x0 0x4000>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 717 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 718 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 719 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 720 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "send-empty", "send-not-empty",
"recv-empty", "recv-not-empty";
#mbox-cells = <0>;
power-domains = <&ps_ans>;
};
sart: sart@27bc50000 {
compatible = "apple,t8112-sart", "apple,t6000-sart";
reg = <0x2 0x7bc50000 0x0 0x10000>;
power-domains = <&ps_ans>;
};
nvme@27bcc0000 {
compatible = "apple,t8112-nvme-ans2", "apple,nvme-ans2";
reg = <0x2 0x7bcc0000 0x0 0x40000>,
<0x2 0x77400000 0x0 0x4000>;
reg-names = "nvme", "ans";
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 724 IRQ_TYPE_LEVEL_HIGH>;
mboxes = <&ans_mbox>;
apple,sart = <&sart>;
power-domains = <&ps_ans>, <&ps_apcie_st>;
power-domain-names = "ans", "apcie0";
resets = <&ps_ans>;
};
pcie0_dart: iommu@681008000 {
compatible = "apple,t8110-dart";
reg = <0x6 0x81008000 0x0 0x4000>;
#iommu-cells = <1>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 782 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&ps_apcie_gp>;
};
pcie1_dart: iommu@682008000 {
compatible = "apple,t8110-dart";
reg = <0x6 0x82008000 0x0 0x4000>;
#iommu-cells = <1>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 785 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&ps_apcie_gp>;
status = "disabled";
};
pcie2_dart: iommu@683008000 {
compatible = "apple,t8110-dart";
reg = <0x6 0x83008000 0x0 0x4000>;
#iommu-cells = <1>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 788 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&ps_apcie_gp>;
status = "disabled";
};
pcie3_dart: iommu@684008000 {
compatible = "apple,t8110-dart";
reg = <0x6 0x84008000 0x0 0x4000>;
#iommu-cells = <1>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 791 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&ps_apcie_gp>;
status = "disabled";
};
pcie0: pcie@690000000 {
compatible = "apple,t8112-pcie", "apple,pcie";
device_type = "pci";
reg = <0x6 0x90000000 0x0 0x1000000>,
<0x6 0x80000000 0x0 0x100000>,
<0x6 0x81000000 0x0 0x4000>,
<0x6 0x82000000 0x0 0x4000>,
<0x6 0x83000000 0x0 0x4000>,
<0x6 0x84000000 0x0 0x4000>;
reg-names = "config", "rc", "port0", "port1", "port2", "port3";
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 784 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 787 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 790 IRQ_TYPE_LEVEL_HIGH>;
msi-controller;
msi-parent = <&pcie0>;
msi-ranges = <&aic AIC_IRQ 793 IRQ_TYPE_EDGE_RISING 32>;
iommu-map = <0x100 &pcie0_dart 0 1>,
<0x200 &pcie1_dart 1 1>,
<0x300 &pcie2_dart 2 1>,
<0x400 &pcie3_dart 3 1>;
iommu-map-mask = <0xff00>;
bus-range = <0 4>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
<0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
power-domains = <&ps_apcie_gp>;
pinctrl-0 = <&pcie_pins>;
pinctrl-names = "default";
port00: pci@0,0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
reset-gpios = <&pinctrl_ap 166 GPIO_ACTIVE_LOW>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
<0 0 0 2 &port00 0 0 0 1>,
<0 0 0 3 &port00 0 0 0 2>,
<0 0 0 4 &port00 0 0 0 3>;
};
port01: pci@1,0 {
device_type = "pci";
reg = <0x800 0x0 0x0 0x0 0x0>;
reset-gpios = <&pinctrl_ap 167 GPIO_ACTIVE_LOW>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
<0 0 0 2 &port01 0 0 0 1>,
<0 0 0 3 &port01 0 0 0 2>,
<0 0 0 4 &port01 0 0 0 3>;
status = "disabled";
};
port02: pci@2,0 {
device_type = "pci";
reg = <0x1000 0x0 0x0 0x0 0x0>;
reset-gpios = <&pinctrl_ap 168 GPIO_ACTIVE_LOW>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
<0 0 0 2 &port02 0 0 0 1>,
<0 0 0 3 &port02 0 0 0 2>,
<0 0 0 4 &port02 0 0 0 3>;
status = "disabled";
};
/* TODO: GPIO unknown */
port03: pci@3,0 {
device_type = "pci";
reg = <0x1800 0x0 0x0 0x0 0x0>;
//reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &port03 0 0 0 0>,
<0 0 0 2 &port03 0 0 0 1>,
<0 0 0 3 &port03 0 0 0 2>,
<0 0 0 4 &port03 0 0 0 3>;
status = "disabled";
};
};
};
};
#include "t8112-pmgr.dtsi"