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soc/tegra: cbb: Check firewall before enabling error reporting
To enable error reporting for a fabric to CCPLEX, we need to write its
register for enabling error interrupt to CCPLEX during boot and later
clear the error status register after error occurs. If a fabric's
registers are protected and not accessible from CCPLEX, then accessing
the registers will cause CBB firewall error.
Add support to check whether write access from CCPLEX to the registers
of a fabric is not blocked by it's firewall before enabling error
reporting to CCPLEX for that fabric.
Fixes: fc2f151d23
("soc/tegra: cbb: Add driver for Tegra234 CBB 2.0")
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
parent
55084947d6
commit
2927cf85f4
@ -72,6 +72,11 @@
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#define REQ_SOCKET_ID GENMASK(27, 24)
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#define CCPLEX_MSTRID 0x1
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#define FIREWALL_APERTURE_SZ 0x10000
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/* Write firewall check enable */
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#define WEN 0x20000
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enum tegra234_cbb_fabric_ids {
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CBB_FAB_ID,
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SCE_FAB_ID,
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@ -92,6 +97,9 @@ struct tegra234_slave_lookup {
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struct tegra234_cbb_fabric {
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const char *name;
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phys_addr_t off_mask_erd;
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phys_addr_t firewall_base;
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unsigned int firewall_ctl;
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unsigned int firewall_wr_ctl;
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const char * const *master_id;
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unsigned int notifier_offset;
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const struct tegra_cbb_error *errors;
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@ -129,6 +137,44 @@ static inline struct tegra234_cbb *to_tegra234_cbb(struct tegra_cbb *cbb)
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static LIST_HEAD(cbb_list);
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static DEFINE_SPINLOCK(cbb_lock);
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static bool
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tegra234_cbb_write_access_allowed(struct platform_device *pdev, struct tegra234_cbb *cbb)
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{
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u32 val;
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if (!cbb->fabric->firewall_base ||
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!cbb->fabric->firewall_ctl ||
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!cbb->fabric->firewall_wr_ctl) {
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dev_info(&pdev->dev, "SoC data missing for firewall\n");
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return false;
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}
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if ((cbb->fabric->firewall_ctl > FIREWALL_APERTURE_SZ) ||
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(cbb->fabric->firewall_wr_ctl > FIREWALL_APERTURE_SZ)) {
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dev_err(&pdev->dev, "wrong firewall offset value\n");
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return false;
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}
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val = readl(cbb->regs + cbb->fabric->firewall_base + cbb->fabric->firewall_ctl);
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/*
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* If the firewall check feature for allowing or blocking the
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* write accesses through the firewall of a fabric is disabled
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* then CCPLEX can write to the registers of that fabric.
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*/
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if (!(val & WEN))
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return true;
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/*
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* If the firewall check is enabled then check whether CCPLEX
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* has write access to the fabric's error notifier registers
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*/
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val = readl(cbb->regs + cbb->fabric->firewall_base + cbb->fabric->firewall_wr_ctl);
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if (val & (BIT(CCPLEX_MSTRID)))
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return true;
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return false;
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}
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static void tegra234_cbb_fault_enable(struct tegra_cbb *cbb)
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{
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struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
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@ -551,7 +597,7 @@ static irqreturn_t tegra234_cbb_isr(int irq, void *data)
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*/
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if (priv->fabric->off_mask_erd) {
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mstr_id = FIELD_GET(USRBITS_MSTR_ID, priv->mn_user_bits);
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if (mstr_id == 0x1)
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if (mstr_id == CCPLEX_MSTRID)
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is_inband_err = 1;
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}
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}
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@ -665,6 +711,9 @@ static const struct tegra234_cbb_fabric tegra234_aon_fabric = {
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.errors = tegra234_cbb_errors,
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.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
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.notifier_offset = 0x17000,
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.firewall_base = 0x30000,
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.firewall_ctl = 0x8d0,
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.firewall_wr_ctl = 0x8c8,
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};
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static const struct tegra234_slave_lookup tegra234_bpmp_slave_map[] = {
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@ -683,6 +732,9 @@ static const struct tegra234_cbb_fabric tegra234_bpmp_fabric = {
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.errors = tegra234_cbb_errors,
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.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
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.notifier_offset = 0x19000,
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.firewall_base = 0x30000,
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.firewall_ctl = 0x8f0,
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.firewall_wr_ctl = 0x8e8,
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};
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static const struct tegra234_slave_lookup tegra234_cbb_slave_map[] = {
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@ -757,7 +809,10 @@ static const struct tegra234_cbb_fabric tegra234_cbb_fabric = {
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.errors = tegra234_cbb_errors,
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.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
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.notifier_offset = 0x60000,
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.off_mask_erd = 0x3a004
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.off_mask_erd = 0x3a004,
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.firewall_base = 0x10000,
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.firewall_ctl = 0x23f0,
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.firewall_wr_ctl = 0x23e8,
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};
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static const struct tegra234_slave_lookup tegra234_common_slave_map[] = {
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@ -777,6 +832,9 @@ static const struct tegra234_cbb_fabric tegra234_dce_fabric = {
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.errors = tegra234_cbb_errors,
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.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
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.notifier_offset = 0x19000,
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.firewall_base = 0x30000,
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.firewall_ctl = 0x290,
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.firewall_wr_ctl = 0x288,
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};
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static const struct tegra234_cbb_fabric tegra234_rce_fabric = {
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@ -787,6 +845,9 @@ static const struct tegra234_cbb_fabric tegra234_rce_fabric = {
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.errors = tegra234_cbb_errors,
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.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
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.notifier_offset = 0x19000,
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.firewall_base = 0x30000,
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.firewall_ctl = 0x290,
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.firewall_wr_ctl = 0x288,
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};
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static const struct tegra234_cbb_fabric tegra234_sce_fabric = {
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@ -797,6 +858,9 @@ static const struct tegra234_cbb_fabric tegra234_sce_fabric = {
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.errors = tegra234_cbb_errors,
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.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
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.notifier_offset = 0x19000,
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.firewall_base = 0x30000,
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.firewall_ctl = 0x290,
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.firewall_wr_ctl = 0x288,
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};
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static const char * const tegra241_master_id[] = {
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@ -979,6 +1043,9 @@ static const struct tegra234_cbb_fabric tegra241_cbb_fabric = {
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.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
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.notifier_offset = 0x60000,
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.off_mask_erd = 0x40004,
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.firewall_base = 0x20000,
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.firewall_ctl = 0x2370,
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.firewall_wr_ctl = 0x2368,
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};
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static const struct tegra234_slave_lookup tegra241_bpmp_slave_map[] = {
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@ -1000,6 +1067,9 @@ static const struct tegra234_cbb_fabric tegra241_bpmp_fabric = {
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.errors = tegra241_cbb_errors,
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.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
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.notifier_offset = 0x19000,
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.firewall_base = 0x30000,
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.firewall_ctl = 0x8f0,
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.firewall_wr_ctl = 0x8e8,
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};
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static const struct of_device_id tegra234_cbb_dt_ids[] = {
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@ -1084,6 +1154,15 @@ static int tegra234_cbb_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, cbb);
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/*
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* Don't enable error reporting for a Fabric if write to it's registers
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* is blocked by CBB firewall.
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*/
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if (!tegra234_cbb_write_access_allowed(pdev, cbb)) {
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dev_info(&pdev->dev, "error reporting not enabled due to firewall\n");
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return 0;
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}
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spin_lock_irqsave(&cbb_lock, flags);
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list_add(&cbb->base.node, &cbb_list);
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spin_unlock_irqrestore(&cbb_lock, flags);
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