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arm64: dts: qcom: msm8992: Add a proper CPU map

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This commit adds cpu nodes for all 6 cores
present on this SoC and the cpu-map.

Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200625182118.131476-6-konradybcio@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Konrad Dybcio 2020-06-25 20:21:09 +02:00 committed by Bjorn Andersson
parent d54df2210d
commit 2912215f53
1 changed files with 75 additions and 7 deletions
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82
arch/arm64/boot/dts/qcom/msm8992.dtsi
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@ -16,24 +16,92 @@
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
};
};
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CPU4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
next-level-cache = <&L2_1>;
enable-method = "psci";
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
CPU5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
next-level-cache = <&L2_1>;
enable-method = "psci";
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
};
};
};
clocks {