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dt-bindings: memory: lpddr3: convert to dtschema
Convert the LPDDR3 memory bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220206135807.211767-4-krzysztof.kozlowski@canonical.com
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Krzysztof Kozlowski
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
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maintainers:
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- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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properties:
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compatible:
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items:
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- enum:
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- samsung,K3QF2F20DB
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- const: jedec,lpddr3
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'#address-cells':
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const: 1
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density:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Density in megabits of SDRAM chip.
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enum:
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- 4096
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- 8192
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- 16384
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- 32768
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io-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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IO bus width in bits of SDRAM chip.
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enum:
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- 64
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- 32
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- 16
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- 8
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manufacturer-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Manufacturer ID value read from Mode Register 5.
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revision-id:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 2
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maxItems: 2
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items:
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maximum: 255
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description: |
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Revision value of SDRAM chip read from Mode Registers 6 and 7.
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'#size-cells':
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const: 0
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tCKE-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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description: |
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CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
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of clock cycles.
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tCKESR-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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description: |
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CKE minimum pulse width during SELF REFRESH (low pulse width during
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SELF REFRESH) in terms of number of clock cycles.
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tDQSCK-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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description: |
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DQS output data access time from CK_t/CK_c in terms of number of clock
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cycles.
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tFAW-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 63
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description: |
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Four-bank activate window in terms of number of clock cycles.
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tMRD-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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description: |
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Mode register set command delay in terms of number of clock cycles.
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tR2R-C2C-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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description: |
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Additional READ-to-READ delay in chip-to-chip cases in terms of number
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of clock cycles.
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tRAS-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 63
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description: |
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Row active time in terms of number of clock cycles.
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tRC-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 63
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description: |
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ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
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tRCD-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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description: |
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RAS-to-CAS delay in terms of number of clock cycles.
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tRFC-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 255
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description: |
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Refresh Cycle time in terms of number of clock cycles.
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tRL-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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description: |
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READ data latency in terms of number of clock cycles.
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tRPab-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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description: |
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Row precharge time (all banks) in terms of number of clock cycles.
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tRPpb-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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description: |
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Row precharge time (single banks) in terms of number of clock cycles.
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tRRD-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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description: |
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Active bank A to active bank B in terms of number of clock cycles.
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tRTP-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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description: |
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Internal READ to PRECHARGE command delay in terms of number of clock
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cycles.
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tW2W-C2C-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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description: |
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Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
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of clock cycles.
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tWL-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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description: |
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WRITE data latency in terms of number of clock cycles.
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tWR-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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description: |
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WRITE recovery time in terms of number of clock cycles.
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tWTR-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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description: |
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Internal WRITE-to-READ command delay in terms of number of clock cycles.
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tXP-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 255
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description: |
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Exit power-down to next valid command delay in terms of number of clock
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cycles.
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tXSR-min-tck:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 1023
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description: |
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SELF REFRESH exit to next valid command delay in terms of number of clock
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cycles.
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patternProperties:
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"^timings@[0-9a-f]+$":
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$ref: jedec,lpddr3-timings.yaml
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description: |
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The lpddr3 node may have one or more child nodes with timings.
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Each timing node provides AC timing parameters of the device for a given
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speed-bin. The user may provide the timings for as many speed-bins as is
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required.
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required:
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- compatible
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- '#address-cells'
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- density
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- io-width
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- '#size-cells'
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additionalProperties: false
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examples:
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- |
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lpddr3 {
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compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
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density = <16384>;
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io-width = <32>;
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#address-cells = <1>;
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#size-cells = <0>;
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tCKE-min-tck = <2>;
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tCKESR-min-tck = <2>;
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tDQSCK-min-tck = <5>;
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tFAW-min-tck = <5>;
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tMRD-min-tck = <5>;
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tR2R-C2C-min-tck = <0>;
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tRAS-min-tck = <5>;
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tRC-min-tck = <6>;
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tRCD-min-tck = <3>;
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tRFC-min-tck = <17>;
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tRL-min-tck = <14>;
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tRPab-min-tck = <2>;
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tRPpb-min-tck = <2>;
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tRRD-min-tck = <2>;
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tRTP-min-tck = <2>;
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tW2W-C2C-min-tck = <0>;
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tWL-min-tck = <8>;
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tWR-min-tck = <7>;
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tWTR-min-tck = <2>;
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tXP-min-tck = <2>;
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tXSR-min-tck = <12>;
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timings@800000000 {
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compatible = "jedec,lpddr3-timings";
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reg = <800000000>;
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min-freq = <100000000>;
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tCKE = <3750>;
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tCKESR = <3750>;
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tFAW = <25000>;
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tMRD = <7000>;
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tR2R-C2C = <0>;
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tRAS = <23000>;
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tRC = <33750>;
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tRCD = <10000>;
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tRFC = <65000>;
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tRPab = <12000>;
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tRPpb = <12000>;
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tRRD = <6000>;
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tRTP = <3750>;
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tW2W-C2C = <0>;
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tWR = <7500>;
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tWTR = <3750>;
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tXP = <3750>;
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tXSR = <70000>;
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};
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};
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@ -1,107 +0,0 @@
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* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
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Required properties:
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- compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3".
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Example "<vendor>,<type>" values:
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"samsung,K3QF2F20DB"
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- density : <u32> representing density in Mb (Mega bits)
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- io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64
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- #address-cells: Must be set to 1
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- #size-cells: Must be set to 0
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Optional properties:
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- manufacturer-id : <u32> Manufacturer ID value read from Mode Register 5
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- revision-id : <u32 u32> Revision IDs read from Mode Registers 6 and 7
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The following optional properties represent the minimum value of some AC
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timing parameters of the DDR device in terms of number of clock cycles.
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These values shall be obtained from the device data-sheet.
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- tRFC-min-tck
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- tRRD-min-tck
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- tRPab-min-tck
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- tRPpb-min-tck
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- tRCD-min-tck
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- tRC-min-tck
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- tRAS-min-tck
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- tWTR-min-tck
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- tWR-min-tck
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- tRTP-min-tck
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- tW2W-C2C-min-tck
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- tR2R-C2C-min-tck
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- tWL-min-tck
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- tDQSCK-min-tck
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- tRL-min-tck
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- tFAW-min-tck
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- tXSR-min-tck
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- tXP-min-tck
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- tCKE-min-tck
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- tCKESR-min-tck
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- tMRD-min-tck
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Child nodes:
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- The lpddr3 node may have one or more child nodes of type "lpddr3-timings".
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"lpddr3-timings" provides AC timing parameters of the device for
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a given speed-bin. Please see
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Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt
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for more information on "lpddr3-timings"
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Example:
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samsung_K3QF2F20DB: lpddr3 {
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compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
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density = <16384>;
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io-width = <32>;
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manufacturer-id = <1>;
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revision-id = <123 234>;
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#address-cells = <1>;
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#size-cells = <0>;
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tRFC-min-tck = <17>;
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tRRD-min-tck = <2>;
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tRPab-min-tck = <2>;
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tRPpb-min-tck = <2>;
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tRCD-min-tck = <3>;
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tRC-min-tck = <6>;
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tRAS-min-tck = <5>;
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tWTR-min-tck = <2>;
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tWR-min-tck = <7>;
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tRTP-min-tck = <2>;
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tW2W-C2C-min-tck = <0>;
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tR2R-C2C-min-tck = <0>;
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tWL-min-tck = <8>;
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tDQSCK-min-tck = <5>;
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tRL-min-tck = <14>;
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tFAW-min-tck = <5>;
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tXSR-min-tck = <12>;
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tXP-min-tck = <2>;
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tCKE-min-tck = <2>;
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tCKESR-min-tck = <2>;
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tMRD-min-tck = <5>;
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timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
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compatible = "jedec,lpddr3-timings";
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/* workaround: 'reg' shows max-freq */
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reg = <800000000>;
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min-freq = <100000000>;
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tRFC = <65000>;
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tRRD = <6000>;
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tRPab = <12000>;
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tRPpb = <12000>;
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tRCD = <10000>;
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tRC = <33750>;
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tRAS = <23000>;
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tWTR = <3750>;
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tWR = <7500>;
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tRTP = <3750>;
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tW2W-C2C = <0>;
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tR2R-C2C = <0>;
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tFAW = <25000>;
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tXSR = <70000>;
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tXP = <3750>;
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tCKE = <3750>;
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tCKESR = <3750>;
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tMRD = <7000>;
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};
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}
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@ -51,8 +51,7 @@ properties:
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$ref: '/schemas/types.yaml#/definitions/phandle'
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description: |
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phandle of the connected DRAM memory device. For more information please
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refer to documentation file:
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Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt
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refer to jedec,lpddr3.yaml.
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operating-points-v2: true
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