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drm for 6.13-rc1

Browse Source 
core:
 - split DSC helpers from DP helpers
 - clang build fixes for drm/mm test
 - drop simple pipeline support for gem vram
 - document submission error signaling
 - move drm_rect to drm core module from kms helper
 - add default client setup to most drivers
 - move to video aperture helpers instead of drm ones
 
 tests:
 - new framebuffer tests
 
 ttm:
 - remove swapped and pinned BOs from TTM lru
 
 panic:
 - fix uninit spinlock
 - add ABGR2101010 support
 
 bridge:
 - add TI TDP158 support
 - use standard PM OPS
 
 dma-fence:
 - use read_trylock instead of read_lock to help lockdep
 
 scheduler:
 - add errno to sched start to report different errors
 - add locking to drm_sched_entity_modify_sched
 - improve documentation
 
 xe:
 - add drm_line_printer
 - lots of refactoring
 - Enable Xe2 + PES disaggregation
 - add new ARL PCI ID
 - SRIOV development work
 - fix exec unnecessary implicit fence
 - define and parse OA sync props
 - forcewake refactoring
 
 i915:
 - Enable BMG/LNL ultra joiner
 - Enable 10bpx + CCS scanout on ICL+, fp16/CCS on TGL+
 - use DSB for plane/color mgmt
 - Arrow lake PCI IDs
 - lots of i915/xe display refactoring
 - enable PXP GuC autoteardown
 - Pantherlake (PTL) Xe3 LPD display enablement
 - Allow fastset HDR infoframe changes
 - write DP source OUI for non-eDP sinks
 - share PCI IDs between i915 and xe
 
 amdgpu:
 - SDMA queue reset support
 - SMU 13.0.6, JPEG 4.0.3 updates
 - Initial runtime repartitioning support
 - rework IP structs for multiple IP instances
 - Fetch EDID from _DDC if available
 - SMU13 zero rpm user control
 - lots of fixes/cleanups
 
 amdkfd:
 - Increase event FIFO size
 - add topology cap flag for per queue reset
 
 msm:
 - DPU:
 - SA8775P support
 - (disabled by default) MSM8917, MSM8937, MSM8953 and MSM8996 support
 - Enable large framebuffer support
 - Drop MSM8998 and SDM845
 - DP:
 - SA8775P support
 - GPU:
 - a7xx preemption support
 - Adreno A663 support
 
 ast:
 - warn about unsupported TX chips
 
 ivpu:
 - add coredump
 - add pantherlake support
 
 rockchip:
 - 4K@60Hz display enablement
 - generate pll programming tables
 
 panthor:
 - add timestamp query API
 - add realtime group priority
 - add fdinfo support
 
 etnaviv:
 - improve handling of DMA address limits
 - improve GPU hangcheck
 
 exynos:
 - Decon Exynos7870 support
 
 mediatek:
 - add OF graph support
 
 omap:
 - locking fixes
 
 bochs:
 - convert to gem/shmem from simpledrm
 
 v3d:
 - support big/super pages
 - add gemfs
 
 vc4:
 - BCM2712 support refactoring
 - add YUV444 format support
 
 udmabuf:
 - folio related fixes
 
 nouveau:
 - add panic support on nv50+
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Merge tag 'drm-next-2024-11-21' of https://gitlab.freedesktop.org/drm/kernel

Pull drm updates from Dave Airlie:
 "There's a lot of rework, the panic helper support is being added to
  more drivers, v3d gets support for HW superpages, scheduler
  documentation, drm client and video aperture reworks, some new
  MAINTAINERS added, amdgpu has the usual lots of IP refactors, Intel
  has some Pantherlake enablement and xe is getting some SRIOV bits, but
  just lots of stuff everywhere.

  core:
   - split DSC helpers from DP helpers
   - clang build fixes for drm/mm test
   - drop simple pipeline support for gem vram
   - document submission error signaling
   - move drm_rect to drm core module from kms helper
   - add default client setup to most drivers
   - move to video aperture helpers instead of drm ones

  tests:
   - new framebuffer tests

  ttm:
   - remove swapped and pinned BOs from TTM lru

  panic:
   - fix uninit spinlock
   - add ABGR2101010 support

  bridge:
   - add TI TDP158 support
   - use standard PM OPS

  dma-fence:
   - use read_trylock instead of read_lock to help lockdep

  scheduler:
   - add errno to sched start to report different errors
   - add locking to drm_sched_entity_modify_sched
   - improve documentation

  xe:
   - add drm_line_printer
   - lots of refactoring
   - Enable Xe2 + PES disaggregation
   - add new ARL PCI ID
   - SRIOV development work
   - fix exec unnecessary implicit fence
   - define and parse OA sync props
   - forcewake refactoring

  i915:
   - Enable BMG/LNL ultra joiner
   - Enable 10bpx + CCS scanout on ICL+, fp16/CCS on TGL+
   - use DSB for plane/color mgmt
   - Arrow lake PCI IDs
   - lots of i915/xe display refactoring
   - enable PXP GuC autoteardown
   - Pantherlake (PTL) Xe3 LPD display enablement
   - Allow fastset HDR infoframe changes
   - write DP source OUI for non-eDP sinks
   - share PCI IDs between i915 and xe

  amdgpu:
   - SDMA queue reset support
   - SMU 13.0.6, JPEG 4.0.3 updates
   - Initial runtime repartitioning support
   - rework IP structs for multiple IP instances
   - Fetch EDID from _DDC if available
   - SMU13 zero rpm user control
   - lots of fixes/cleanups

  amdkfd:
   - Increase event FIFO size
   - add topology cap flag for per queue reset

  msm:
   - DPU:
      - SA8775P support
      - (disabled by default) MSM8917, MSM8937, MSM8953 and MSM8996 support
      - Enable large framebuffer support
      - Drop MSM8998 and SDM845
   - DP:
      - SA8775P support
   - GPU:
      - a7xx preemption support
      - Adreno A663 support

  ast:
   - warn about unsupported TX chips

  ivpu:
   - add coredump
   - add pantherlake support

  rockchip:
   - 4K@60Hz display enablement
   - generate pll programming tables

  panthor:
   - add timestamp query API
   - add realtime group priority
   - add fdinfo support

  etnaviv:
   - improve handling of DMA address limits
   - improve GPU hangcheck

  exynos:
   - Decon Exynos7870 support

  mediatek:
   - add OF graph support

  omap:
   - locking fixes

  bochs:
   - convert to gem/shmem from simpledrm

  v3d:
   - support big/super pages
   - add gemfs

  vc4:
   - BCM2712 support refactoring
   - add YUV444 format support

  udmabuf:
   - folio related fixes

  nouveau:
   - add panic support on nv50+"

* tag 'drm-next-2024-11-21' of https://gitlab.freedesktop.org/drm/kernel: (1583 commits)
  drm/xe/guc: Fix dereference before NULL check
  drm/amd: Fix initialization mistake for NBIO 7.7.0
  Revert "drm/amd/display: parse umc_info or vram_info based on ASIC"
  drm/amd/display: Fix failure to read vram info due to static BP_RESULT
  drm/amdgpu: enable GTT fallback handling for dGPUs only
  drm/amd/amdgpu: limit single process inside MES
  drm/fourcc: add AMD_FMT_MOD_TILE_GFX9_4K_D_X
  drm/amdgpu/mes12: correct kiq unmap latency
  drm/amdgpu: Support vcn and jpeg error info parsing
  drm/amd : Update MES API header file for v11 & v12
  drm/amd/amdkfd: add/remove kfd queues on start/stop KFD scheduling
  drm/amdkfd: change kfd process kref count at creation
  drm/amdgpu: Cleanup shift coding style
  drm/amd/amdgpu: Increase MES log buffer to dump mes scratch data
  drm/amdgpu: Implement virt req_ras_err_count
  drm/amdgpu: VF Query RAS Caps from Host if supported
  drm/amdgpu: Add msg handlers for SRIOV RAS Telemetry
  drm/amdgpu: Update SRIOV Exchange Headers for RAS Telemetry Support
  drm/amd/display: 3.2.309
  drm/amd/display: Adjust VSDB parser for replay feature
  ...
This commit is contained in:
Linus Torvalds 2024-11-21 14:56:17 -08:00
commit 28eb75e178
1476 changed files with 51967 additions and 29006 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
View File

@ -83,3 +83,11 @@ Contact: intel-gfx@lists.freedesktop.org
Description: RO. Fan speed of device in RPM.
Only supported for particular Intel i915 graphics platforms.
What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/temp1_input
Date: November 2024
KernelVersion: 6.12
Contact: intel-gfx@lists.freedesktop.org
Description: RO. GPU package temperature in millidegree Celsius.
Only supported for particular Intel i915 graphics platforms.

10
Documentation/ABI/testing/sysfs-driver-panthor-profiling Normal file
View File

@ -0,0 +1,10 @@
What: /sys/bus/platform/drivers/panthor/.../profiling
Date: September 2024
KernelVersion: 6.11.0
Contact: Adrian Larumbe <adrian.larumbe@collabora.com>
Description:
Bitmask to enable drm fdinfo's job profiling measurements.
Valid values are:
0: Don't enable fdinfo job profiling sources.
1: Enable GPU cycle measurements for running jobs.
2: Enable GPU timestamp sampling for running jobs.

14
Documentation/accel/qaic/aic080.rst Normal file
View File

@ -0,0 +1,14 @@
.. SPDX-License-Identifier: GPL-2.0-only
===============================
Qualcomm Cloud AI 80 (AIC080)
===============================
Overview
========
The Qualcomm Cloud AI 80/AIC080 family of products are a derivative of AIC100.
The number of NSPs and clock rates are reduced to fit within resource
constrained solutions. The PCIe Product ID is 0xa080.
As a derivative product, all AIC100 documentation applies.

2
Documentation/accel/qaic/aic100.rst
View File

@ -229,6 +229,8 @@ of the defined channels, and their uses.
| _PERIODIC | | | timestamps in the device side logs with|
| | | | the host time source. |
+----------------+---------+----------+----------------------------------------+
| IPCR | 24 & 25 | AMSS | AF_QIPCRTR clients and servers. |
+----------------+---------+----------+----------------------------------------+
DMA Bridge
==========

1
Documentation/accel/qaic/index.rst
View File

@ -10,4 +10,5 @@ accelerator cards.
.. toctree::
qaic
aic080
aic100

250
Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml Normal file
View File

@ -0,0 +1,250 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ITE IT6263 LVDS to HDMI converter
maintainers:
- Liu Ying <victor.liu@nxp.com>
description: |
The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitter,
the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP
1.2 and backward compatible with DVI 1.0 specification.
The IT6263 also encodes and transmits up to 8 channels of I2S digital audio,
with sampling rate up to 192KHz and sample size up to 24 bits. In addition,
an S/PDIF input port takes in compressed audio of up to 192KHz frame rate.
The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is
provided by the IT6263 in two interfaces: the four I2S input ports or the
S/PDIF input port. With both interfaces the highest possible HBR frame rate
is supported at up to 768KHz.
allOf:
- $ref: /schemas/display/lvds-dual-ports.yaml#
properties:
compatible:
const: ite,it6263
reg:
maxItems: 1
clocks:
maxItems: 1
description: audio master clock
clock-names:
const: mclk
data-mapping:
enum:
- jeida-18
- jeida-24
- jeida-30
- vesa-24
- vesa-30
reset-gpios:
maxItems: 1
ivdd-supply:
description: 1.8V digital logic power
ovdd-supply:
description: 3.3V I/O pin power
txavcc18-supply:
description: 1.8V HDMI analog frontend power
txavcc33-supply:
description: 3.3V HDMI analog frontend power
pvcc1-supply:
description: 1.8V HDMI frontend core PLL power
pvcc2-supply:
description: 1.8V HDMI frontend filter PLL power
avcc-supply:
description: 3.3V LVDS frontend power
anvdd-supply:
description: 1.8V LVDS frontend analog power
apvdd-supply:
description: 1.8V LVDS frontend PLL power
"#sound-dai-cells":
const: 0
ite,i2s-audio-fifo-sources:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 4
items:
enum: [0, 1, 2, 3]
description:
Each array element indicates the pin number of an I2S serial data input
line which is connected to an audio FIFO, from audio FIFO0 to FIFO3.
ite,rl-channel-swap-audio-sources:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 4
uniqueItems: true
items:
enum: [0, 1, 2, 3]
description:
Each array element indicates an audio source whose right channel and left
channel are swapped by this converter. For I2S, the element is the pin
number of an I2S serial data input line. For S/PDIF, the element is always
0.
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0: true
port@1:
oneOf:
- required: [dual-lvds-odd-pixels]
- required: [dual-lvds-even-pixels]
port@2:
$ref: /schemas/graph.yaml#/properties/port
description: video port for the HDMI output
port@3:
$ref: /schemas/graph.yaml#/properties/port
description: sound input port
required:
- port@0
- port@2
required:
- compatible
- reg
- data-mapping
- ivdd-supply
- ovdd-supply
- txavcc18-supply
- txavcc33-supply
- pvcc1-supply
- pvcc2-supply
- avcc-supply
- anvdd-supply
- apvdd-supply
unevaluatedProperties: false
examples:
- |
/* single-link LVDS input */
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
hdmi@4c {
compatible = "ite,it6263";
reg = <0x4c>;
data-mapping = "jeida-24";
reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
ivdd-supply = <&reg_buck5>;
ovdd-supply = <&reg_vext_3v3>;
txavcc18-supply = <&reg_buck5>;
txavcc33-supply = <&reg_vext_3v3>;
pvcc1-supply = <&reg_buck5>;
pvcc2-supply = <&reg_buck5>;
avcc-supply = <&reg_vext_3v3>;
anvdd-supply = <&reg_buck5>;
apvdd-supply = <&reg_buck5>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
it6263_lvds_link1: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
port@2 {
reg = <2>;
it6263_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};
};
- |
/* dual-link LVDS input */
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
hdmi@4c {
compatible = "ite,it6263";
reg = <0x4c>;
data-mapping = "jeida-24";
reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
ivdd-supply = <&reg_buck5>;
ovdd-supply = <&reg_vext_3v3>;
txavcc18-supply = <&reg_buck5>;
txavcc33-supply = <&reg_vext_3v3>;
pvcc1-supply = <&reg_buck5>;
pvcc2-supply = <&reg_buck5>;
avcc-supply = <&reg_vext_3v3>;
anvdd-supply = <&reg_buck5>;
apvdd-supply = <&reg_buck5>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dual-lvds-odd-pixels;
it6263_lvds_link1_dual: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
port@1 {
reg = <1>;
dual-lvds-even-pixels;
it6263_lvds_link2_dual: endpoint {
remote-endpoint = <&ldb_lvds_ch1>;
};
};
port@2 {
reg = <2>;
it6263_out_dual: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};
};

15
Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml
View File

@ -81,9 +81,22 @@ properties:
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
unevaluatedProperties: false
$ref: /schemas/graph.yaml#/$defs/port-base
description: Parallel RGB input port
properties:
endpoint:
$ref: /schemas/graph.yaml#/$defs/endpoint-base
unevaluatedProperties: false
properties:
bus-width:
description:
Endpoint bus width.
enum: [ 16, 18, 24 ]
default: 24
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: HDMI output port

57
Documentation/devicetree/bindings/display/bridge/ti,tdp158.yaml Normal file
View File

@ -0,0 +1,57 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/ti,tdp158.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI TDP158 HDMI to TMDS Redriver
maintainers:
- Arnaud Vrac <avrac@freebox.fr>
- Pierre-Hugues Husson <phhusson@freebox.fr>
properties:
compatible:
const: ti,tdp158
# The reg property is required if and only if the device is connected
# to an I2C bus. In pin strap mode, reg must not be specified.
reg:
description: I2C address of the device
# Pin 36 = Operation Enable / Reset Pin
# OE = L: Power Down Mode
# OE = H: Normal Operation
# Internal weak pullup - device resets on H to L transitions
enable-gpios:
description: GPIO controlling bridge enable
vcc-supply:
description: Power supply 3.3V
vdd-supply:
description: Power supply 1.1V
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Bridge input
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Bridge output
required:
- port@0
- port@1
required:
- compatible
- vcc-supply
- vdd-supply
- ports
additionalProperties: false

4
Documentation/devicetree/bindings/display/bridge/toshiba,tc358768.yaml
View File

@ -60,6 +60,10 @@ properties:
data-lines:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 16, 18, 24 ]
deprecated: true
bus-width:
enum: [ 16, 18, 24 ]
port@1:
$ref: /schemas/graph.yaml#/properties/port

2
Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
View File

@ -119,7 +119,6 @@ Optional properties:
- interface-pix-fmt: How this display is connected to the
display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
and "lvds666".
- edid: verbatim EDID data block describing attached display.
- ddc: phandle describing the i2c bus handling the display data
channel
- port@[0-1]: Port nodes with endpoint definitions as defined in
@ -131,7 +130,6 @@ example:
disp0 {
compatible = "fsl,imx-parallel-display";
edid = [edid-data];
interface-pix-fmt = "rgb24";
port@0 {

1
Documentation/devicetree/bindings/display/imx/ldb.txt
View File

@ -62,7 +62,6 @@ Required properties:
display-timings are used instead.
Optional properties (required if display-timings are used):
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- display-timings : A node that describes the display timings as defined in
Documentation/devicetree/bindings/display/panel/display-timing.txt.
- fsl,data-mapping : should be "spwg" or "jeida"

31
Documentation/devicetree/bindings/display/lvds-data-mapping.yaml
View File

@ -26,12 +26,17 @@ description: |
Device compatible with those specifications have been marketed under the
FPD-Link and FlatLink brands.
This bindings also supports 30-bit data mapping compatible with JEIDA and
VESA.
properties:
data-mapping:
enum:
- jeida-18
- jeida-24
- jeida-30
- vesa-24
- vesa-30
description: |
The color signals mapping order.
@ -60,6 +65,19 @@ properties:
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
- "jeida-30" - 30-bit data mapping compatible with JEIDA and VESA. Data
are transferred as follows on 5 LVDS lanes.
Slot 0 1 2 3 4 5 6
________________ _________________
Clock \_______________________/
______ ______ ______ ______ ______ ______ ______
DATA0 ><__G4__><__R9__><__R8__><__R7__><__R6__><__R5__><__R4__><
DATA1 ><__B5__><__B4__><__G9__><__G8__><__G7__><__G6__><__G5__><
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B9__><__B8__><__B7__><__B6__><
DATA3 ><_CTL3_><__B3__><__B2__><__G3__><__G2__><__R3__><__R2__><
DATA4 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
- "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
Data are transferred as follows on 4 LVDS lanes.
@ -72,6 +90,19 @@ properties:
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
- "vesa-30" - 30-bit data mapping compatible with VESA. Data are
transferred as follows on 5 LVDS lanes.
Slot 0 1 2 3 4 5 6
________________ _________________
Clock \_______________________/
______ ______ ______ ______ ______ ______ ______
DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
DATA4 ><_CTL3_><__B9__><__B8__><__G9__><__G8__><__R9__><__R8__><
Control signals are mapped as follows.
CTL0: HSync

63
Documentation/devicetree/bindings/display/lvds-dual-ports.yaml Normal file
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@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/lvds-dual-ports.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Dual-link LVDS Display Common Properties
maintainers:
- Liu Ying <victor.liu@nxp.com>
description: |
Common properties for LVDS displays with dual LVDS links. Extend LVDS display
common properties defined in lvds.yaml.
Dual-link LVDS displays receive odd pixels and even pixels separately from
the dual LVDS links. One link receives odd pixels and the other receives
even pixels. Some of those displays may also use only one LVDS link to
receive all pixels, being odd and even agnostic.
allOf:
- $ref: lvds.yaml#
properties:
ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port@[01]$':
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: |
port@0 represents the first LVDS input link.
port@1 represents the second LVDS input link.
properties:
dual-lvds-odd-pixels:
type: boolean
description: LVDS input link for odd pixels
dual-lvds-even-pixels:
type: boolean
description: LVDS input link for even pixels
oneOf:
- required: [dual-lvds-odd-pixels]
- required: [dual-lvds-even-pixels]
- properties:
dual-lvds-odd-pixels: false
dual-lvds-even-pixels: false
anyOf:
- required:
- port@0
- required:
- port@1
required:
- ports
additionalProperties: true
...

40
Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
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@ -62,6 +62,27 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: AAL input port
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
AAL output to the next component's input, for example could be one
of many gamma, overdrive or other blocks.
required:
- port@0
- port@1
required:
- compatible
- reg
@ -89,5 +110,24 @@ examples:
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_AAL>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
aal0_in: endpoint {
remote-endpoint = <&ccorr0_out>;
};
};
port@1 {
reg = <1>;
aal0_out: endpoint {
remote-endpoint = <&gamma0_in>;
};
};
};
};
};

21
Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
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@ -57,6 +57,27 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: CCORR input port
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
CCORR output to the input of the next desired component in the
display pipeline, usually only one of the available AAL blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

22
Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
View File

@ -65,6 +65,28 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: COLOR input port
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
COLOR output to the input of the next desired component in the
display pipeline, for example one of the available CCORR or AAL
blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

22
Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
View File

@ -56,6 +56,28 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: DITHER input, usually from a POSTMASK or GAMMA block.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
DITHER output to the input of the next desired component in the
display pipeline, for example one of the available DSC compressors,
DP_INTF, DSI, LVDS or others.
required:
- port@0
- port@1
required:
- compatible
- reg

25
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
View File

@ -81,13 +81,34 @@ properties:
Output port node. This port should be connected to the input port of an
attached HDMI, LVDS or DisplayPort encoder chip.
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: DPI input port
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: DPI output to an HDMI, LVDS or DisplayPort encoder input
required:
- port@0
- port@1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- port
oneOf:
- required:
- port
- required:
- ports
additionalProperties: false
@ -96,7 +117,7 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
dpi0: dpi@1401d000 {
dpi: dpi@1401d000 {
compatible = "mediatek,mt8173-dpi";
reg = <0x1401d000 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;

24
Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
View File

@ -49,6 +49,30 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
Display Stream Compression input, usually from one of the DITHER
or MERGE blocks.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
Display Stream Compression output to the input of the next desired
component in the display pipeline, for example to MERGE, DP_INTF,
DPI or DSI.
required:
- port@0
- port@1
required:
- compatible
- reg

27
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
View File

@ -77,6 +77,26 @@ properties:
Output port node. This port should be connected to the input
port of an attached DSI panel or DSI-to-eDP encoder chip.
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input ports can have multiple endpoints, each of those connects
to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: DSI input port, usually from DITHER, DSC or MERGE
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
DSI output to an attached DSI panel, or a DSI-to-X encoder chip
required:
- port@0
- port@1
required:
- compatible
- reg
@ -86,7 +106,12 @@ required:
- clock-names
- phys
- phy-names
- port
oneOf:
- required:
- port
- required:
- ports
unevaluatedProperties: false

22
Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
View File

@ -110,6 +110,28 @@ properties:
include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display
function block.
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: ETHDR input, usually from one of the MERGE blocks.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
ETHDR output to the input of the next desired component in the
display pipeline, for example one of the available MERGE blocks,
or others.
required:
- port@0
- port@1
required:
- compatible
- reg

19
Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
View File

@ -65,6 +65,25 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: GAMMA input, usually from one of the AAL blocks.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
GAMMA output to the input of the next desired component in the
display pipeline, for example one of the available DITHER or
POSTMASK blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

23
Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
View File

@ -77,6 +77,29 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
MERGE input port, usually from DITHER, DPI, DSC, DSI, MDP_RDMA,
ETHDR or even from a different MERGE block
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
MERGE output to a DSC, DPI, DP_INTF, DSI, ETHDR, Write DMA, or
a different MERGE block, or others.
required:
- port@0
- port@1
resets:
description: reset controller
See Documentation/devicetree/bindings/reset/reset.txt for details.

22
Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
View File

@ -38,6 +38,28 @@ properties:
items:
- description: OD Clock
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: OD input port, usually from an AAL block
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
OD output to the input of the next desired component in the
display pipeline, for example one of the available RDMA or
other blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

22
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
View File

@ -57,6 +57,28 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: OVL input port from MMSYS, VDOSYS or other OVLs
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
OVL output to the input of the next desired component in the
display pipeline, for example one of the available COLOR, RDMA
or WDMA blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

22
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
View File

@ -75,6 +75,28 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: OVL input port from MMSYS or one of multiple VDOSYS
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
OVL output to the input of the next desired component in the
display pipeline, for example one of the available COLOR, RDMA
or WDMA blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

21
Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
View File

@ -52,6 +52,27 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: POSTMASK input port, usually from GAMMA
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
POSTMASK output to the input of the next desired component in the
display pipeline, for example one of the available DITHER blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

22
Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
View File

@ -87,6 +87,28 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: RDMA input port, usually from MMSYS, OD or OVL
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
RDMA output to the input of the next desired component in the
display pipeline, for example one of the available COLOR, DPI,
DSI, MERGE or UFOE blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

21
Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
View File

@ -43,6 +43,27 @@ properties:
items:
- description: UFOe Clock
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: UFOE input, usually from one of the RDMA blocks.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
UFOE output to the input of the next desired component in the
display pipeline, usually one of the available DSI blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

1
Documentation/devicetree/bindings/display/msm/dp-controller.yaml
View File

@ -17,6 +17,7 @@ properties:
compatible:
oneOf:
- enum:
- qcom,sa8775p-dp
- qcom,sc7180-dp
- qcom,sc7280-dp
- qcom,sc7280-edp

1
Documentation/devicetree/bindings/display/msm/gmu.yaml
View File

@ -125,6 +125,7 @@ allOf:
enum:
- qcom,adreno-gmu-635.0
- qcom,adreno-gmu-660.1
- qcom,adreno-gmu-663.0
then:
properties:
reg:

241
Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml Normal file
View File

@ -0,0 +1,241 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. SA87755P Display MDSS
maintainers:
- Mahadevan <quic_mahap@quicinc.com>
description:
SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
DPU display controller, DP interfaces and EDP etc.
$ref: /schemas/display/msm/mdss-common.yaml#
properties:
compatible:
const: qcom,sa8775p-mdss
clocks:
items:
- description: Display AHB
- description: Display hf AXI
- description: Display core
iommus:
maxItems: 1
interconnects:
maxItems: 3
interconnect-names:
maxItems: 3
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sa8775p-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
- const: qcom,sa8775p-dp
required:
- compatible
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-subsystem@ae00000 {
compatible = "qcom,sa8775p-mdss";
reg = <0x0ae00000 0x1000>;
reg-names = "mdss";
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
<&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
interconnect-names = "mdp0-mem",
"mdp1-mem",
"cpu-cfg";
resets = <&dispcc_core_bcr>;
power-domains = <&dispcc_gdsc>;
clocks = <&dispcc_ahb_clk>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc_mdp_clk>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
iommus = <&apps_smmu 0x1000 0x402>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
display-controller@ae01000 {
compatible = "qcom,sa8775p-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc_ahb_clk>,
<&dispcc_mdp_lut_clk>,
<&dispcc_mdp_clk>,
<&dispcc_mdp_vsync_clk>;
clock-names = "nrt_bus",
"iface",
"lut",
"core",
"vsync";
assigned-clocks = <&dispcc_mdp_vsync_clk>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdss0_mdp_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss0>;
interrupts = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf0_out: endpoint {
remote-endpoint = <&mdss0_dp0_in>;
};
};
};
mdss0_mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-375000000 {
opp-hz = /bits/ 64 <375000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
required-opps = <&rpmhpd_opp_nom>;
};
opp-575000000 {
opp-hz = /bits/ 64 <575000000>;
required-opps = <&rpmhpd_opp_turbo>;
};
opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
required-opps = <&rpmhpd_opp_turbo_l1>;
};
};
};
displayport-controller@af54000 {
compatible = "qcom,sa8775p-dp";
pinctrl-0 = <&dp_hot_plug_det>;
pinctrl-names = "default";
reg = <0xaf54000 0x104>,
<0xaf54200 0x0c0>,
<0xaf55000 0x770>,
<0xaf56000 0x09c>;
interrupt-parent = <&mdss0>;
interrupts = <12>;
clocks = <&dispcc_mdss_ahb_clk>,
<&dispcc_dptx0_aux_clk>,
<&dispcc_dptx0_link_clk>,
<&dispcc_dptx0_link_intf_clk>,
<&dispcc_dptx0_pixel0_clk>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
<&dispcc_mdss_dptx0_pixel0_clk_src>;
assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>;
phys = <&mdss0_edp_phy>;
phy-names = "dp";
operating-points-v2 = <&dp_opp_table>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#sound-dai-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss0_dp0_in: endpoint {
remote-endpoint = <&dpu_intf0_out>;
};
};
port@1 {
reg = <1>;
mdss0_dp_out: endpoint { };
};
};
dp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-810000000 {
opp-hz = /bits/ 64 <810000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
};
...

10
Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml
View File

@ -7,13 +7,21 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU on SC7280
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Neil Armstrong <neil.armstrong@linaro.org>
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
- Krishna Manikandan <quic_mkrishn@quicinc.com>
$ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
const: qcom,sc7280-dpu
enum:
- qcom,sc7280-dpu
- qcom,sc8280xp-dpu
- qcom,sm8350-dpu
- qcom,sm8450-dpu
- qcom,sm8550-dpu
reg:
items:

122
Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml
View File

@ -1,122 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SC8280XP Display Processing Unit
maintainers:
- Bjorn Andersson <andersson@kernel.org>
description:
Device tree bindings for SC8280XP Display Processing Unit.
$ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
const: qcom,sc8280xp-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for vbif register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display hf axi clock
- description: Display sf axi clock
- description: Display ahb clock
- description: Display lut clock
- description: Display core clock
- description: Display vsync clock
clock-names:
items:
- const: bus
- const: nrt_bus
- const: iface
- const: lut
- const: core
- const: vsync
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-controller@ae01000 {
compatible = "qcom,sc8280xp-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&gcc GCC_DISP_SF_AXI_CLK>,
<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
<&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc0 DISP_CC_MDSS_MDP_CLK>,
<&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus",
"nrt_bus",
"iface",
"lut",
"core",
"vsync";
assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
<&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <460000000>,
<19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SC8280XP_MMCX>;
interrupt-parent = <&mdss0>;
interrupts = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&mdss0_dp0_in>;
};
};
port@4 {
reg = <4>;
endpoint {
remote-endpoint = <&mdss0_dp1_in>;
};
};
port@5 {
reg = <5>;
endpoint {
remote-endpoint = <&mdss0_dp3_in>;
};
};
port@6 {
reg = <6>;
endpoint {
remote-endpoint = <&mdss0_dp2_in>;
};
};
};
};
...

4
Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml
View File

@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
const: qcom,sm8150-dpu
enum:
- qcom,sm8150-dpu
- qcom,sm8250-dpu
reg:
items:

99
Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml
View File

@ -1,99 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8250 Display DPU
maintainers:
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
$ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
const: qcom,sm8250-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for vbif register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display ahb clock
- description: Display hf axi clock
- description: Display core clock
- description: Display vsync clock
clock-names:
items:
- const: iface
- const: bus
- const: core
- const: vsync
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
display-controller@ae01000 {
compatible = "qcom,sm8250-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "iface", "bus", "core", "vsync";
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
};
...

120
Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
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@ -1,120 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8350 Display DPU
maintainers:
- Robert Foss <robert.foss@linaro.org>
$ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
const: qcom,sm8350-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for vbif register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display hf axi clock
- description: Display sf axi clock
- description: Display ahb clock
- description: Display lut clock
- description: Display core clock
- description: Display vsync clock
clock-names:
items:
- const: bus
- const: nrt_bus
- const: iface
- const: lut
- const: core
- const: vsync
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
display-controller@ae01000 {
compatible = "qcom,sm8350-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&gcc GCC_DISP_SF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus",
"nrt_bus",
"iface",
"lut",
"core",
"vsync";
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-345000000 {
opp-hz = /bits/ 64 <345000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-460000000 {
opp-hz = /bits/ 64 <460000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
...

139
Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml
View File

@ -1,139 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8450 Display DPU
maintainers:
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
$ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
const: qcom,sm8450-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for vbif register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display hf axi
- description: Display sf axi
- description: Display ahb
- description: Display lut
- description: Display core
- description: Display vsync
clock-names:
items:
- const: bus
- const: nrt_bus
- const: iface
- const: lut
- const: core
- const: vsync
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm8450-dispcc.h>
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sm8450.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
display-controller@ae01000 {
compatible = "qcom,sm8450-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&gcc GCC_DISP_SF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus",
"nrt_bus",
"iface",
"lut",
"core",
"vsync";
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf2_out: endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-172000000{
opp-hz = /bits/ 64 <172000000>;
required-opps = <&rpmhpd_opp_low_svs_d1>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-325000000 {
opp-hz = /bits/ 64 <325000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-375000000 {
opp-hz = /bits/ 64 <375000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
...

133
Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml
View File

@ -1,133 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8550 Display DPU
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
$ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
const: qcom,sm8550-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for vbif register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display AHB
- description: Display hf axi
- description: Display MDSS ahb
- description: Display lut
- description: Display core
- description: Display vsync
clock-names:
items:
- const: bus
- const: nrt_bus
- const: iface
- const: lut
- const: core
- const: vsync
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm8550-dispcc.h>
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
display-controller@ae01000 {
compatible = "qcom,sm8550-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus",
"nrt_bus",
"iface",
"lut",
"core",
"vsync";
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf2_out: endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-325000000 {
opp-hz = /bits/ 64 <325000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-375000000 {
opp-hz = /bits/ 64 <375000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-514000000 {
opp-hz = /bits/ 64 <514000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
...

1
Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
View File

@ -14,6 +14,7 @@ $ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
enum:
- qcom,sa8775p-dpu
- qcom,sm8650-dpu
- qcom,x1e80100-dpu

14
Documentation/devicetree/bindings/display/panel/advantech,idk-2121wr.yaml
View File

@ -20,6 +20,7 @@ description: |
dual-lvds-odd-pixels or dual-lvds-even-pixels).
allOf:
- $ref: /schemas/display/lvds-dual-ports.yaml#
- $ref: panel-common.yaml#
properties:
@ -44,22 +45,10 @@ properties:
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: The sink for odd pixels.
properties:
dual-lvds-odd-pixels: true
required:
- dual-lvds-odd-pixels
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: The sink for even pixels.
properties:
dual-lvds-even-pixels: true
required:
- dual-lvds-even-pixels
@ -75,7 +64,6 @@ required:
- height-mm
- data-mapping
- panel-timing
- ports
examples:
- |+

8
Documentation/devicetree/bindings/display/panel/panel-common.yaml
View File

@ -51,6 +51,14 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 90, 180, 270]
flip-horizontal:
description: boolean to flip image horizontally
type: boolean
flip-vertical:
description: boolean to flip image vertically
type: boolean
# Display Timings
panel-timing:
description:

2
Documentation/devicetree/bindings/display/panel/panel-lvds.yaml
View File

@ -50,6 +50,8 @@ properties:
- hannstar,hsd101pww2
# Hydis Technologies 7" WXGA (800x1280) TFT LCD LVDS panel
- hydis,hv070wx2-1e0
# Jenson Display BL-JT60050-01A 7" WSVGA (1024x600) color TFT LCD LVDS panel
- jenson,bl-jt60050-01a
- tbs,a711-panel
- const: panel-lvds

20
Documentation/devicetree/bindings/display/panel/panel-simple-lvds-dual-ports.yaml
View File

@ -22,6 +22,7 @@ description: |
If the panel is more advanced a dedicated binding file is required.
allOf:
- $ref: /schemas/display/lvds-dual-ports.yaml#
- $ref: panel-common.yaml#
properties:
@ -55,28 +56,10 @@ properties:
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: The first sink port.
properties:
dual-lvds-odd-pixels:
type: boolean
description: The first sink port for odd pixels.
required:
- dual-lvds-odd-pixels
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: The second sink port.
properties:
dual-lvds-even-pixels:
type: boolean
description: The second sink port for even pixels.
required:
- dual-lvds-even-pixels
@ -88,7 +71,6 @@ unevaluatedProperties: false
required:
- compatible
- ports
- power-supply
examples:

2
Documentation/devicetree/bindings/display/panel/panel-simple.yaml
View File

@ -200,6 +200,8 @@ properties:
- logictechno,lttd800480070-l2rt
# Logic Technologies LTTD800480070-L6WH-RT 7” 800x480 TFT Resistive Touch Module
- logictechno,lttd800480070-l6wh-rt
# Microchip AC69T88A 5" 800X480 LVDS interface TFT LCD Panel
- microchip,ac69t88a
# Mitsubishi "AA070MC01 7.0" WVGA TFT LCD panel
- mitsubishi,aa070mc01-ca1
# Mitsubishi AA084XE01 8.4" XGA TFT LCD panel

79
Documentation/devicetree/bindings/display/panel/samsung,ams581vf01.yaml Normal file
View File

@ -0,0 +1,79 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/samsung,ams581vf01.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung AMS581VF01 SOFEF01-based 5.81" 1080x2340 MIPI-DSI Panel
maintainers:
- Danila Tikhonov <danila@jiaxyga.com>
description:
The Samsung AMS581VF01 is a 5.81 inch 1080x2340 MIPI-DSI CMD mode OLED panel.
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
const: samsung,ams581vf01
reg:
maxItems: 1
vdd3p3-supply:
description: 3.3V source voltage rail
vddio-supply:
description: I/O source voltage rail
vsn-supply:
description: Negative source voltage rail
vsp-supply:
description: Positive source voltage rail
reset-gpios: true
port: true
required:
- compatible
- reg
- vdd3p3-supply
- vddio-supply
- vsn-supply
- vsp-supply
- reset-gpios
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "samsung,ams581vf01";
reg = <0>;
vdd3p3-supply = <&vreg_l7c_3p0>;
vddio-supply = <&vreg_l13a_1p8>;
vsn-supply = <&vreg_ibb>;
vsp-supply = <&vreg_lab>;
reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>;
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
...

80
Documentation/devicetree/bindings/display/panel/samsung,ams639rq08.yaml Normal file
View File

@ -0,0 +1,80 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/samsung,ams639rq08.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung AMS639RQ08 EA8076-based 6.39" 1080x2340 MIPI-DSI Panel
maintainers:
- Danila Tikhonov <danila@jiaxyga.com>
- Jens Reidel <adrian@travitia.xyz>
description:
The Samsung AMS639RQ08 is a 6.39 inch 1080x2340 MIPI-DSI CMD mode AMOLED panel.
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
const: samsung,ams639rq08
reg:
maxItems: 1
vdd3p3-supply:
description: 3.3V source voltage rail
vddio-supply:
description: I/O source voltage rail
vsn-supply:
description: Negative source voltage rail
vsp-supply:
description: Positive source voltage rail
reset-gpios: true
port: true
required:
- compatible
- reg
- vdd3p3-supply
- vddio-supply
- vsn-supply
- vsp-supply
- reset-gpios
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "samsung,ams639rq08";
reg = <0>;
vdd3p3-supply = <&vreg_l18a_2p8>;
vddio-supply = <&vreg_l13a_1p8>;
vsn-supply = <&vreg_ibb>;
vsp-supply = <&vreg_lab>;
reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>;
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
...

75
Documentation/devicetree/bindings/display/panel/samsung,s6e3ha8.yaml Normal file
View File

@ -0,0 +1,75 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/samsung,s6e3ha8.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung s6e3ha8 AMOLED DSI panel
description: The s6e3ha8 is a 1440x2960 DPI display panel from Samsung Mobile
Displays (SMD).
maintainers:
- Dzmitry Sankouski <dsankouski@gmail.com>
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
const: samsung,s6e3ha8
reg:
maxItems: 1
reset-gpios: true
port: true
vdd3-supply:
description: VDD regulator
vci-supply:
description: VCI regulator
vddr-supply:
description: VDDR regulator
required:
- compatible
- reset-gpios
- vdd3-supply
- vci-supply
- vddr-supply
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "samsung,s6e3ha8";
reg = <0>;
vci-supply = <&s2dos05_ldo4>;
vddr-supply = <&s2dos05_buck1>;
vdd3-supply = <&s2dos05_ldo1>;
te-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_active_sleep>;
pinctrl-names = "default", "sleep";
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
...

65
Documentation/devicetree/bindings/display/panel/samsung,s6e88a0-ams427ap24.yaml Normal file
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@ -0,0 +1,65 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/samsung,s6e88a0-ams427ap24.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung AMS427AP24 panel with S6E88A0 controller
maintainers:
- Jakob Hauser <jahau@rocketmail.com>
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
const: samsung,s6e88a0-ams427ap24
reg:
maxItems: 1
port: true
reset-gpios: true
flip-horizontal: true
vdd3-supply:
description: core voltage supply
vci-supply:
description: voltage supply for analog circuits
required:
- compatible
- reg
- port
- reset-gpios
- vdd3-supply
- vci-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "samsung,s6e88a0-ams427ap24";
reg = <0>;
vdd3-supply = <&pm8916_l17>;
vci-supply = <&pm8916_l6>;
reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
flip-horizontal;
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};

10
Documentation/devicetree/bindings/display/panel/samsung,s6e8aa0.yaml
View File

@ -21,6 +21,8 @@ properties:
reset-gpios: true
display-timings: true
flip-horizontal: true
flip-vertical: true
vdd3-supply:
description: core voltage supply
@ -46,14 +48,6 @@ properties:
panel-height-mm:
description: physical panel height [mm]
flip-horizontal:
description: boolean to flip image horizontally
type: boolean
flip-vertical:
description: boolean to flip image vertically
type: boolean
required:
- compatible
- reg

188
Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml Normal file
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@ -0,0 +1,188 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip DW HDMI QP TX Encoder
maintainers:
- Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
description: |
Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI QP TX controller
IP and a HDMI/eDP TX Combo PHY based on a Samsung IP block, providing the
following features, among others:
* Fixed Rate Link (FRL)
* Display Stream Compression (DSC)
* 4K@120Hz and 8K@60Hz video modes
* Variable Refresh Rate (VRR) including Quick Media Switching (QMS)
* Fast Vactive (FVA)
* SCDC I2C DDC access
* Multi-stream audio
* Enhanced Audio Return Channel (EARC)
allOf:
- $ref: /schemas/sound/dai-common.yaml#
properties:
compatible:
enum:
- rockchip,rk3588-dw-hdmi-qp
reg:
maxItems: 1
clocks:
items:
- description: Peripheral/APB bus clock
- description: EARC RX biphase clock
- description: Reference clock
- description: Audio interface clock
- description: TMDS/FRL link clock
- description: Video datapath clock
clock-names:
items:
- const: pclk
- const: earc
- const: ref
- const: aud
- const: hdp
- const: hclk_vo1
interrupts:
items:
- description: AVP Unit interrupt
- description: CEC interrupt
- description: eARC RX interrupt
- description: Main Unit interrupt
- description: HPD interrupt
interrupt-names:
items:
- const: avp
- const: cec
- const: earc
- const: main
- const: hpd
phys:
maxItems: 1
description: The HDMI/eDP PHY
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Video port for RGB/YUV input.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Video port for HDMI/eDP output.
required:
- port@0
- port@1
power-domains:
maxItems: 1
resets:
maxItems: 2
reset-names:
items:
- const: ref
- const: hdp
"#sound-dai-cells":
const: 0
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Some HDMI QP related data is accessed through SYS GRF regs.
rockchip,vo-grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Additional HDMI QP related data is accessed through VO GRF regs.
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- interrupt-names
- phys
- ports
- resets
- reset-names
- rockchip,grf
- rockchip,vo-grf
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/rk3588-power.h>
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
hdmi@fde80000 {
compatible = "rockchip,rk3588-dw-hdmi-qp";
reg = <0x0 0xfde80000 0x0 0x20000>;
clocks = <&cru PCLK_HDMITX0>,
<&cru CLK_HDMITX0_EARC>,
<&cru CLK_HDMITX0_REF>,
<&cru MCLK_I2S5_8CH_TX>,
<&cru CLK_HDMIHDP0>,
<&cru HCLK_VO1>;
clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "avp", "cec", "earc", "main", "hpd";
phys = <&hdptxphy_hdmi0>;
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
reset-names = "ref", "hdp";
rockchip,grf = <&sys_grf>;
rockchip,vo-grf = <&vo1_grf>;
#sound-dai-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi0_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi0>;
};
};
port@1 {
reg = <1>;
hdmi0_out_con0: endpoint {
remote-endpoint = <&hdmi_con0_in>;
};
};
};
};
};

4
Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml
View File

@ -19,7 +19,9 @@ description: |
properties:
compatible:
const: samsung,exynos7-decon
enum:
- samsung,exynos7-decon
- samsung,exynos7870-decon
clocks:
maxItems: 4

92
Documentation/devicetree/bindings/display/sharp,ls010b7dh04.yaml Normal file
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@ -0,0 +1,92 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/sharp,ls010b7dh04.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sharp Memory LCD panels
maintainers:
- Alex Lanzano <lanzano.alex@gmail.com>
description:
Sharp Memory LCDs are a series of monochrome displays that operate over
a SPI bus. The displays require a signal (VCOM) to be generated to prevent
DC bias build up resulting in pixels being unable to change. Three modes
can be used to provide the VCOM signal ("software", "external", "pwm").
properties:
compatible:
enum:
- sharp,ls010b7dh04
- sharp,ls011b7dh03
- sharp,ls012b7dd01
- sharp,ls013b7dh03
- sharp,ls013b7dh05
- sharp,ls018b7dh02
- sharp,ls027b7dh01
- sharp,ls027b7dh01a
- sharp,ls032b7dd02
- sharp,ls044q7dh01
reg:
maxItems: 1
spi-max-frequency:
maximum: 2000000
sharp,vcom-mode:
$ref: /schemas/types.yaml#/definitions/string
description: |
software - This mode relies on a software operation to send a
"maintain display" message to the display, toggling the vcom
bit on and off with each message
external - This mode relies on an external clock to generate
the signal on the EXTCOMM pin
pwm - This mode relies on a pwm device to generate the signal
on the EXTCOMM pin
enum: [software, external, pwm]
enable-gpios: true
pwms:
maxItems: 1
description: External VCOM signal
required:
- compatible
- reg
- sharp,vcom-mode
allOf:
- $ref: panel/panel-common.yaml#
- $ref: /schemas/spi/spi-peripheral-props.yaml#
- if:
properties:
sharp,vcom-mode:
const: pwm
then:
required:
- pwms
unevaluatedProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
display@0 {
compatible = "sharp,ls013b7dh03";
reg = <0>;
spi-cs-high;
spi-max-frequency = <1000000>;
sharp,vcom-mode = "software";
};
};
...

1
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
View File

@ -26,6 +26,7 @@ properties:
- renesas,r9a07g054-mali
- rockchip,px30-mali
- rockchip,rk3568-mali
- rockchip,rk3576-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
- items:
- enum:

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -756,6 +756,8 @@ patternProperties:
description: Japan Display Inc.
"^jedec,.*":
description: JEDEC Solid State Technology Association
"^jenson,.*":
description: Jenson Display Co. Ltd.
"^jesurun,.*":
description: Shenzhen Jesurun Electronics Business Dept.
"^jethome,.*":

731
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Display Core Debug tools
========================
In this section, you will find helpful information on debugging the amdgpu
driver from the display perspective. This page introduces debug mechanisms and
procedures to help you identify if some issues are related to display code.
Narrow down display issues
==========================
Since the display is the driver's visual component, it is common to see users
reporting issues as a display when another component causes the problem. This
section equips users to determine if a specific issue was caused by the display
component or another part of the driver.
DC dmesg important messages
---------------------------
The dmesg log is the first source of information to be checked, and amdgpu
takes advantage of this feature by logging some valuable information. When
looking for the issues associated with amdgpu, remember that each component of
the driver (e.g., smu, PSP, dm, etc.) is loaded one by one, and this
information can be found in the dmesg log. In this sense, look for the part of
the log that looks like the below log snippet::
[ 4.254295] [drm] initializing kernel modesetting (IP DISCOVERY 0x1002:0x744C 0x1002:0x0E3B 0xC8).
[ 4.254718] [drm] register mmio base: 0xFCB00000
[ 4.254918] [drm] register mmio size: 1048576
[ 4.260095] [drm] add ip block number 0 <soc21_common>
[ 4.260318] [drm] add ip block number 1 <gmc_v11_0>
[ 4.260510] [drm] add ip block number 2 <ih_v6_0>
[ 4.260696] [drm] add ip block number 3 <psp>
[ 4.260878] [drm] add ip block number 4 <smu>
[ 4.261057] [drm] add ip block number 5 <dm>
[ 4.261231] [drm] add ip block number 6 <gfx_v11_0>
[ 4.261402] [drm] add ip block number 7 <sdma_v6_0>
[ 4.261568] [drm] add ip block number 8 <vcn_v4_0>
[ 4.261729] [drm] add ip block number 9 <jpeg_v4_0>
[ 4.261887] [drm] add ip block number 10 <mes_v11_0>
From the above example, you can see the line that reports that `<dm>`,
(**Display Manager**), was loaded, which means that display can be part of the
issue. If you do not see that line, something else might have failed before
amdgpu loads the display component, indicating that we don't have a
display issue.
After you identified that the DM was loaded correctly, you can check for the
display version of the hardware in use, which can be retrieved from the dmesg
log with the command::
dmesg | grep -i 'display core'
This command shows a message that looks like this::
[ 4.655828] [drm] Display Core v3.2.285 initialized on DCN 3.2
This message has two key pieces of information:
* **The DC version (e.g., v3.2.285)**: Display developers release a new DC version
every week, and this information can be advantageous in a situation where a
user/developer must find a good point versus a bad point based on a tested
version of the display code. Remember from page :ref:`Display Core <amdgpu-display-core>`,
that every week the new patches for display are heavily tested with IGT and
manual tests.
* **The DCN version (e.g., DCN 3.2)**: The DCN block is associated with the
hardware generation, and the DCN version conveys the hardware generation that
the driver is currently running. This information helps to narrow down the
code debug area since each DCN version has its files in the DC folder per DCN
component (from the example, the developer might want to focus on
files/folders/functions/structs with the dcn32 label might be executed).
However, keep in mind that DC reuses code across different DCN versions; for
example, it is expected to have some callbacks set in one DCN that are the same
as those from another DCN. In summary, use the DCN version just as a guide.
From the dmesg file, it is also possible to get the ATOM bios code by using::
dmesg | grep -i 'ATOM BIOS'
Which generates an output that looks like this::
[ 4.274534] amdgpu: ATOM BIOS: 113-D7020100-102
This type of information is useful to be reported.
Avoid loading display core
--------------------------
Sometimes, it might be hard to figure out which part of the driver is causing
the issue; if you suspect that the display is not part of the problem and your
bug scenario is simple (e.g., some desktop configuration) you can try to remove
the display component from the equation. First, you need to identify `dm` ID
from the dmesg log; for example, search for the following log::
[ 4.254295] [drm] initializing kernel modesetting (IP DISCOVERY 0x1002:0x744C 0x1002:0x0E3B 0xC8).
[..]
[ 4.260095] [drm] add ip block number 0 <soc21_common>
[ 4.260318] [drm] add ip block number 1 <gmc_v11_0>
[..]
[ 4.261057] [drm] add ip block number 5 <dm>
Notice from the above example that the `dm` id is 5 for this specific hardware.
Next, you need to run the following binary operation to identify the IP block
mask::
0xffffffff & ~(1 << [DM ID])
From our example the IP mask is::
0xffffffff & ~(1 << 5) = 0xffffffdf
Finally, to disable DC, you just need to set the below parameter in your
bootloader::
amdgpu.ip_block_mask = 0xffffffdf
If you can boot your system with the DC disabled and still see the issue, it
means you can rule DC out of the equation. However, if the bug disappears, you
still need to consider the DC part of the problem and keep narrowing down the
issue. In some scenarios, disabling DC is impossible since it might be
necessary to use the display component to reproduce the issue (e.g., play a
game).
**Note: This will probably lead to the absence of a display output.**
Display flickering
------------------
Display flickering might have multiple causes; one is the lack of proper power
to the GPU or problems in the DPM switches. A good first generic verification
is to set the GPU to use high voltage::
bash -c "echo high > /sys/class/drm/card0/device/power_dpm_force_performance_level"
The above command sets the GPU/APU to use the maximum power allowed which
disables DPM switches. If forcing DPM levels high does not fix the issue, it
is less likely that the issue is related to power management. If the issue
disappears, there is a good chance that other components might be involved, and
the display should not be ignored since this could be a DPM issues. From the
display side, if the power increase fixes the issue, it is worth debugging the
clock configuration and the pipe split police used in the specific
configuration.
Display artifacts
-----------------
Users may see some screen artifacts that can be categorized into two different
types: localized artifacts and general artifacts. The localized artifacts
happen in some specific areas, such as around the UI window corners; if you see
this type of issue, there is a considerable chance that you have a userspace
problem, likely Mesa or similar. The general artifacts usually happen on the
entire screen. They might be caused by a misconfiguration at the driver level
of the display parameters, but the userspace might also cause this issue. One
way to identify the source of the problem is to take a screenshot or make a
desktop video capture when the problem happens; after checking the
screenshot/video recording, if you don't see any of the artifacts, it means
that the issue is likely on the the driver side. If you can still see the
problem in the data collected, it is an issue that probably happened during
rendering, and the display code just got the framebuffer already corrupted.
Disabling/Enabling specific features
====================================
DC has a struct named `dc_debug_options`, which is statically initialized by
all DCE/DCN components based on the specific hardware characteristic. This
structure usually facilitates the bring-up phase since developers can start
with many disabled features and enable them individually. This is also an
important debug feature since users can change it when debugging specific
issues.
For example, dGPU users sometimes see a problem where a horizontal fillet of
flickering happens in some specific part of the screen. This could be an
indication of Sub-Viewport issues; after the users identified the target DCN,
they can set the `force_disable_subvp` field to true in the statically
initialized version of `dc_debug_options` to see if the issue gets fixed. Along
the same lines, users/developers can also try to turn off `fams2_config` and
`enable_single_display_2to1_odm_policy`. In summary, the `dc_debug_options` is
an interesting form for identifying the problem.
DC Visual Confirmation
======================
@ -76,6 +251,18 @@ change in real-time by using something like::
When reporting a bug related to DC, consider attaching this log before and
after you reproduce the bug.
Collect Firmware information
============================
When reporting issues, it is important to have the firmware information since
it can be helpful for debugging purposes. To get all the firmware information,
use the command::
cat /sys/kernel/debug/dri/0/amdgpu_firmware_info
From the display perspective, pay attention to the firmware of the DMCU and
DMCUB.
DMUB Firmware Debug
===================

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@ -1,3 +1,5 @@
.. _dcn_blocks:
==========
DCN Blocks
==========

2
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@ -1,3 +1,5 @@
.. _dcn_overview:
=======================
Display Core Next (DCN)
=======================

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@ -90,6 +90,7 @@ table of content:
display-manager.rst
dcn-overview.rst
dcn-blocks.rst
programming-model-dcn.rst
mpo-overview.rst
dc-debug.rst
display-contributing.rst

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@ -0,0 +1,162 @@
====================
DC Programming Model
====================
In the :ref:`Display Core Next (DCN) <dcn_overview>` and :ref:`DCN Block
<dcn_blocks>` pages, you learned about the hardware components and how they
interact with each other. On this page, the focus is shifted to the display
code architecture. Hence, it is reasonable to remind the reader that the code
in DC is shared with other OSes; for this reason, DC provides a set of
abstractions and operations to connect different APIs with the hardware
configuration. See DC as a service available for a Display Manager (amdgpu_dm)
to access and configure DCN/DCE hardware (DCE is also part of DC, but for
simplicity's sake, this documentation only examines DCN).
.. note::
For this page, we will use the term GPU to refers to dGPU and APU.
Overview
========
From the display hardware perspective, it is plausible to expect that if a
problem is well-defined, it will probably be implemented at the hardware level.
On the other hand, when there are multiple ways of achieving something without
a very well-defined scope, the solution is usually implemented as a policy at
the DC level. In other words, some policies are defined in the DC core
(resource management, power optimization, image quality, etc.), and the others
implemented in hardware are enabled via DC configuration.
In terms of hardware management, DCN has multiple instances of the same block
(e.g., HUBP, DPP, MPC, etc), and during the driver execution, it might be
necessary to use some of these instances. The core has policies in place for
handling those instances. Regarding resource management, the DC objective is
quite simple: minimize the hardware shuffle when the driver performs some
actions. When the state changes from A to B, the transition is considered
easier to maneuver if the hardware resource is still used for the same set of
driver objects. Usually, adding and removing a resource to a `pipe_ctx` (more
details below) is not a problem; however, moving a resource from one `pipe_ctx`
to another should be avoided.
Another area of influence for DC is power optimization, which has a myriad of
arrangement possibilities. In some way, just displaying an image via DCN should
be relatively straightforward; however, showing it with the best power
footprint is more desirable, but it has many associated challenges.
Unfortunately, there is no straight-forward analytic way to determine if a
configuration is the best one for the context due to the enormous variety of
variables related to this problem (e.g., many different DCN/DCE hardware
versions, different displays configurations, etc.) for this reason DC
implements a dedicated library for trying some configuration and verify if it
is possible to support it or not. This type of policy is extremely complex to
create and maintain, and amdgpu driver relies on Display Mode Library (DML) to
generate the best decisions.
In summary, DC must deal with the complexity of handling multiple scenarios and
determine policies to manage them. All of the above information is conveyed to
give the reader some idea about the complexity of driving a display from the
driver's perspective. This page hopes to allow the reader to better navigate
over the amdgpu display code.
Display Driver Architecture Overview
====================================
The diagram below provides an overview of the display driver architecture;
notice it illustrates the software layers adopted by DC:
.. kernel-figure:: dc-components.svg
The first layer of the diagram is the high-level DC API represented by the
`dc.h` file; below it are two big blocks represented by Core and Link. Next is
the hardware configuration block; the main file describing it is
the`hw_sequencer.h`, where the implementation of the callbacks can be found in
the hardware sequencer folder. Almost at the end, you can see the block level
API (`dc/inc/hw`), which represents each DCN low-level block, such as HUBP,
DPP, MPC, OPTC, etc. Notice on the left side of the diagram that we have a
different set of layers representing the interaction with the DMUB
microcontroller.
Basic Objects
-------------
The below diagram outlines the basic display objects. In particular, pay
attention to the names in the boxes since they represent a data structure in
the driver:
.. kernel-figure:: dc-arch-overview.svg
Let's start with the central block in the image, `dc`. The `dc` struct is
initialized per GPU; for example, one GPU has one `dc` instance, two GPUs have
two `dc` instances, and so forth. In other words we have one 'dc' per 'amdgpu'
instance. In some ways, this object behaves like the `Singleton` pattern.
After the `dc` block in the diagram, you can see the `dc_link` component, which
is a low-level abstraction for the connector. One interesting aspect of the
image is that connectors are not part of the DCN block; they are defined by the
platform/board and not by the SoC. The `dc_link` struct is the high-level data
container with information such as connected sinks, connection status, signal
types, etc. After `dc_link`, there is the `dc_sink`, which is the object that
represents the connected display.
.. note::
For historical reasons, we used the name `dc_link`, which gives the
wrong impression that this abstraction only deals with physical connections
that the developer can easily manipulate. However, this also covers
conections like eDP or cases where the output is connected to other devices.
There are two structs that are not represented in the diagram since they were
elaborated in the DCN overview page (check the DCN block diagram :ref:`Display
Core Next (DCN) <dcn_overview>`); still, it is worth bringing back for this
overview which is `dc_stream` and `dc_state`. The `dc_stream` stores many
properties associated with the data transmission, but most importantly, it
represents the data flow from the connector to the display. Next we have
`dc_state`, which represents the logic state within the hardware at the moment;
`dc_state` is composed of `dc_stream` and `dc_plane`. The `dc_stream` is the DC
version of `drm_crtc` and represents the post-blending pipeline.
Speaking of the `dc_plane` data structure (first part of the diagram), you can
think about it as an abstraction similar to `drm_plane` that represents the
pre-blending portion of the pipeline. This image was probably processed by GFX
and is ready to be composited under a `dc_stream`. Normally, the driver may
have one or more `dc_plane` connected to the same `dc_stream`, which defines a
composition at the DC level.
Basic Operations
----------------
Now that we have covered the basic objects, it is time to examine some of the
basic hardware/software operations. Let's start with the `dc_create()`
function, which directly works with the `dc` data struct; this function behaves
like a constructor responsible for the basic software initialization and
preparing for enabling other parts of the API. It is important to highlight
that this operation does not touch any hardware configuration; it is only a
software initialization.
Next, we have the `dc_hardware_init()`, which also relies on the `dc` data
struct. Its main function is to put the hardware in a valid state. It is worth
highlighting that the hardware might initialize in an unknown state, and it is
a requirement to put it in a valid state; this function has multiple callbacks
for the hardware-specific initialization, whereas `dc_hardware_init` does the
hardware initialization and is the first point where we touch hardware.
The `dc_get_link_at_index` is an operation that depends on the `dc_link` data
structure. This function retrieves and enumerates all the `dc_links` available
on the device; this is required since this information is not part of the SoC
definition but depends on the board configuration. As soon as the `dc_link` is
initialized, it is useful to figure out if any of them are already connected to
the display by using the `dc_link_detect()` function. After the driver figures
out if any display is connected to the device, the challenging phase starts:
configuring the monitor to show something. Nonetheless, dealing with the ideal
configuration is not a DC task since this is the Display Manager (`amdgpu_dm`)
responsibility which in turn is responsible for dealing with the atomic
commits. The only interface DC provides to the configuration phase is the
function `dc_validate_with_context` that receives the configuration information
and, based on that, validates whether the hardware can support it or not. It is
important to add that even if the display supports some specific configuration,
it does not mean the DCN hardware can support it.
After the DM and DC agree upon the configuration, the stream configuration
phase starts. This task activates one or more `dc_stream` at this phase, and in
the best-case scenario, you might be able to turn the display on with a black
screen (it does not show anything yet since it does not have any plane
associated with it). The final step would be to call the
`dc_update_planes_and_stream,` which will add or remove planes.

1
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@ -16,4 +16,5 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures.
thermal
driver-misc
debugging
process-isolation
amdgpu-glossary

59
Documentation/gpu/amdgpu/process-isolation.rst Normal file
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@ -0,0 +1,59 @@
.. SPDX-License-Identifier: GPL-2.0
=========================
AMDGPU Process Isolation
=========================
The AMDGPU driver includes a feature that enables automatic process isolation on the graphics engine. This feature serializes access to the graphics engine and adds a cleaner shader which clears the Local Data Store (LDS) and General Purpose Registers (GPRs) between jobs. All processes using the GPU, including both graphics and compute workloads, are serialized when this feature is enabled. On GPUs that support partitionable graphics engines, this feature can be enabled on a per-partition basis.
In addition, there is an interface to manually run the cleaner shader when the use of the GPU is complete. This may be preferable in some use cases, such as a single-user system where the login manager triggers the cleaner shader when the user logs out.
Process Isolation
=================
The `run_cleaner_shader` and `enforce_isolation` sysfs interfaces allow users to manually execute the cleaner shader and control the process isolation feature, respectively.
Partition Handling
------------------
The `enforce_isolation` file in sysfs can be used to enable process isolation and automatic shader cleanup between processes. On GPUs that support graphics engine partitioning, this can be enabled per partition. The partition and its current setting (0 disabled, 1 enabled) can be read from sysfs. On GPUs that do not support graphics engine partitioning, only a single partition will be present. Writing 1 to the partition position enables enforce isolation, writing 0 disables it.
Example of enabling enforce isolation on a GPU with multiple partitions:
.. code-block:: console
$ echo 1 0 1 0 > /sys/class/drm/card0/device/enforce_isolation
$ cat /sys/class/drm/card0/device/enforce_isolation
1 0 1 0
The output indicates that enforce isolation is enabled on zeroth and second parition and disabled on first and fourth parition.
For devices with a single partition or those that do not support partitions, there will be only one element:
.. code-block:: console
$ echo 1 > /sys/class/drm/card0/device/enforce_isolation
$ cat /sys/class/drm/card0/device/enforce_isolation
1
Cleaner Shader Execution
========================
The driver can trigger a cleaner shader to clean up the LDS and GPR state on the graphics engine. When process isolation is enabled, this happens automatically between processes. In addition, there is a sysfs file to manually trigger cleaner shader execution.
To manually trigger the execution of the cleaner shader, write `0` to the `run_cleaner_shader` sysfs file:
.. code-block:: console
$ echo 0 > /sys/class/drm/card0/device/run_cleaner_shader
For multi-partition devices, you can specify the partition index when triggering the cleaner shader:
.. code-block:: console
$ echo 0 > /sys/class/drm/card0/device/run_cleaner_shader # For partition 0
$ echo 1 > /sys/class/drm/card0/device/run_cleaner_shader # For partition 1
$ echo 2 > /sys/class/drm/card0/device/run_cleaner_shader # For partition 2
# ... and so on for each partition
This command initiates the cleaner shader, which will run and complete before any new tasks are scheduled on the GPU.

12
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@ -100,6 +100,18 @@ fan_minimum_pwm
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
:doc: fan_minimum_pwm
fan_zero_rpm_enable
----------------------
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
:doc: fan_zero_rpm_enable
fan_zero_rpm_stop_temperature
-----------------------------
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
:doc: fan_zero_rpm_stop_temperature
GFXOFF
======

14
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@ -68,19 +68,25 @@ known to behave unreliably. These tests won't cause a job to fail regardless of
the result. They will still be run.
Each new flake entry must be associated with a link to the email reporting the
bug to the author of the affected driver, the board name or Device Tree name of
the board, the first kernel version affected, the IGT version used for tests,
and an approximation of the failure rate.
bug to the author of the affected driver or the relevant GitLab issue. The entry
must also include the board name or Device Tree name, the first kernel version
affected, the IGT version used for tests, and an approximation of the failure rate.
They should be provided under the following format::
# Bug Report: $LORE_OR_PATCHWORK_URL
# Bug Report: $LORE_URL_OR_GITLAB_ISSUE
# Board Name: broken-board.dtb
# Linux Version: 6.6-rc1
# IGT Version: 1.28-gd2af13d9f
# Failure Rate: 100
flaky-test
Use the appropriate link below to create a GitLab issue:
amdgpu driver: https://gitlab.freedesktop.org/drm/amd/-/issues
i915 driver: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues
msm driver: https://gitlab.freedesktop.org/drm/msm/-/issues
xe driver: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues
drivers/gpu/drm/ci/${DRIVER_NAME}-${HW_REVISION}-skips.txt
-----------------------------------------------------------

2
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@ -22,6 +22,8 @@ GPU Driver Documentation
afbc
komeda-kms
panfrost
panthor
zynqmp
.. only:: subproject and html

3
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View File

@ -13,3 +13,6 @@ Kernel clients
.. kernel-doc:: drivers/gpu/drm/drm_client_modeset.c
:export:
.. kernel-doc:: drivers/gpu/drm/drm_client_event.c
:export:

12
Documentation/gpu/drm-internals.rst
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@ -75,18 +75,6 @@ Module Initialization
.. kernel-doc:: include/drm/drm_module.h
:doc: overview
Managing Ownership of the Framebuffer Aperture
----------------------------------------------
.. kernel-doc:: drivers/gpu/drm/drm_aperture.c
:doc: overview
.. kernel-doc:: include/drm/drm_aperture.h
:internal:
.. kernel-doc:: drivers/gpu/drm/drm_aperture.c
:export:
Device Instance and Driver Handling
-----------------------------------

9
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@ -110,15 +110,6 @@ fbdev Helper Functions Reference
.. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c
:doc: fbdev helpers
.. kernel-doc:: drivers/gpu/drm/drm_fbdev_dma.c
:export:
.. kernel-doc:: drivers/gpu/drm/drm_fbdev_shmem.c
:export:
.. kernel-doc:: drivers/gpu/drm/drm_fbdev_ttm.c
:export:
.. kernel-doc:: include/drm/drm_fb_helper.h
:internal:

27
Documentation/gpu/drm-uapi.rst
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@ -305,13 +305,26 @@ Kernel Mode Driver
------------------
The KMD is responsible for checking if the device needs a reset, and to perform
it as needed. Usually a hang is detected when a job gets stuck executing. KMD
should keep track of resets, because userspace can query any time about the
reset status for a specific context. This is needed to propagate to the rest of
the stack that a reset has happened. Currently, this is implemented by each
driver separately, with no common DRM interface. Ideally this should be properly
integrated at DRM scheduler to provide a common ground for all drivers. After a
reset, KMD should reject new command submissions for affected contexts.
it as needed. Usually a hang is detected when a job gets stuck executing.
Propagation of errors to userspace has proven to be tricky since it goes in
the opposite direction of the usual flow of commands. Because of this vendor
independent error handling was added to the &dma_fence object, this way drivers
can add an error code to their fences before signaling them. See function
dma_fence_set_error() on how to do this and for examples of error codes to use.
The DRM scheduler also allows setting error codes on all pending fences when
hardware submissions are restarted after an reset. Error codes are also
forwarded from the hardware fence to the scheduler fence to bubble up errors
to the higher levels of the stack and eventually userspace.
Fence errors can be queried by userspace through the generic SYNC_IOC_FILE_INFO
IOCTL as well as through driver specific interfaces.
Additional to setting fence errors drivers should also keep track of resets per
context, the DRM scheduler provides the drm_sched_entity_error() function as
helper for this use case. After a reset, KMD should reject new command
submissions for affected contexts.
User Mode Driver
----------------

31
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@ -73,6 +73,11 @@ scope of each device, in which case `drm-pdev` shall be present as well.
Userspace should make sure to not double account any usage statistics by using
the above described criteria in order to associate data to individual clients.
- drm-client-name: <valstr>
String optionally set by userspace using DRM_IOCTL_SET_CLIENT_NAME.
Utilization
^^^^^^^^^^^
@ -144,7 +149,9 @@ Memory
Each possible memory type which can be used to store buffer objects by the
GPU in question shall be given a stable and unique name to be returned as the
string here. The name "memory" is reserved to refer to normal system memory.
string here.
The region name "memory" is reserved to refer to normal system memory.
Value shall reflect the amount of storage currently consumed by the buffer
objects belong to this client, in the respective memory region.
@ -152,6 +159,9 @@ objects belong to this client, in the respective memory region.
Default unit shall be bytes with optional unit specifiers of 'KiB' or 'MiB'
indicating kibi- or mebi-bytes.
This key is deprecated and is an alias for drm-resident-<region>. Only one of
the two should be present in the output.
- drm-shared-<region>: <uint> [KiB|MiB]
The total size of buffers that are shared with another file (e.g., have more
@ -159,20 +169,34 @@ than a single handle).
- drm-total-<region>: <uint> [KiB|MiB]
The total size of buffers that including shared and private memory.
The total size of all created buffers including shared and private memory. The
backing store for the buffers does not have to be currently instantiated to be
counted under this category.
- drm-resident-<region>: <uint> [KiB|MiB]
The total size of buffers that are resident in the specified region.
The total size of buffers that are resident (have their backing store present or
instantiated) in the specified region.
This is an alias for drm-memory-<region> and only one of the two should be
present in the output.
- drm-purgeable-<region>: <uint> [KiB|MiB]
The total size of buffers that are purgeable.
For example drivers which implement a form of 'madvise' like functionality can
here count buffers which have instantiated backing store, but have been marked
with an equivalent of MADV_DONTNEED.
- drm-active-<region>: <uint> [KiB|MiB]
The total size of buffers that are active on one or more engines.
One practical example of this can be presence of unsignaled fences in an GEM
buffer reservation object. Therefore the active category is a subset of
resident.
Implementation Details
======================
@ -186,4 +210,5 @@ Driver specific implementations
* :ref:`i915-usage-stats`
* :ref:`panfrost-usage-stats`
* :ref:`panthor-usage-stats`
* :ref:`xe-usage-stats`

4
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@ -35,10 +35,10 @@ Interrupt Handling
:functions: intel_irq_init intel_irq_init_hw intel_hpd_init
.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
:functions: intel_runtime_pm_disable_interrupts
:functions: intel_irq_suspend
.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
:functions: intel_runtime_pm_enable_interrupts
:functions: intel_irq_resume
Intel GVT-g Guest Support(vGPU)
-------------------------------

99
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@ -0,0 +1,99 @@
.. SPDX-License-Identifier: GPL-2.0
:orphan:
==============
MSM Preemption
==============
Preemption allows Adreno GPUs to switch to a higher priority ring when work is
pushed to it, reducing latency for high priority submissions.
When preemption is enabled 4 rings are initialized, corresponding to different
priority levels. Having multiple rings is purely a software concept as the GPU
only has registers to keep track of one graphics ring.
The kernel is able to switch which ring is currently being processed by
requesting preemption. When certain conditions are met, depending on the
priority level, the GPU will save its current state in a series of buffers,
then restores state from a similar set of buffers specified by the kernel. It
then resumes execution and fires an IRQ to let the kernel know the context
switch has completed.
This mechanism can be used by the kernel to switch between rings. Whenever a
submission occurs the kernel finds the highest priority ring which isn't empty
and preempts to it if said ring is not the one being currently executed. This is
also done whenever a submission completes to make sure execution resumes on a
lower priority ring when a higher priority ring is done.
Preemption levels
-----------------
Preemption can only occur at certain boundaries. The exact conditions can be
configured by changing the preemption level, this allows to compromise between
latency (ie. the time that passes between when the kernel requests preemption
and when the SQE begins saving state) and overhead (the amount of state that
needs to be saved).
The GPU offers 3 levels:
Level 0
Preemption only occurs at the submission level. This requires the least amount
of state to be saved as the execution of userspace submitted IBs is never
interrupted, however it offers very little benefit compared to not enabling
preemption of any kind.
Level 1
Preemption occurs at either bin level, if using GMEM rendering, or draw level
in the sysmem rendering case.
Level 2
Preemption occurs at draw level.
Level 1 is the mode that is used by the msm driver.
Additionally the GPU allows to specify a `skip_save_restore` option. This
disables the saving and restoring of all registers except those relating to the
operation of the SQE itself, reducing overhead. Saving and restoring is only
skipped when using GMEM with Level 1 preemption. When enabling this userspace is
expected to set the state that isn't preserved whenever preemption occurs which
is done by specifying preamble and postambles. Those are IBs that are executed
before and after preemption.
Preemption buffers
------------------
A series of buffers are necessary to store the state of rings while they are not
being executed. There are different kinds of preemption records and most of
those require one buffer per ring. This is because preemption never occurs
between submissions on the same ring, which always run in sequence when the ring
is active. This means that only one context per ring is effectively active.
SMMU_INFO
This buffer contains info about the current SMMU configuration such as the
ttbr0 register. The SQE firmware isn't actually able to save this record.
As a result SMMU info must be saved manually from the CP to a buffer and the
SMMU record updated with info from said buffer before triggering
preemption.
NON_SECURE
This is the main preemption record where most state is saved. It is mostly
opaque to the kernel except for the first few words that must be initialized
by the kernel.
SECURE
This saves state related to the GPU's secure mode.
NON_PRIV
The intended purpose of this record is unknown. The SQE firmware actually
ignores it and therefore msm doesn't handle it.
COUNTER
This record is used to save and restore performance counters.
Handling the permissions of those buffers is critical for security. All but the
NON_PRIV records need to be inaccessible from userspace, so they must be mapped
in the kernel address space with the MSM_BO_MAP_PRIV flag.
For example, making the NON_SECURE record accessible from userspace would allow
any process to manipulate a saved ring's RPTR which can be used to skip the
execution of some packets in a ring and execute user commands with higher
privileges.

46
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@ -0,0 +1,46 @@
.. SPDX-License-Identifier: GPL-2.0+
=========================
drm/Panthor CSF driver
=========================
.. _panthor-usage-stats:
Panthor DRM client usage stats implementation
==============================================
The drm/Panthor driver implements the DRM client usage stats specification as
documented in :ref:`drm-client-usage-stats`.
Example of the output showing the implemented key value pairs and entirety of
the currently possible format options:
::
pos: 0
flags: 02400002
mnt_id: 29
ino: 491
drm-driver: panthor
drm-client-id: 10
drm-engine-panthor: 111110952750 ns
drm-cycles-panthor: 94439687187
drm-maxfreq-panthor: 1000000000 Hz
drm-curfreq-panthor: 1000000000 Hz
drm-total-memory: 16480 KiB
drm-shared-memory: 0
drm-active-memory: 16200 KiB
drm-resident-memory: 16480 KiB
drm-purgeable-memory: 0
Possible `drm-engine-` key names are: `panthor`.
`drm-curfreq-` values convey the current operating frequency for that engine.
Users must bear in mind that engine and cycle sampling are disabled by default,
because of power saving concerns. `fdinfo` users and benchmark applications which
query the fdinfo file must make sure to toggle the job profiling status of the
driver by writing into the appropriate sysfs node::
echo <N> > /sys/bus/platform/drivers/panthor/[a-f0-9]*.gpu/profiling
Where `N` is a bit mask where cycle and timestamp sampling are respectively
enabled by the first and second bits.

16
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@ -834,6 +834,22 @@ Contact: Javier Martinez Canillas <javierm@redhat.com>
Level: Advanced
Querying errors from drm_syncobj
================================
The drm_syncobj container can be used by driver independent code to signal
complection of submission.
One minor feature still missing is a generic DRM IOCTL to query the error
status of binary and timeline drm_syncobj.
This should probably be improved by implementing the necessary kernel interface
and adding support for that in the userspace stack.
Contact: Christian König
Level: Starter
Outside DRM
===========

149
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@ -0,0 +1,149 @@
.. SPDX-License-Identifier: GPL-2.0+
===============================================
Xilinx ZynqMP Ultrascale+ DisplayPort Subsystem
===============================================
This subsystem handles DisplayPort video and audio output on the ZynqMP. It
supports in-memory framebuffers with the DisplayPort DMA controller
(xilinx-dpdma), as well as "live" video and audio from the programmable logic
(PL). This subsystem can perform several transformations, including color space
conversion, alpha blending, and audio mixing, although not all features are
currently supported.
debugfs
-------
To support debugging and compliance testing, several test modes can be enabled
though debugfs. The following files in /sys/kernel/debug/dri/X/DP-1/test/
control the DisplayPort test modes:
active:
Writing a 1 to this file will activate test mode, and writing a 0 will
deactivate test mode. Writing a 1 or 0 when the test mode is already
active/inactive will re-activate/re-deactivate test mode. When test
mode is inactive, changes made to other files will have no (immediate)
effect, although the settings will be saved for when test mode is
activated. When test mode is active, changes made to other files will
apply immediately.
custom:
Custom test pattern value
downspread:
Enable/disable clock downspreading (spread-spectrum clocking) by
writing 1/0
enhanced:
Enable/disable enhanced framing
ignore_aux_errors:
Ignore AUX errors when set to 1. Writes to this file take effect
immediately (regardless of whether test mode is active) and affect all
AUX transfers.
ignore_hpd:
Ignore hotplug events (such as cable removals or monitor link
retraining requests) when set to 1. Writes to this file take effect
immediately (regardless of whether test mode is active).
laneX_preemphasis:
Preemphasis from 0 (lowest) to 2 (highest) for lane X
laneX_swing:
Voltage swing from 0 (lowest) to 3 (highest) for lane X
lanes:
Number of lanes to use (1, 2, or 4)
pattern:
Test pattern. May be one of:
video
Use regular video input
symbol-error
Symbol error measurement pattern
prbs7
Output of the PRBS7 (x^7 + x^6 + 1) polynomial
80bit-custom
A custom 80-bit pattern
cp2520
HBR2 compliance eye pattern
tps1
Link training symbol pattern TPS1 (/D10.2/)
tps2
Link training symbol pattern TPS2
tps3
Link training symbol pattern TPS3 (for HBR2)
rate:
Rate in hertz. One of
* 5400000000 (HBR2)
* 2700000000 (HBR)
* 1620000000 (RBR)
You can dump the displayport test settings with the following command::
for prop in /sys/kernel/debug/dri/1/DP-1/test/*; do
printf '%-17s ' ${prop##*/}
if [ ${prop##*/} = custom ]; then
hexdump -C $prop | head -1
else
cat $prop
fi
done
The output could look something like::
active 1
custom 00000000 00 00 00 00 00 00 00 00 00 00 |..........|
downspread 0
enhanced 1
ignore_aux_errors 1
ignore_hpd 1
lane0_preemphasis 0
lane0_swing 3
lane1_preemphasis 0
lane1_swing 3
lanes 2
pattern prbs7
rate 1620000000
The recommended test procedure is to connect the board to a monitor,
configure test mode, activate test mode, and then disconnect the cable
and connect it to your test equipment of choice. For example, one
sequence of commands could be::
echo 1 > /sys/kernel/debug/dri/1/DP-1/test/enhanced
echo tps1 > /sys/kernel/debug/dri/1/DP-1/test/pattern
echo 1620000000 > /sys/kernel/debug/dri/1/DP-1/test/rate
echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_aux_errors
echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_hpd
echo 1 > /sys/kernel/debug/dri/1/DP-1/test/active
at which point the cable could be disconnected from the monitor.
Internals
---------
.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_disp.h
.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_dpsub.h
.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_kms.h
.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_disp.c
.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_dp.c
.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_dpsub.c
.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_kms.c

156
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@ -2225,7 +2225,7 @@ The following table list existing packed 48bit wide RGB formats.
\endgroup
On LVDS buses, usually each sample is transferred serialized in seven
time slots per pixel clock, on three (18-bit) or four (24-bit)
time slots per pixel clock, on three (18-bit) or four (24-bit) or five (30-bit)
differential data pairs at the same time. The remaining bits are used
for control signals as defined by SPWG/PSWG/VESA or JEIDA standards. The
24-bit RGB format serialized in seven time slots on four lanes using
@ -2246,11 +2246,12 @@ JEIDA defined bit mapping will be named
- Code
-
-
- :cspan:`3` Data organization
- :cspan:`4` Data organization
* -
-
- Timeslot
- Lane
- 4
- 3
- 2
- 1
@ -2262,6 +2263,7 @@ JEIDA defined bit mapping will be named
- 0
-
-
-
- d
- b\ :sub:`1`
- g\ :sub:`0`
@ -2270,6 +2272,7 @@ JEIDA defined bit mapping will be named
- 1
-
-
-
- d
- b\ :sub:`0`
- r\ :sub:`5`
@ -2278,6 +2281,7 @@ JEIDA defined bit mapping will be named
- 2
-
-
-
- d
- g\ :sub:`5`
- r\ :sub:`4`
@ -2286,6 +2290,7 @@ JEIDA defined bit mapping will be named
- 3
-
-
-
- b\ :sub:`5`
- g\ :sub:`4`
- r\ :sub:`3`
@ -2294,6 +2299,7 @@ JEIDA defined bit mapping will be named
- 4
-
-
-
- b\ :sub:`4`
- g\ :sub:`3`
- r\ :sub:`2`
@ -2302,6 +2308,7 @@ JEIDA defined bit mapping will be named
- 5
-
-
-
- b\ :sub:`3`
- g\ :sub:`2`
- r\ :sub:`1`
@ -2310,6 +2317,7 @@ JEIDA defined bit mapping will be named
- 6
-
-
-
- b\ :sub:`2`
- g\ :sub:`1`
- r\ :sub:`0`
@ -2319,6 +2327,7 @@ JEIDA defined bit mapping will be named
- 0x1011
- 0
-
-
- d
- d
- b\ :sub:`1`
@ -2327,6 +2336,7 @@ JEIDA defined bit mapping will be named
-
- 1
-
-
- b\ :sub:`7`
- d
- b\ :sub:`0`
@ -2335,6 +2345,7 @@ JEIDA defined bit mapping will be named
-
- 2
-
-
- b\ :sub:`6`
- d
- g\ :sub:`5`
@ -2343,6 +2354,7 @@ JEIDA defined bit mapping will be named
-
- 3
-
-
- g\ :sub:`7`
- b\ :sub:`5`
- g\ :sub:`4`
@ -2351,6 +2363,7 @@ JEIDA defined bit mapping will be named
-
- 4
-
-
- g\ :sub:`6`
- b\ :sub:`4`
- g\ :sub:`3`
@ -2359,6 +2372,7 @@ JEIDA defined bit mapping will be named
-
- 5
-
-
- r\ :sub:`7`
- b\ :sub:`3`
- g\ :sub:`2`
@ -2367,6 +2381,7 @@ JEIDA defined bit mapping will be named
-
- 6
-
-
- r\ :sub:`6`
- b\ :sub:`2`
- g\ :sub:`1`
@ -2377,6 +2392,7 @@ JEIDA defined bit mapping will be named
- 0x1012
- 0
-
-
- d
- d
- b\ :sub:`3`
@ -2385,6 +2401,7 @@ JEIDA defined bit mapping will be named
-
- 1
-
-
- b\ :sub:`1`
- d
- b\ :sub:`2`
@ -2393,6 +2410,7 @@ JEIDA defined bit mapping will be named
-
- 2
-
-
- b\ :sub:`0`
- d
- g\ :sub:`7`
@ -2401,6 +2419,7 @@ JEIDA defined bit mapping will be named
-
- 3
-
-
- g\ :sub:`1`
- b\ :sub:`7`
- g\ :sub:`6`
@ -2409,6 +2428,7 @@ JEIDA defined bit mapping will be named
-
- 4
-
-
- g\ :sub:`0`
- b\ :sub:`6`
- g\ :sub:`5`
@ -2417,6 +2437,7 @@ JEIDA defined bit mapping will be named
-
- 5
-
-
- r\ :sub:`1`
- b\ :sub:`5`
- g\ :sub:`4`
@ -2425,10 +2446,141 @@ JEIDA defined bit mapping will be named
-
- 6
-
-
- r\ :sub:`0`
- b\ :sub:`4`
- g\ :sub:`3`
- r\ :sub:`2`
* .. _MEDIA-BUS-FMT-RGB101010-1X7X5-SPWG:
- MEDIA_BUS_FMT_RGB101010_1X7X5_SPWG
- 0x1026
- 0
-
- d
- d
- d
- b\ :sub:`1`
- g\ :sub:`0`
* -
-
- 1
-
- b\ :sub:`9`
- b\ :sub:`7`
- d
- b\ :sub:`0`
- r\ :sub:`5`
* -
-
- 2
-
- b\ :sub:`8`
- b\ :sub:`6`
- d
- g\ :sub:`5`
- r\ :sub:`4`
* -
-
- 3
-
- g\ :sub:`9`
- g\ :sub:`7`
- b\ :sub:`5`
- g\ :sub:`4`
- r\ :sub:`3`
* -
-
- 4
-
- g\ :sub:`8`
- g\ :sub:`6`
- b\ :sub:`4`
- g\ :sub:`3`
- r\ :sub:`2`
* -
-
- 5
-
- r\ :sub:`9`
- r\ :sub:`7`
- b\ :sub:`3`
- g\ :sub:`2`
- r\ :sub:`1`
* -
-
- 6
-
- r\ :sub:`8`
- r\ :sub:`6`
- b\ :sub:`2`
- g\ :sub:`1`
- r\ :sub:`0`
* .. _MEDIA-BUS-FMT-RGB101010-1X7X5-JEIDA:
- MEDIA_BUS_FMT_RGB101010_1X7X5_JEIDA
- 0x1027
- 0
-
- d
- d
- d
- b\ :sub:`5`
- g\ :sub:`4`
* -
-
- 1
-
- b\ :sub:`1`
- b\ :sub:`3`
- d
- b\ :sub:`4`
- r\ :sub:`9`
* -
-
- 2
-
- b\ :sub:`0`
- b\ :sub:`2`
- d
- g\ :sub:`9`
- r\ :sub:`8`
* -
-
- 3
-
- g\ :sub:`1`
- g\ :sub:`3`
- b\ :sub:`9`
- g\ :sub:`8`
- r\ :sub:`7`
* -
-
- 4
-
- g\ :sub:`0`
- g\ :sub:`2`
- b\ :sub:`8`
- g\ :sub:`7`
- r\ :sub:`6`
* -
-
- 5
-
- r\ :sub:`1`
- r\ :sub:`3`
- b\ :sub:`7`
- g\ :sub:`6`
- r\ :sub:`5`
* -
-
- 6
-
- r\ :sub:`0`
- r\ :sub:`2`
- b\ :sub:`6`
- g\ :sub:`5`
- r\ :sub:`4`
.. raw:: latex

28
MAINTAINERS
View File

@ -7103,12 +7103,10 @@ M: Javier Martinez Canillas <javierm@redhat.com>
L: dri-devel@lists.freedesktop.org
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: drivers/gpu/drm/drm_aperture.c
F: drivers/gpu/drm/tiny/ofdrm.c
F: drivers/gpu/drm/tiny/simpledrm.c
F: drivers/video/aperture.c
F: drivers/video/nomodeset.c
F: include/drm/drm_aperture.h
F: include/linux/aperture.h
F: include/video/nomodeset.h
@ -7389,6 +7387,18 @@ S: Maintained
F: Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml
F: drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c
DRM DRIVER FOR SAMSUNG S6E3HA8 PANELS
M: Dzmitry Sankouski <dsankouski@gmail.com>
S: Maintained
F: Documentation/devicetree/bindings/display/panel/samsung,s6e3ha8.yaml
F: drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c
DRM DRIVER FOR SHARP MEMORY LCD
M: Alex Lanzano <lanzano.alex@gmail.com>
S: Maintained
F: Documentation/devicetree/bindings/display/sharp,ls010b7dh04.yaml
F: drivers/gpu/drm/tiny/sharp-memory.c
DRM DRIVER FOR SITRONIX ST7586 PANELS
M: David Lechner <david@lechnology.com>
S: Maintained
@ -7466,8 +7476,7 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: drivers/gpu/drm/udl/
DRM DRIVER FOR VIRTUAL KERNEL MODESETTING (VKMS)
M: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
M: Maíra Canal <mairacanal@riseup.net>
M: Louis Chauvet <louis.chauvet@bootlin.com>
R: Haneen Mohammed <hamohammed.sa@gmail.com>
R: Simona Vetter <simona@ffwll.ch>
R: Melissa Wen <melissa.srw@gmail.com>
@ -7799,6 +7808,7 @@ F: include/uapi/drm/v3d_drm.h
DRM DRIVERS FOR VC4
M: Maxime Ripard <mripard@kernel.org>
M: Dave Stevenson <dave.stevenson@raspberrypi.com>
R: Maíra Canal <mcanal@igalia.com>
R: Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
S: Supported
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
@ -7833,6 +7843,7 @@ L: dri-devel@lists.freedesktop.org
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/xlnx/
F: Documentation/gpu/zynqmp.rst
F: drivers/gpu/drm/xlnx/
DRM GPU SCHEDULER
@ -12174,6 +12185,14 @@ W: https://linuxtv.org
Q: http://patchwork.linuxtv.org/project/linux-media/list/
F: drivers/media/tuners/it913x*
ITE IT6263 LVDS TO HDMI BRIDGE DRIVER
M: Liu Ying <victor.liu@nxp.com>
L: dri-devel@lists.freedesktop.org
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
F: drivers/gpu/drm/bridge/ite-it6263.c
ITE IT66121 HDMI BRIDGE DRIVER
M: Phong LE <ple@baylibre.com>
M: Neil Armstrong <neil.armstrong@linaro.org>
@ -24301,6 +24320,7 @@ F: lib/iov_iter.c
USERSPACE DMA BUFFER DRIVER
M: Gerd Hoffmann <kraxel@redhat.com>
M: Vivek Kasireddy <vivek.kasireddy@intel.com>
L: dri-devel@lists.freedesktop.org
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git

2
arch/x86/kernel/early-quirks.c
View File

@ -18,7 +18,7 @@
#include <linux/bcma/bcma_regs.h>
#include <linux/platform_data/x86/apple.h>
#include <drm/intel/i915_drm.h>
#include <drm/intel/i915_pciids.h>
#include <drm/intel/pciids.h>
#include <asm/pci-direct.h>
#include <asm/dma.h>
#include <asm/io_apic.h>

10
drivers/accel/ivpu/Kconfig
View File

@ -8,6 +8,7 @@ config DRM_ACCEL_IVPU
select FW_LOADER
select DRM_GEM_SHMEM_HELPER
select GENERIC_ALLOCATOR
select WANT_DEV_COREDUMP
help
Choose this option if you have a system with an 14th generation
Intel CPU (Meteor Lake) or newer. Intel NPU (formerly called Intel VPU)
@ -15,3 +16,12 @@ config DRM_ACCEL_IVPU
and Deep Learning applications.
If "M" is selected, the module will be called intel_vpu.
config DRM_ACCEL_IVPU_DEBUG
bool "Intel NPU debug mode"
depends on DRM_ACCEL_IVPU
help
Choose this option to enable additional
debug features for the Intel NPU driver:
- Always print debug messages regardless of dyndbg config,
- Enable unsafe module params.

8
drivers/accel/ivpu/Makefile
View File

@ -16,8 +16,14 @@ intel_vpu-y := \
ivpu_mmu_context.o \
ivpu_ms.o \
ivpu_pm.o \
ivpu_sysfs.o
ivpu_sysfs.o \
ivpu_trace_points.o
intel_vpu-$(CONFIG_DEBUG_FS) += ivpu_debugfs.o
intel_vpu-$(CONFIG_DEV_COREDUMP) += ivpu_coredump.o
obj-$(CONFIG_DRM_ACCEL_IVPU) += intel_vpu.o
subdir-ccflags-$(CONFIG_DRM_ACCEL_IVPU_DEBUG) += -DDEBUG
CFLAGS_ivpu_trace_points.o = -I$(src)

39
drivers/accel/ivpu/ivpu_coredump.c Normal file
View File

@ -0,0 +1,39 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020-2024 Intel Corporation
*/
#include <linux/devcoredump.h>
#include <linux/firmware.h>
#include "ivpu_coredump.h"
#include "ivpu_fw.h"
#include "ivpu_gem.h"
#include "vpu_boot_api.h"
#define CRASH_DUMP_HEADER "Intel NPU crash dump"
#define CRASH_DUMP_HEADERS_SIZE SZ_4K
void ivpu_dev_coredump(struct ivpu_device *vdev)
{
struct drm_print_iterator pi = {};
struct drm_printer p;
size_t coredump_size;
char *coredump;
coredump_size = CRASH_DUMP_HEADERS_SIZE + FW_VERSION_HEADER_SIZE +
ivpu_bo_size(vdev->fw->mem_log_crit) + ivpu_bo_size(vdev->fw->mem_log_verb);
coredump = vmalloc(coredump_size);
if (!coredump)
return;
pi.data = coredump;
pi.remain = coredump_size;
p = drm_coredump_printer(&pi);
drm_printf(&p, "%s\n", CRASH_DUMP_HEADER);
drm_printf(&p, "FW version: %s\n", vdev->fw->version);
ivpu_fw_log_print(vdev, false, &p);
dev_coredumpv(vdev->drm.dev, coredump, pi.offset, GFP_KERNEL);
}

25
drivers/accel/ivpu/ivpu_coredump.h Normal file
View File

@ -0,0 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2020-2024 Intel Corporation
*/
#ifndef __IVPU_COREDUMP_H__
#define __IVPU_COREDUMP_H__
#include <drm/drm_print.h>
#include "ivpu_drv.h"
#include "ivpu_fw_log.h"
#ifdef CONFIG_DEV_COREDUMP
void ivpu_dev_coredump(struct ivpu_device *vdev);
#else
static inline void ivpu_dev_coredump(struct ivpu_device *vdev)
{
struct drm_printer p = drm_info_printer(vdev->drm.dev);
ivpu_fw_log_print(vdev, false, &p);
}
#endif
#endif /* __IVPU_COREDUMP_H__ */

90
drivers/accel/ivpu/ivpu_debugfs.c
View File

@ -45,6 +45,14 @@ static int fw_name_show(struct seq_file *s, void *v)
return 0;
}
static int fw_version_show(struct seq_file *s, void *v)
{
struct ivpu_device *vdev = seq_to_ivpu(s);
seq_printf(s, "%s\n", vdev->fw->version);
return 0;
}
static int fw_trace_capability_show(struct seq_file *s, void *v)
{
struct ivpu_device *vdev = seq_to_ivpu(s);
@ -119,6 +127,7 @@ static int firewall_irq_counter_show(struct seq_file *s, void *v)
static const struct drm_debugfs_info vdev_debugfs_list[] = {
{"bo_list", bo_list_show, 0},
{"fw_name", fw_name_show, 0},
{"fw_version", fw_version_show, 0},
{"fw_trace_capability", fw_trace_capability_show, 0},
{"fw_trace_config", fw_trace_config_show, 0},
{"last_bootmode", last_bootmode_show, 0},
@ -127,32 +136,23 @@ static const struct drm_debugfs_info vdev_debugfs_list[] = {
{"firewall_irq_counter", firewall_irq_counter_show, 0},
};
static ssize_t
dvfs_mode_fops_write(struct file *file, const char __user *user_buf, size_t size, loff_t *pos)
static int dvfs_mode_get(void *data, u64 *dvfs_mode)
{
struct ivpu_device *vdev = file->private_data;
struct ivpu_fw_info *fw = vdev->fw;
u32 dvfs_mode;
int ret;
struct ivpu_device *vdev = (struct ivpu_device *)data;
ret = kstrtou32_from_user(user_buf, size, 0, &dvfs_mode);
if (ret < 0)
return ret;
fw->dvfs_mode = dvfs_mode;
ret = pci_try_reset_function(to_pci_dev(vdev->drm.dev));
if (ret)
return ret;
return size;
*dvfs_mode = vdev->fw->dvfs_mode;
return 0;
}
static const struct file_operations dvfs_mode_fops = {
.owner = THIS_MODULE,
.open = simple_open,
.write = dvfs_mode_fops_write,
};
static int dvfs_mode_set(void *data, u64 dvfs_mode)
{
struct ivpu_device *vdev = (struct ivpu_device *)data;
vdev->fw->dvfs_mode = (u32)dvfs_mode;
return pci_try_reset_function(to_pci_dev(vdev->drm.dev));
}
DEFINE_DEBUGFS_ATTRIBUTE(dvfs_mode_fops, dvfs_mode_get, dvfs_mode_set, "%llu\n");
static ssize_t
fw_dyndbg_fops_write(struct file *file, const char __user *user_buf, size_t size, loff_t *pos)
@ -201,7 +201,7 @@ fw_log_fops_write(struct file *file, const char __user *user_buf, size_t size, l
if (!size)
return -EINVAL;
ivpu_fw_log_clear(vdev);
ivpu_fw_log_mark_read(vdev);
return size;
}
@ -346,49 +346,23 @@ static const struct file_operations ivpu_force_recovery_fops = {
.write = ivpu_force_recovery_fn,
};
static ssize_t
ivpu_reset_engine_fn(struct file *file, const char __user *user_buf, size_t size, loff_t *pos)
static int ivpu_reset_engine_fn(void *data, u64 val)
{
struct ivpu_device *vdev = file->private_data;
struct ivpu_device *vdev = (struct ivpu_device *)data;
if (!size)
return -EINVAL;
if (ivpu_jsm_reset_engine(vdev, DRM_IVPU_ENGINE_COMPUTE))
return -ENODEV;
if (ivpu_jsm_reset_engine(vdev, DRM_IVPU_ENGINE_COPY))
return -ENODEV;
return size;
return ivpu_jsm_reset_engine(vdev, (u32)val);
}
static const struct file_operations ivpu_reset_engine_fops = {
.owner = THIS_MODULE,
.open = simple_open,
.write = ivpu_reset_engine_fn,
};
DEFINE_DEBUGFS_ATTRIBUTE(ivpu_reset_engine_fops, NULL, ivpu_reset_engine_fn, "0x%02llx\n");
static ssize_t
ivpu_resume_engine_fn(struct file *file, const char __user *user_buf, size_t size, loff_t *pos)
static int ivpu_resume_engine_fn(void *data, u64 val)
{
struct ivpu_device *vdev = file->private_data;
struct ivpu_device *vdev = (struct ivpu_device *)data;
if (!size)
return -EINVAL;
if (ivpu_jsm_hws_resume_engine(vdev, DRM_IVPU_ENGINE_COMPUTE))
return -ENODEV;
if (ivpu_jsm_hws_resume_engine(vdev, DRM_IVPU_ENGINE_COPY))
return -ENODEV;
return size;
return ivpu_jsm_hws_resume_engine(vdev, (u32)val);
}
static const struct file_operations ivpu_resume_engine_fops = {
.owner = THIS_MODULE,
.open = simple_open,
.write = ivpu_resume_engine_fn,
};
DEFINE_DEBUGFS_ATTRIBUTE(ivpu_resume_engine_fops, NULL, ivpu_resume_engine_fn, "0x%02llx\n");
static int dct_active_get(void *data, u64 *active_percent)
{
@ -432,7 +406,7 @@ void ivpu_debugfs_init(struct ivpu_device *vdev)
debugfs_create_file("force_recovery", 0200, debugfs_root, vdev,
&ivpu_force_recovery_fops);
debugfs_create_file("dvfs_mode", 0200, debugfs_root, vdev,
debugfs_create_file("dvfs_mode", 0644, debugfs_root, vdev,
&dvfs_mode_fops);
debugfs_create_file("fw_dyndbg", 0200, debugfs_root, vdev,

70
drivers/accel/ivpu/ivpu_drv.c
View File

@ -7,6 +7,7 @@
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pm_runtime.h>
#include <generated/utsrelease.h>
#include <drm/drm_accel.h>
#include <drm/drm_file.h>
@ -14,7 +15,7 @@
#include <drm/drm_ioctl.h>
#include <drm/drm_prime.h>
#include "vpu_boot_api.h"
#include "ivpu_coredump.h"
#include "ivpu_debugfs.h"
#include "ivpu_drv.h"
#include "ivpu_fw.h"
@ -29,10 +30,10 @@
#include "ivpu_ms.h"
#include "ivpu_pm.h"
#include "ivpu_sysfs.h"
#include "vpu_boot_api.h"
#ifndef DRIVER_VERSION_STR
#define DRIVER_VERSION_STR __stringify(DRM_IVPU_DRIVER_MAJOR) "." \
__stringify(DRM_IVPU_DRIVER_MINOR) "."
#define DRIVER_VERSION_STR "1.0.0 " UTS_RELEASE
#endif
static struct lock_class_key submitted_jobs_xa_lock_class_key;
@ -42,8 +43,10 @@ module_param_named(dbg_mask, ivpu_dbg_mask, int, 0644);
MODULE_PARM_DESC(dbg_mask, "Driver debug mask. See IVPU_DBG_* macros.");
int ivpu_test_mode;
#if IS_ENABLED(CONFIG_DRM_ACCEL_IVPU_DEBUG)
module_param_named_unsafe(test_mode, ivpu_test_mode, int, 0644);
MODULE_PARM_DESC(test_mode, "Test mode mask. See IVPU_TEST_MODE_* macros.");
#endif
u8 ivpu_pll_min_ratio;
module_param_named(pll_min_ratio, ivpu_pll_min_ratio, byte, 0644);
@ -53,9 +56,9 @@ u8 ivpu_pll_max_ratio = U8_MAX;
module_param_named(pll_max_ratio, ivpu_pll_max_ratio, byte, 0644);
MODULE_PARM_DESC(pll_max_ratio, "Maximum PLL ratio used to set NPU frequency");
int ivpu_sched_mode;
int ivpu_sched_mode = IVPU_SCHED_MODE_AUTO;
module_param_named(sched_mode, ivpu_sched_mode, int, 0444);
MODULE_PARM_DESC(sched_mode, "Scheduler mode: 0 - Default scheduler, 1 - Force HW scheduler");
MODULE_PARM_DESC(sched_mode, "Scheduler mode: -1 - Use default scheduler, 0 - Use OS scheduler, 1 - Use HW scheduler");
bool ivpu_disable_mmu_cont_pages;
module_param_named(disable_mmu_cont_pages, ivpu_disable_mmu_cont_pages, bool, 0444);
@ -85,7 +88,7 @@ static void file_priv_unbind(struct ivpu_device *vdev, struct ivpu_file_priv *fi
ivpu_cmdq_release_all_locked(file_priv);
ivpu_bo_unbind_all_bos_from_context(vdev, &file_priv->ctx);
ivpu_mmu_user_context_fini(vdev, &file_priv->ctx);
ivpu_mmu_context_fini(vdev, &file_priv->ctx);
file_priv->bound = false;
drm_WARN_ON(&vdev->drm, !xa_erase_irq(&vdev->context_xa, file_priv->ctx.id));
}
@ -103,6 +106,8 @@ static void file_priv_release(struct kref *ref)
pm_runtime_get_sync(vdev->drm.dev);
mutex_lock(&vdev->context_list_lock);
file_priv_unbind(vdev, file_priv);
drm_WARN_ON(&vdev->drm, !xa_empty(&file_priv->cmdq_xa));
xa_destroy(&file_priv->cmdq_xa);
mutex_unlock(&vdev->context_list_lock);
pm_runtime_put_autosuspend(vdev->drm.dev);
@ -116,8 +121,6 @@ void ivpu_file_priv_put(struct ivpu_file_priv **link)
struct ivpu_file_priv *file_priv = *link;
struct ivpu_device *vdev = file_priv->vdev;
drm_WARN_ON(&vdev->drm, !file_priv);
ivpu_dbg(vdev, KREF, "file_priv put: ctx %u refcount %u\n",
file_priv->ctx.id, kref_read(&file_priv->ref));
@ -255,9 +258,14 @@ static int ivpu_open(struct drm_device *dev, struct drm_file *file)
goto err_unlock;
}
ret = ivpu_mmu_user_context_init(vdev, &file_priv->ctx, ctx_id);
if (ret)
goto err_xa_erase;
ivpu_mmu_context_init(vdev, &file_priv->ctx, ctx_id);
file_priv->job_limit.min = FIELD_PREP(IVPU_JOB_ID_CONTEXT_MASK, (file_priv->ctx.id - 1));
file_priv->job_limit.max = file_priv->job_limit.min | IVPU_JOB_ID_JOB_MASK;
xa_init_flags(&file_priv->cmdq_xa, XA_FLAGS_ALLOC1);
file_priv->cmdq_limit.min = IVPU_CMDQ_MIN_ID;
file_priv->cmdq_limit.max = IVPU_CMDQ_MAX_ID;
mutex_unlock(&vdev->context_list_lock);
drm_dev_exit(idx);
@ -269,8 +277,6 @@ static int ivpu_open(struct drm_device *dev, struct drm_file *file)
return 0;
err_xa_erase:
xa_erase_irq(&vdev->context_xa, ctx_id);
err_unlock:
mutex_unlock(&vdev->context_list_lock);
mutex_destroy(&file_priv->ms_lock);
@ -346,7 +352,7 @@ static int ivpu_hw_sched_init(struct ivpu_device *vdev)
{
int ret = 0;
if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) {
if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) {
ret = ivpu_jsm_hws_setup_priority_bands(vdev);
if (ret) {
ivpu_err(vdev, "Failed to enable hw scheduler: %d", ret);
@ -380,10 +386,7 @@ int ivpu_boot(struct ivpu_device *vdev)
ret = ivpu_wait_for_ready(vdev);
if (ret) {
ivpu_err(vdev, "Failed to boot the firmware: %d\n", ret);
ivpu_hw_diagnose_failure(vdev);
ivpu_mmu_evtq_dump(vdev);
ivpu_fw_log_dump(vdev);
return ret;
goto err_diagnose_failure;
}
ivpu_hw_irq_clear(vdev);
@ -394,12 +397,20 @@ int ivpu_boot(struct ivpu_device *vdev)
if (ivpu_fw_is_cold_boot(vdev)) {
ret = ivpu_pm_dct_init(vdev);
if (ret)
return ret;
goto err_diagnose_failure;
return ivpu_hw_sched_init(vdev);
ret = ivpu_hw_sched_init(vdev);
if (ret)
goto err_diagnose_failure;
}
return 0;
err_diagnose_failure:
ivpu_hw_diagnose_failure(vdev);
ivpu_mmu_evtq_dump(vdev);
ivpu_dev_coredump(vdev);
return ret;
}
void ivpu_prepare_for_reset(struct ivpu_device *vdev)
@ -446,9 +457,16 @@ static const struct drm_driver driver = {
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
#ifdef DRIVER_DATE
.date = DRIVER_DATE,
.major = DRM_IVPU_DRIVER_MAJOR,
.minor = DRM_IVPU_DRIVER_MINOR,
.major = DRIVER_MAJOR,
.minor = DRIVER_MINOR,
.patchlevel = DRIVER_PATCHLEVEL,
#else
.date = UTS_RELEASE,
.major = 1,
#endif
};
static void ivpu_context_abort_invalid(struct ivpu_device *vdev)
@ -606,6 +624,9 @@ static int ivpu_dev_init(struct ivpu_device *vdev)
lockdep_set_class(&vdev->submitted_jobs_xa.xa_lock, &submitted_jobs_xa_lock_class_key);
INIT_LIST_HEAD(&vdev->bo_list);
vdev->db_limit.min = IVPU_MIN_DB;
vdev->db_limit.max = IVPU_MAX_DB;
ret = drmm_mutex_init(&vdev->drm, &vdev->context_list_lock);
if (ret)
goto err_xa_destroy;
@ -632,9 +653,7 @@ static int ivpu_dev_init(struct ivpu_device *vdev)
if (ret)
goto err_shutdown;
ret = ivpu_mmu_global_context_init(vdev);
if (ret)
goto err_shutdown;
ivpu_mmu_global_context_init(vdev);
ret = ivpu_mmu_init(vdev);
if (ret)
@ -722,6 +741,7 @@ static struct pci_device_id ivpu_pci_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_MTL) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_ARL) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_LNL) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PTL_P) },
{ }
};
MODULE_DEVICE_TABLE(pci, ivpu_pci_ids);

37
drivers/accel/ivpu/ivpu_drv.h
View File

@ -21,11 +21,11 @@
#define DRIVER_NAME "intel_vpu"
#define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"
#define DRIVER_DATE "20230117"
#define PCI_DEVICE_ID_MTL 0x7d1d
#define PCI_DEVICE_ID_ARL 0xad1d
#define PCI_DEVICE_ID_LNL 0x643e
#define PCI_DEVICE_ID_MTL 0x7d1d
#define PCI_DEVICE_ID_ARL 0xad1d
#define PCI_DEVICE_ID_LNL 0x643e
#define PCI_DEVICE_ID_PTL_P 0xb03e
#define IVPU_HW_IP_37XX 37
#define IVPU_HW_IP_40XX 40
@ -46,17 +46,22 @@
#define IVPU_MIN_DB 1
#define IVPU_MAX_DB 255
#define IVPU_NUM_ENGINES 2
#define IVPU_NUM_PRIORITIES 4
#define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_ENGINES * IVPU_NUM_PRIORITIES)
#define IVPU_JOB_ID_JOB_MASK GENMASK(7, 0)
#define IVPU_JOB_ID_CONTEXT_MASK GENMASK(31, 8)
#define IVPU_CMDQ_INDEX(engine, priority) ((engine) * IVPU_NUM_PRIORITIES + (priority))
#define IVPU_NUM_PRIORITIES 4
#define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_PRIORITIES)
#define IVPU_CMDQ_MIN_ID 1
#define IVPU_CMDQ_MAX_ID 255
#define IVPU_PLATFORM_SILICON 0
#define IVPU_PLATFORM_SIMICS 2
#define IVPU_PLATFORM_FPGA 3
#define IVPU_PLATFORM_INVALID 8
#define IVPU_SCHED_MODE_AUTO -1
#define IVPU_DBG_REG BIT(0)
#define IVPU_DBG_IRQ BIT(1)
#define IVPU_DBG_MMU BIT(2)
@ -134,6 +139,8 @@ struct ivpu_device {
struct xa_limit context_xa_limit;
struct xarray db_xa;
struct xa_limit db_limit;
u32 db_next;
struct mutex bo_list_lock; /* Protects bo_list */
struct list_head bo_list;
@ -152,6 +159,7 @@ struct ivpu_device {
int tdr;
int autosuspend;
int d0i3_entry_msg;
int state_dump_msg;
} timeout;
};
@ -163,11 +171,15 @@ struct ivpu_file_priv {
struct kref ref;
struct ivpu_device *vdev;
struct mutex lock; /* Protects cmdq */
struct ivpu_cmdq *cmdq[IVPU_NUM_CMDQS_PER_CTX];
struct xarray cmdq_xa;
struct ivpu_mmu_context ctx;
struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */
struct list_head ms_instance_list;
struct ivpu_bo *ms_info_bo;
struct xa_limit job_limit;
u32 job_id_next;
struct xa_limit cmdq_limit;
u32 cmdq_id_next;
bool has_mmu_faults;
bool bound;
bool aborted;
@ -185,9 +197,9 @@ extern bool ivpu_force_snoop;
#define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2)
#define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4)
#define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5)
#define IVPU_TEST_MODE_PREEMPTION_DISABLE BIT(6)
#define IVPU_TEST_MODE_HWS_EXTRA_EVENTS BIT(7)
#define IVPU_TEST_MODE_MIP_DISABLE BIT(6)
#define IVPU_TEST_MODE_DISABLE_TIMEOUTS BIT(8)
#define IVPU_TEST_MODE_TURBO BIT(9)
extern int ivpu_test_mode;
struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
@ -215,6 +227,8 @@ static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev)
return IVPU_HW_IP_37XX;
case PCI_DEVICE_ID_LNL:
return IVPU_HW_IP_40XX;
case PCI_DEVICE_ID_PTL_P:
return IVPU_HW_IP_50XX;
default:
dump_stack();
ivpu_err(vdev, "Unknown NPU IP generation\n");
@ -229,6 +243,7 @@ static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev)
case PCI_DEVICE_ID_ARL:
return IVPU_HW_BTRS_MTL;
case PCI_DEVICE_ID_LNL:
case PCI_DEVICE_ID_PTL_P:
return IVPU_HW_BTRS_LNL;
default:
dump_stack();

37
drivers/accel/ivpu/ivpu_fw.c
View File

@ -25,7 +25,6 @@
#define FW_SHAVE_NN_MAX_SIZE SZ_2M
#define FW_RUNTIME_MIN_ADDR (FW_GLOBAL_MEM_START)
#define FW_RUNTIME_MAX_ADDR (FW_GLOBAL_MEM_END - FW_SHARED_MEM_SIZE)
#define FW_VERSION_HEADER_SIZE SZ_4K
#define FW_FILE_IMAGE_OFFSET (VPU_FW_HEADER_SIZE + FW_VERSION_HEADER_SIZE)
#define WATCHDOG_MSS_REDIRECT 32
@ -47,8 +46,10 @@
#define IVPU_FOCUS_PRESENT_TIMER_MS 1000
static char *ivpu_firmware;
#if IS_ENABLED(CONFIG_DRM_ACCEL_IVPU_DEBUG)
module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644);
MODULE_PARM_DESC(firmware, "NPU firmware binary in /lib/firmware/..");
#endif
static struct {
int gen;
@ -58,11 +59,14 @@ static struct {
{ IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v0.0.bin" },
{ IVPU_HW_IP_40XX, "vpu_40xx.bin" },
{ IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v0.0.bin" },
{ IVPU_HW_IP_50XX, "vpu_50xx.bin" },
{ IVPU_HW_IP_50XX, "intel/vpu/vpu_50xx_v0.0.bin" },
};
/* Production fw_names from the table above */
MODULE_FIRMWARE("intel/vpu/vpu_37xx_v0.0.bin");
MODULE_FIRMWARE("intel/vpu/vpu_40xx_v0.0.bin");
MODULE_FIRMWARE("intel/vpu/vpu_50xx_v0.0.bin");
static int ivpu_fw_request(struct ivpu_device *vdev)
{
@ -135,6 +139,15 @@ static bool is_within_range(u64 addr, size_t size, u64 range_start, size_t range
return true;
}
static u32
ivpu_fw_sched_mode_select(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr)
{
if (ivpu_sched_mode != IVPU_SCHED_MODE_AUTO)
return ivpu_sched_mode;
return VPU_SCHEDULING_MODE_OS;
}
static int ivpu_fw_parse(struct ivpu_device *vdev)
{
struct ivpu_fw_info *fw = vdev->fw;
@ -191,8 +204,10 @@ static int ivpu_fw_parse(struct ivpu_device *vdev)
ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n",
fw_hdr->header_version, fw_hdr->image_format);
ivpu_info(vdev, "Firmware: %s, version: %s", fw->name,
(const char *)fw_hdr + VPU_FW_HEADER_SIZE);
if (!scnprintf(fw->version, sizeof(fw->version), "%s", fw->file->data + VPU_FW_HEADER_SIZE))
ivpu_warn(vdev, "Missing firmware version\n");
ivpu_info(vdev, "Firmware: %s, version: %s\n", fw->name, fw->version);
if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, BOOT, 3))
return -EINVAL;
@ -208,14 +223,16 @@ static int ivpu_fw_parse(struct ivpu_device *vdev)
fw->cold_boot_entry_point = fw_hdr->entry_point;
fw->entry_point = fw->cold_boot_entry_point;
fw->trace_level = min_t(u32, ivpu_log_level, IVPU_FW_LOG_FATAL);
fw->trace_level = min_t(u32, ivpu_fw_log_level, IVPU_FW_LOG_FATAL);
fw->trace_destination_mask = VPU_TRACE_DESTINATION_VERBOSE_TRACING;
fw->trace_hw_component_mask = -1;
fw->dvfs_mode = 0;
fw->sched_mode = ivpu_fw_sched_mode_select(vdev, fw_hdr);
fw->primary_preempt_buf_size = fw_hdr->preemption_buffer_1_size;
fw->secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_size;
ivpu_info(vdev, "Scheduler mode: %s\n", fw->sched_mode ? "HW" : "OS");
if (fw_hdr->ro_section_start_address && !is_within_range(fw_hdr->ro_section_start_address,
fw_hdr->ro_section_size,
@ -311,7 +328,7 @@ static int ivpu_fw_mem_init(struct ivpu_device *vdev)
goto err_free_fw_mem;
}
if (ivpu_log_level <= IVPU_FW_LOG_INFO)
if (ivpu_fw_log_level <= IVPU_FW_LOG_INFO)
log_verb_size = IVPU_FW_VERBOSE_BUFFER_LARGE_SIZE;
else
log_verb_size = IVPU_FW_VERBOSE_BUFFER_SMALL_SIZE;
@ -567,8 +584,10 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params
boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ivpu_bo_size(ipc_mem_rx) / 2;
boot_params->ipc_payload_area_size = ivpu_bo_size(ipc_mem_rx) / 2;
boot_params->global_aliased_pio_base = vdev->hw->ranges.user.start;
boot_params->global_aliased_pio_size = ivpu_hw_range_size(&vdev->hw->ranges.user);
if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
boot_params->global_aliased_pio_base = vdev->hw->ranges.user.start;
boot_params->global_aliased_pio_size = ivpu_hw_range_size(&vdev->hw->ranges.user);
}
/* Allow configuration for L2C_PAGE_TABLE with boot param value */
boot_params->autoconfig = 1;
@ -604,8 +623,8 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params
boot_params->punit_telemetry_sram_base = ivpu_hw_telemetry_offset_get(vdev);
boot_params->punit_telemetry_sram_size = ivpu_hw_telemetry_size_get(vdev);
boot_params->vpu_telemetry_enable = ivpu_hw_telemetry_enable_get(vdev);
boot_params->vpu_scheduling_mode = vdev->hw->sched_mode;
if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW)
boot_params->vpu_scheduling_mode = vdev->fw->sched_mode;
if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW)
boot_params->vpu_focus_present_timer_ms = IVPU_FOCUS_PRESENT_TIMER_MS;
boot_params->dvfs_mode = vdev->fw->dvfs_mode;
if (!IVPU_WA(disable_d0i3_msg))

9
drivers/accel/ivpu/ivpu_fw.h
View File

@ -1,11 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2020-2023 Intel Corporation
* Copyright (C) 2020-2024 Intel Corporation
*/
#ifndef __IVPU_FW_H__
#define __IVPU_FW_H__
#include "vpu_jsm_api.h"
#define FW_VERSION_HEADER_SIZE SZ_4K
#define FW_VERSION_STR_SIZE SZ_256
struct ivpu_device;
struct ivpu_bo;
struct vpu_boot_params;
@ -13,6 +18,7 @@ struct vpu_boot_params;
struct ivpu_fw_info {
const struct firmware *file;
const char *name;
char version[FW_VERSION_STR_SIZE];
struct ivpu_bo *mem;
struct ivpu_bo *mem_shave_nn;
struct ivpu_bo *mem_log_crit;
@ -32,6 +38,7 @@ struct ivpu_fw_info {
u32 secondary_preempt_buf_size;
u64 read_only_addr;
u32 read_only_size;
u32 sched_mode;
};
int ivpu_fw_init(struct ivpu_device *vdev);

119
drivers/accel/ivpu/ivpu_fw_log.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020-2023 Intel Corporation
* Copyright (C) 2020-2024 Intel Corporation
*/
#include <linux/ctype.h>
@ -15,19 +15,19 @@
#include "ivpu_fw_log.h"
#include "ivpu_gem.h"
#define IVPU_FW_LOG_LINE_LENGTH 256
#define IVPU_FW_LOG_LINE_LENGTH 256
unsigned int ivpu_log_level = IVPU_FW_LOG_ERROR;
module_param(ivpu_log_level, uint, 0444);
MODULE_PARM_DESC(ivpu_log_level,
"NPU firmware default trace level: debug=" __stringify(IVPU_FW_LOG_DEBUG)
unsigned int ivpu_fw_log_level = IVPU_FW_LOG_ERROR;
module_param_named(fw_log_level, ivpu_fw_log_level, uint, 0444);
MODULE_PARM_DESC(fw_log_level,
"NPU firmware default log level: debug=" __stringify(IVPU_FW_LOG_DEBUG)
" info=" __stringify(IVPU_FW_LOG_INFO)
" warn=" __stringify(IVPU_FW_LOG_WARN)
" error=" __stringify(IVPU_FW_LOG_ERROR)
" fatal=" __stringify(IVPU_FW_LOG_FATAL));
static int fw_log_ptr(struct ivpu_device *vdev, struct ivpu_bo *bo, u32 *offset,
struct vpu_tracing_buffer_header **log_header)
static int fw_log_from_bo(struct ivpu_device *vdev, struct ivpu_bo *bo, u32 *offset,
struct vpu_tracing_buffer_header **out_log)
{
struct vpu_tracing_buffer_header *log;
@ -48,7 +48,7 @@ static int fw_log_ptr(struct ivpu_device *vdev, struct ivpu_bo *bo, u32 *offset,
return -EINVAL;
}
*log_header = log;
*out_log = log;
*offset += log->size;
ivpu_dbg(vdev, FW_BOOT,
@ -59,7 +59,7 @@ static int fw_log_ptr(struct ivpu_device *vdev, struct ivpu_bo *bo, u32 *offset,
return 0;
}
static void buffer_print(char *buffer, u32 size, struct drm_printer *p)
static void fw_log_print_lines(char *buffer, u32 size, struct drm_printer *p)
{
char line[IVPU_FW_LOG_LINE_LENGTH];
u32 index = 0;
@ -87,56 +87,89 @@ static void buffer_print(char *buffer, u32 size, struct drm_printer *p)
}
line[index] = 0;
if (index != 0)
drm_printf(p, "%s\n", line);
drm_printf(p, "%s", line);
}
static void fw_log_print_buffer(struct ivpu_device *vdev, struct vpu_tracing_buffer_header *log,
const char *prefix, bool only_new_msgs, struct drm_printer *p)
static void fw_log_print_buffer(struct vpu_tracing_buffer_header *log, const char *prefix,
bool only_new_msgs, struct drm_printer *p)
{
char *log_buffer = (void *)log + log->header_size;
u32 log_size = log->size - log->header_size;
u32 log_start = log->read_index;
u32 log_end = log->write_index;
char *log_data = (void *)log + log->header_size;
u32 data_size = log->size - log->header_size;
u32 log_start = only_new_msgs ? READ_ONCE(log->read_index) : 0;
u32 log_end = READ_ONCE(log->write_index);
if (!(log->write_index || log->wrap_count) ||
(log->write_index == log->read_index && only_new_msgs)) {
drm_printf(p, "==== %s \"%s\" log empty ====\n", prefix, log->name);
return;
if (log->wrap_count == log->read_wrap_count) {
if (log_end <= log_start) {
drm_printf(p, "==== %s \"%s\" log empty ====\n", prefix, log->name);
return;
}
} else if (log->wrap_count == log->read_wrap_count + 1) {
if (log_end > log_start)
log_start = log_end;
} else {
log_start = log_end;
}
drm_printf(p, "==== %s \"%s\" log start ====\n", prefix, log->name);
if (log->write_index > log->read_index) {
buffer_print(log_buffer + log_start, log_end - log_start, p);
if (log_end > log_start) {
fw_log_print_lines(log_data + log_start, log_end - log_start, p);
} else {
buffer_print(log_buffer + log_end, log_size - log_end, p);
buffer_print(log_buffer, log_end, p);
fw_log_print_lines(log_data + log_start, data_size - log_start, p);
fw_log_print_lines(log_data, log_end, p);
}
drm_printf(p, "\x1b[0m");
drm_printf(p, "\n\x1b[0m"); /* add new line and clear formatting */
drm_printf(p, "==== %s \"%s\" log end ====\n", prefix, log->name);
}
static void
fw_log_print_all_in_bo(struct ivpu_device *vdev, const char *name,
struct ivpu_bo *bo, bool only_new_msgs, struct drm_printer *p)
{
struct vpu_tracing_buffer_header *log;
u32 next = 0;
while (fw_log_from_bo(vdev, bo, &next, &log) == 0)
fw_log_print_buffer(log, name, only_new_msgs, p);
}
void ivpu_fw_log_print(struct ivpu_device *vdev, bool only_new_msgs, struct drm_printer *p)
{
struct vpu_tracing_buffer_header *log_header;
u32 next = 0;
while (fw_log_ptr(vdev, vdev->fw->mem_log_crit, &next, &log_header) == 0)
fw_log_print_buffer(vdev, log_header, "NPU critical", only_new_msgs, p);
next = 0;
while (fw_log_ptr(vdev, vdev->fw->mem_log_verb, &next, &log_header) == 0)
fw_log_print_buffer(vdev, log_header, "NPU verbose", only_new_msgs, p);
fw_log_print_all_in_bo(vdev, "NPU critical", vdev->fw->mem_log_crit, only_new_msgs, p);
fw_log_print_all_in_bo(vdev, "NPU verbose", vdev->fw->mem_log_verb, only_new_msgs, p);
}
void ivpu_fw_log_clear(struct ivpu_device *vdev)
void ivpu_fw_log_mark_read(struct ivpu_device *vdev)
{
struct vpu_tracing_buffer_header *log_header;
u32 next = 0;
while (fw_log_ptr(vdev, vdev->fw->mem_log_crit, &next, &log_header) == 0)
log_header->read_index = log_header->write_index;
struct vpu_tracing_buffer_header *log;
u32 next;
next = 0;
while (fw_log_ptr(vdev, vdev->fw->mem_log_verb, &next, &log_header) == 0)
log_header->read_index = log_header->write_index;
while (fw_log_from_bo(vdev, vdev->fw->mem_log_crit, &next, &log) == 0) {
log->read_index = READ_ONCE(log->write_index);
log->read_wrap_count = READ_ONCE(log->wrap_count);
}
next = 0;
while (fw_log_from_bo(vdev, vdev->fw->mem_log_verb, &next, &log) == 0) {
log->read_index = READ_ONCE(log->write_index);
log->read_wrap_count = READ_ONCE(log->wrap_count);
}
}
void ivpu_fw_log_reset(struct ivpu_device *vdev)
{
struct vpu_tracing_buffer_header *log;
u32 next;
next = 0;
while (fw_log_from_bo(vdev, vdev->fw->mem_log_crit, &next, &log) == 0) {
log->read_index = 0;
log->read_wrap_count = 0;
}
next = 0;
while (fw_log_from_bo(vdev, vdev->fw->mem_log_verb, &next, &log) == 0) {
log->read_index = 0;
log->read_wrap_count = 0;
}
}

17
drivers/accel/ivpu/ivpu_fw_log.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2020-2023 Intel Corporation
* Copyright (C) 2020-2024 Intel Corporation
*/
#ifndef __IVPU_FW_LOG_H__
@ -8,8 +8,6 @@
#include <linux/types.h>
#include <drm/drm_print.h>
#include "ivpu_drv.h"
#define IVPU_FW_LOG_DEFAULT 0
@ -19,20 +17,15 @@
#define IVPU_FW_LOG_ERROR 4
#define IVPU_FW_LOG_FATAL 5
extern unsigned int ivpu_log_level;
#define IVPU_FW_VERBOSE_BUFFER_SMALL_SIZE SZ_1M
#define IVPU_FW_VERBOSE_BUFFER_LARGE_SIZE SZ_8M
#define IVPU_FW_CRITICAL_BUFFER_SIZE SZ_512K
extern unsigned int ivpu_fw_log_level;
void ivpu_fw_log_print(struct ivpu_device *vdev, bool only_new_msgs, struct drm_printer *p);
void ivpu_fw_log_clear(struct ivpu_device *vdev);
void ivpu_fw_log_mark_read(struct ivpu_device *vdev);
void ivpu_fw_log_reset(struct ivpu_device *vdev);
static inline void ivpu_fw_log_dump(struct ivpu_device *vdev)
{
struct drm_printer p = drm_info_printer(vdev->drm.dev);
ivpu_fw_log_print(vdev, false, &p);
}
#endif /* __IVPU_FW_LOG_H__ */

3
drivers/accel/ivpu/ivpu_gem.c
View File

@ -384,6 +384,9 @@ int ivpu_bo_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file
timeout = drm_timeout_abs_to_jiffies(args->timeout_ns);
/* Add 1 jiffy to ensure the wait function never times out before intended timeout_ns */
timeout += 1;
obj = drm_gem_object_lookup(file, args->handle);
if (!obj)
return -EINVAL;

15
drivers/accel/ivpu/ivpu_hw.c
View File

@ -89,12 +89,14 @@ static void timeouts_init(struct ivpu_device *vdev)
vdev->timeout.tdr = 2000000;
vdev->timeout.autosuspend = -1;
vdev->timeout.d0i3_entry_msg = 500;
vdev->timeout.state_dump_msg = 10;
} else if (ivpu_is_simics(vdev)) {
vdev->timeout.boot = 50;
vdev->timeout.jsm = 500;
vdev->timeout.tdr = 10000;
vdev->timeout.autosuspend = -1;
vdev->timeout.autosuspend = 100;
vdev->timeout.d0i3_entry_msg = 100;
vdev->timeout.state_dump_msg = 10;
} else {
vdev->timeout.boot = 1000;
vdev->timeout.jsm = 500;
@ -104,6 +106,7 @@ static void timeouts_init(struct ivpu_device *vdev)
else
vdev->timeout.autosuspend = 100;
vdev->timeout.d0i3_entry_msg = 5;
vdev->timeout.state_dump_msg = 10;
}
}
@ -111,14 +114,14 @@ static void memory_ranges_init(struct ivpu_device *vdev)
{
if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
ivpu_hw_range_init(&vdev->hw->ranges.global, 0x80000000, SZ_512M);
ivpu_hw_range_init(&vdev->hw->ranges.user, 0xc0000000, 255 * SZ_1M);
ivpu_hw_range_init(&vdev->hw->ranges.user, 0x88000000, 511 * SZ_1M);
ivpu_hw_range_init(&vdev->hw->ranges.shave, 0x180000000, SZ_2G);
ivpu_hw_range_init(&vdev->hw->ranges.dma, 0x200000000, SZ_8G);
ivpu_hw_range_init(&vdev->hw->ranges.dma, 0x200000000, SZ_128G);
} else {
ivpu_hw_range_init(&vdev->hw->ranges.global, 0x80000000, SZ_512M);
ivpu_hw_range_init(&vdev->hw->ranges.user, 0x80000000, SZ_256M);
ivpu_hw_range_init(&vdev->hw->ranges.shave, 0x80000000 + SZ_256M, SZ_2G - SZ_256M);
ivpu_hw_range_init(&vdev->hw->ranges.dma, 0x200000000, SZ_8G);
ivpu_hw_range_init(&vdev->hw->ranges.shave, 0x80000000, SZ_2G);
ivpu_hw_range_init(&vdev->hw->ranges.user, 0x100000000, SZ_256G);
vdev->hw->ranges.dma = vdev->hw->ranges.user;
}
}

1
drivers/accel/ivpu/ivpu_hw.h
View File

@ -46,7 +46,6 @@ struct ivpu_hw_info {
u32 profiling_freq;
} pll;
u32 tile_fuse;
u32 sched_mode;
u32 sku;
u16 config;
int dma_bits;

2
drivers/accel/ivpu/ivpu_hw_40xx_reg.h
View File

@ -115,6 +115,8 @@
#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY 0x00030068u
#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST_DLY_MASK GENMASK(7, 0)
#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST1_DLY_MASK GENMASK(15, 8)
#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST2_DLY_MASK GENMASK(23, 16)
#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY 0x0003006cu
#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY_STATUS_DLY_MASK GENMASK(7, 0)

21
drivers/accel/ivpu/ivpu_hw_btrs.c
View File

@ -141,16 +141,10 @@ static int read_tile_config_fuse(struct ivpu_device *vdev, u32 *tile_fuse_config
}
config = REG_GET_FLD(VPU_HW_BTRS_LNL_TILE_FUSE, CONFIG, fuse);
if (!tile_disable_check(config)) {
ivpu_err(vdev, "Fuse: Invalid tile disable config (0x%x)\n", config);
return -EIO;
}
if (!tile_disable_check(config))
ivpu_warn(vdev, "More than 1 tile disabled, tile fuse config mask: 0x%x\n", config);
if (config)
ivpu_dbg(vdev, MISC, "Fuse: %d tiles enabled. Tile number %d disabled\n",
BTRS_LNL_TILE_MAX_NUM - 1, ffs(config) - 1);
else
ivpu_dbg(vdev, MISC, "Fuse: All %d tiles enabled\n", BTRS_LNL_TILE_MAX_NUM);
ivpu_dbg(vdev, MISC, "Tile disable config mask: 0x%x\n", config);
*tile_fuse_config = config;
return 0;
@ -163,7 +157,6 @@ static int info_init_mtl(struct ivpu_device *vdev)
hw->tile_fuse = BTRS_MTL_TILE_FUSE_ENABLE_BOTH;
hw->sku = BTRS_MTL_TILE_SKU_BOTH;
hw->config = BTRS_MTL_WP_CONFIG_2_TILE_4_3_RATIO;
hw->sched_mode = ivpu_sched_mode;
return 0;
}
@ -178,7 +171,6 @@ static int info_init_lnl(struct ivpu_device *vdev)
if (ret)
return ret;
hw->sched_mode = ivpu_sched_mode;
hw->tile_fuse = tile_fuse_config;
hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
@ -315,10 +307,6 @@ static void prepare_wp_request(struct ivpu_device *vdev, struct wp_request *wp,
wp->cdyn = enable ? PLL_CDYN_DEFAULT : 0;
wp->epp = enable ? PLL_EPP_DEFAULT : 0;
}
/* Simics cannot start without at least one tile */
if (enable && ivpu_is_simics(vdev))
wp->cfg = 1;
}
static int wait_for_pll_lock(struct ivpu_device *vdev, bool enable)
@ -465,9 +453,6 @@ int ivpu_hw_btrs_wait_for_clock_res_own_ack(struct ivpu_device *vdev)
if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
return 0;
if (ivpu_is_simics(vdev))
return 0;
return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, CLOCK_RESOURCE_OWN_ACK, 1, TIMEOUT_US);
}

57
drivers/accel/ivpu/ivpu_hw_ip.c
View File

@ -8,15 +8,12 @@
#include "ivpu_hw.h"
#include "ivpu_hw_37xx_reg.h"
#include "ivpu_hw_40xx_reg.h"
#include "ivpu_hw_btrs.h"
#include "ivpu_hw_ip.h"
#include "ivpu_hw_reg_io.h"
#include "ivpu_mmu.h"
#include "ivpu_pm.h"
#define PWR_ISLAND_EN_POST_DLY_FREQ_DEFAULT 0
#define PWR_ISLAND_EN_POST_DLY_FREQ_HIGH 18
#define PWR_ISLAND_STATUS_DLY_FREQ_DEFAULT 3
#define PWR_ISLAND_STATUS_DLY_FREQ_HIGH 46
#define PWR_ISLAND_STATUS_TIMEOUT_US (5 * USEC_PER_MSEC)
#define TIM_SAFE_ENABLE 0xf1d0dead
@ -268,20 +265,15 @@ void ivpu_hw_ip_idle_gen_disable(struct ivpu_device *vdev)
idle_gen_drive_40xx(vdev, false);
}
static void pwr_island_delay_set_50xx(struct ivpu_device *vdev)
static void
pwr_island_delay_set_50xx(struct ivpu_device *vdev, u32 post, u32 post1, u32 post2, u32 status)
{
u32 val, post, status;
if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT) {
post = PWR_ISLAND_EN_POST_DLY_FREQ_DEFAULT;
status = PWR_ISLAND_STATUS_DLY_FREQ_DEFAULT;
} else {
post = PWR_ISLAND_EN_POST_DLY_FREQ_HIGH;
status = PWR_ISLAND_STATUS_DLY_FREQ_HIGH;
}
u32 val;
val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY);
val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST_DLY, post, val);
val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST1_DLY, post1, val);
val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST2_DLY, post2, val);
REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, val);
val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY);
@ -311,9 +303,6 @@ static void pwr_island_trickle_drive_40xx(struct ivpu_device *vdev, bool enable)
val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);
REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);
if (enable)
ndelay(500);
}
static void pwr_island_drive_37xx(struct ivpu_device *vdev, bool enable)
@ -326,9 +315,6 @@ static void pwr_island_drive_37xx(struct ivpu_device *vdev, bool enable)
val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
if (!enable)
ndelay(500);
}
static void pwr_island_drive_40xx(struct ivpu_device *vdev, bool enable)
@ -347,9 +333,11 @@ static void pwr_island_enable(struct ivpu_device *vdev)
{
if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
pwr_island_trickle_drive_37xx(vdev, true);
ndelay(500);
pwr_island_drive_37xx(vdev, true);
} else {
pwr_island_trickle_drive_40xx(vdev, true);
ndelay(500);
pwr_island_drive_40xx(vdev, true);
}
}
@ -686,13 +674,36 @@ static void dpu_active_drive_37xx(struct ivpu_device *vdev, bool enable)
REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val);
}
static void pwr_island_delay_set(struct ivpu_device *vdev)
{
bool high = vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_HIGH;
u32 post, post1, post2, status;
if (ivpu_hw_ip_gen(vdev) < IVPU_HW_IP_50XX)
return;
switch (ivpu_device_id(vdev)) {
case PCI_DEVICE_ID_PTL_P:
post = high ? 18 : 0;
post1 = 0;
post2 = 0;
status = high ? 46 : 3;
break;
default:
dump_stack();
ivpu_err(vdev, "Unknown device ID\n");
return;
}
pwr_island_delay_set_50xx(vdev, post, post1, post2, status);
}
int ivpu_hw_ip_pwr_domain_enable(struct ivpu_device *vdev)
{
int ret;
if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_50XX)
pwr_island_delay_set_50xx(vdev);
pwr_island_delay_set(vdev);
pwr_island_enable(vdev);
ret = wait_for_pwr_island_status(vdev, 0x1);

45
drivers/accel/ivpu/ivpu_ipc.c
View File

@ -15,6 +15,7 @@
#include "ivpu_ipc.h"
#include "ivpu_jsm_msg.h"
#include "ivpu_pm.h"
#include "ivpu_trace.h"
#define IPC_MAX_RX_MSG 128
@ -227,6 +228,7 @@ int ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, stru
goto unlock;
ivpu_ipc_tx(vdev, cons->tx_vpu_addr);
trace_jsm("[tx]", req);
unlock:
mutex_unlock(&ipc->lock);
@ -278,12 +280,13 @@ int ivpu_ipc_receive(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
u32 size = min_t(int, rx_msg->ipc_hdr->data_size, sizeof(*jsm_msg));
if (rx_msg->jsm_msg->result != VPU_JSM_STATUS_SUCCESS) {
ivpu_dbg(vdev, IPC, "IPC resp result error: %d\n", rx_msg->jsm_msg->result);
ivpu_err(vdev, "IPC resp result error: %d\n", rx_msg->jsm_msg->result);
ret = -EBADMSG;
}
if (jsm_msg)
memcpy(jsm_msg, rx_msg->jsm_msg, size);
trace_jsm("[rx]", rx_msg->jsm_msg);
}
ivpu_ipc_rx_msg_del(vdev, rx_msg);
@ -291,15 +294,16 @@ int ivpu_ipc_receive(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
return ret;
}
static int
int
ivpu_ipc_send_receive_internal(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
enum vpu_ipc_msg_type expected_resp_type,
struct vpu_jsm_msg *resp, u32 channel,
unsigned long timeout_ms)
struct vpu_jsm_msg *resp, u32 channel, unsigned long timeout_ms)
{
struct ivpu_ipc_consumer cons;
int ret;
drm_WARN_ON(&vdev->drm, pm_runtime_status_suspended(vdev->drm.dev));
ivpu_ipc_consumer_add(vdev, &cons, channel, NULL);
ret = ivpu_ipc_send(vdev, &cons, req);
@ -325,19 +329,21 @@ consumer_del:
return ret;
}
int ivpu_ipc_send_receive_active(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
enum vpu_ipc_msg_type expected_resp, struct vpu_jsm_msg *resp,
u32 channel, unsigned long timeout_ms)
int ivpu_ipc_send_receive(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
enum vpu_ipc_msg_type expected_resp, struct vpu_jsm_msg *resp,
u32 channel, unsigned long timeout_ms)
{
struct vpu_jsm_msg hb_req = { .type = VPU_JSM_MSG_QUERY_ENGINE_HB };
struct vpu_jsm_msg hb_resp;
int ret, hb_ret;
drm_WARN_ON(&vdev->drm, pm_runtime_status_suspended(vdev->drm.dev));
ret = ivpu_rpm_get(vdev);
if (ret < 0)
return ret;
ret = ivpu_ipc_send_receive_internal(vdev, req, expected_resp, resp, channel, timeout_ms);
if (ret != -ETIMEDOUT)
return ret;
goto rpm_put;
hb_ret = ivpu_ipc_send_receive_internal(vdev, &hb_req, VPU_JSM_MSG_QUERY_ENGINE_HB_DONE,
&hb_resp, VPU_IPC_CHAN_ASYNC_CMD,
@ -345,21 +351,33 @@ int ivpu_ipc_send_receive_active(struct ivpu_device *vdev, struct vpu_jsm_msg *r
if (hb_ret == -ETIMEDOUT)
ivpu_pm_trigger_recovery(vdev, "IPC timeout");
rpm_put:
ivpu_rpm_put(vdev);
return ret;
}
int ivpu_ipc_send_receive(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
enum vpu_ipc_msg_type expected_resp, struct vpu_jsm_msg *resp,
u32 channel, unsigned long timeout_ms)
int ivpu_ipc_send_and_wait(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
u32 channel, unsigned long timeout_ms)
{
struct ivpu_ipc_consumer cons;
int ret;
ret = ivpu_rpm_get(vdev);
if (ret < 0)
return ret;
ret = ivpu_ipc_send_receive_active(vdev, req, expected_resp, resp, channel, timeout_ms);
ivpu_ipc_consumer_add(vdev, &cons, channel, NULL);
ret = ivpu_ipc_send(vdev, &cons, req);
if (ret) {
ivpu_warn_ratelimited(vdev, "IPC send failed: %d\n", ret);
goto consumer_del;
}
msleep(timeout_ms);
consumer_del:
ivpu_ipc_consumer_del(vdev, &cons);
ivpu_rpm_put(vdev);
return ret;
}
@ -518,7 +536,6 @@ void ivpu_ipc_fini(struct ivpu_device *vdev)
{
struct ivpu_ipc_info *ipc = vdev->ipc;
drm_WARN_ON(&vdev->drm, ipc->on);
drm_WARN_ON(&vdev->drm, !list_empty(&ipc->cons_list));
drm_WARN_ON(&vdev->drm, !list_empty(&ipc->cb_msg_list));
drm_WARN_ON(&vdev->drm, atomic_read(&ipc->rx_msg_count) > 0);

9
drivers/accel/ivpu/ivpu_ipc.h
View File

@ -101,12 +101,13 @@ int ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
int ivpu_ipc_receive(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
struct ivpu_ipc_hdr *ipc_buf, struct vpu_jsm_msg *jsm_msg,
unsigned long timeout_ms);
int ivpu_ipc_send_receive_active(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
enum vpu_ipc_msg_type expected_resp, struct vpu_jsm_msg *resp,
u32 channel, unsigned long timeout_ms);
int ivpu_ipc_send_receive_internal(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
enum vpu_ipc_msg_type expected_resp_type,
struct vpu_jsm_msg *resp, u32 channel, unsigned long timeout_ms);
int ivpu_ipc_send_receive(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
enum vpu_ipc_msg_type expected_resp, struct vpu_jsm_msg *resp,
u32 channel, unsigned long timeout_ms);
int ivpu_ipc_send_and_wait(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
u32 channel, unsigned long timeout_ms);
#endif /* __IVPU_IPC_H__ */

190
drivers/accel/ivpu/ivpu_job.c
View File

@ -18,11 +18,10 @@
#include "ivpu_job.h"
#include "ivpu_jsm_msg.h"
#include "ivpu_pm.h"
#include "ivpu_trace.h"
#include "vpu_boot_api.h"
#define CMD_BUF_IDX 0
#define JOB_ID_JOB_MASK GENMASK(7, 0)
#define JOB_ID_CONTEXT_MASK GENMASK(31, 8)
#define JOB_MAX_BUFFER_COUNT 65535
static void ivpu_cmdq_ring_db(struct ivpu_device *vdev, struct ivpu_cmdq *cmdq)
@ -35,24 +34,20 @@ static int ivpu_preemption_buffers_create(struct ivpu_device *vdev,
{
u64 primary_size = ALIGN(vdev->fw->primary_preempt_buf_size, PAGE_SIZE);
u64 secondary_size = ALIGN(vdev->fw->secondary_preempt_buf_size, PAGE_SIZE);
struct ivpu_addr_range range;
if (vdev->hw->sched_mode != VPU_SCHEDULING_MODE_HW)
if (vdev->fw->sched_mode != VPU_SCHEDULING_MODE_HW ||
ivpu_test_mode & IVPU_TEST_MODE_MIP_DISABLE)
return 0;
range.start = vdev->hw->ranges.user.end - (primary_size * IVPU_NUM_CMDQS_PER_CTX);
range.end = vdev->hw->ranges.user.end;
cmdq->primary_preempt_buf = ivpu_bo_create(vdev, &file_priv->ctx, &range, primary_size,
DRM_IVPU_BO_WC);
cmdq->primary_preempt_buf = ivpu_bo_create(vdev, &file_priv->ctx, &vdev->hw->ranges.user,
primary_size, DRM_IVPU_BO_WC);
if (!cmdq->primary_preempt_buf) {
ivpu_err(vdev, "Failed to create primary preemption buffer\n");
return -ENOMEM;
}
range.start = vdev->hw->ranges.shave.end - (secondary_size * IVPU_NUM_CMDQS_PER_CTX);
range.end = vdev->hw->ranges.shave.end;
cmdq->secondary_preempt_buf = ivpu_bo_create(vdev, &file_priv->ctx, &range, secondary_size,
DRM_IVPU_BO_WC);
cmdq->secondary_preempt_buf = ivpu_bo_create(vdev, &file_priv->ctx, &vdev->hw->ranges.dma,
secondary_size, DRM_IVPU_BO_WC);
if (!cmdq->secondary_preempt_buf) {
ivpu_err(vdev, "Failed to create secondary preemption buffer\n");
goto err_free_primary;
@ -62,24 +57,24 @@ static int ivpu_preemption_buffers_create(struct ivpu_device *vdev,
err_free_primary:
ivpu_bo_free(cmdq->primary_preempt_buf);
cmdq->primary_preempt_buf = NULL;
return -ENOMEM;
}
static void ivpu_preemption_buffers_free(struct ivpu_device *vdev,
struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)
{
if (vdev->hw->sched_mode != VPU_SCHEDULING_MODE_HW)
if (vdev->fw->sched_mode != VPU_SCHEDULING_MODE_HW)
return;
drm_WARN_ON(&vdev->drm, !cmdq->primary_preempt_buf);
drm_WARN_ON(&vdev->drm, !cmdq->secondary_preempt_buf);
ivpu_bo_free(cmdq->primary_preempt_buf);
ivpu_bo_free(cmdq->secondary_preempt_buf);
if (cmdq->primary_preempt_buf)
ivpu_bo_free(cmdq->primary_preempt_buf);
if (cmdq->secondary_preempt_buf)
ivpu_bo_free(cmdq->secondary_preempt_buf);
}
static struct ivpu_cmdq *ivpu_cmdq_alloc(struct ivpu_file_priv *file_priv)
{
struct xa_limit db_xa_limit = {.max = IVPU_MAX_DB, .min = IVPU_MIN_DB};
struct ivpu_device *vdev = file_priv->vdev;
struct ivpu_cmdq *cmdq;
int ret;
@ -88,25 +83,33 @@ static struct ivpu_cmdq *ivpu_cmdq_alloc(struct ivpu_file_priv *file_priv)
if (!cmdq)
return NULL;
ret = xa_alloc(&vdev->db_xa, &cmdq->db_id, NULL, db_xa_limit, GFP_KERNEL);
if (ret) {
ret = xa_alloc_cyclic(&vdev->db_xa, &cmdq->db_id, NULL, vdev->db_limit, &vdev->db_next,
GFP_KERNEL);
if (ret < 0) {
ivpu_err(vdev, "Failed to allocate doorbell id: %d\n", ret);
goto err_free_cmdq;
}
ret = xa_alloc_cyclic(&file_priv->cmdq_xa, &cmdq->id, cmdq, file_priv->cmdq_limit,
&file_priv->cmdq_id_next, GFP_KERNEL);
if (ret < 0) {
ivpu_err(vdev, "Failed to allocate command queue id: %d\n", ret);
goto err_erase_db_xa;
}
cmdq->mem = ivpu_bo_create_global(vdev, SZ_4K, DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE);
if (!cmdq->mem)
goto err_erase_xa;
goto err_erase_cmdq_xa;
ret = ivpu_preemption_buffers_create(vdev, file_priv, cmdq);
if (ret)
goto err_free_cmdq_mem;
ivpu_warn(vdev, "Failed to allocate preemption buffers, preemption limited\n");
return cmdq;
err_free_cmdq_mem:
ivpu_bo_free(cmdq->mem);
err_erase_xa:
err_erase_cmdq_xa:
xa_erase(&file_priv->cmdq_xa, cmdq->id);
err_erase_db_xa:
xa_erase(&vdev->db_xa, cmdq->db_id);
err_free_cmdq:
kfree(cmdq);
@ -130,13 +133,13 @@ static int ivpu_hws_cmdq_init(struct ivpu_file_priv *file_priv, struct ivpu_cmdq
struct ivpu_device *vdev = file_priv->vdev;
int ret;
ret = ivpu_jsm_hws_create_cmdq(vdev, file_priv->ctx.id, file_priv->ctx.id, cmdq->db_id,
ret = ivpu_jsm_hws_create_cmdq(vdev, file_priv->ctx.id, file_priv->ctx.id, cmdq->id,
task_pid_nr(current), engine,
cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem));
if (ret)
return ret;
ret = ivpu_jsm_hws_set_context_sched_properties(vdev, file_priv->ctx.id, cmdq->db_id,
ret = ivpu_jsm_hws_set_context_sched_properties(vdev, file_priv->ctx.id, cmdq->id,
priority);
if (ret)
return ret;
@ -149,21 +152,22 @@ static int ivpu_register_db(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *
struct ivpu_device *vdev = file_priv->vdev;
int ret;
if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW)
ret = ivpu_jsm_hws_register_db(vdev, file_priv->ctx.id, cmdq->db_id, cmdq->db_id,
if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW)
ret = ivpu_jsm_hws_register_db(vdev, file_priv->ctx.id, cmdq->id, cmdq->db_id,
cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem));
else
ret = ivpu_jsm_register_db(vdev, file_priv->ctx.id, cmdq->db_id,
cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem));
if (!ret)
ivpu_dbg(vdev, JOB, "DB %d registered to ctx %d\n", cmdq->db_id, file_priv->ctx.id);
ivpu_dbg(vdev, JOB, "DB %d registered to cmdq %d ctx %d\n",
cmdq->db_id, cmdq->id, file_priv->ctx.id);
return ret;
}
static int
ivpu_cmdq_init(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq, u16 engine, u8 priority)
ivpu_cmdq_init(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq, u8 priority)
{
struct ivpu_device *vdev = file_priv->vdev;
struct vpu_job_queue_header *jobq_header;
@ -179,13 +183,18 @@ ivpu_cmdq_init(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq, u16 eng
cmdq->jobq = (struct vpu_job_queue *)ivpu_bo_vaddr(cmdq->mem);
jobq_header = &cmdq->jobq->header;
jobq_header->engine_idx = engine;
jobq_header->engine_idx = VPU_ENGINE_COMPUTE;
jobq_header->head = 0;
jobq_header->tail = 0;
if (ivpu_test_mode & IVPU_TEST_MODE_TURBO) {
ivpu_dbg(vdev, JOB, "Turbo mode enabled");
jobq_header->flags = VPU_JOB_QUEUE_FLAGS_TURBO_MODE;
}
wmb(); /* Flush WC buffer for jobq->header */
if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) {
ret = ivpu_hws_cmdq_init(file_priv, cmdq, engine, priority);
if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) {
ret = ivpu_hws_cmdq_init(file_priv, cmdq, VPU_ENGINE_COMPUTE, priority);
if (ret)
return ret;
}
@ -211,10 +220,10 @@ static int ivpu_cmdq_fini(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cm
cmdq->db_registered = false;
if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) {
ret = ivpu_jsm_hws_destroy_cmdq(vdev, file_priv->ctx.id, cmdq->db_id);
if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) {
ret = ivpu_jsm_hws_destroy_cmdq(vdev, file_priv->ctx.id, cmdq->id);
if (!ret)
ivpu_dbg(vdev, JOB, "Command queue %d destroyed\n", cmdq->db_id);
ivpu_dbg(vdev, JOB, "Command queue %d destroyed\n", cmdq->id);
}
ret = ivpu_jsm_unregister_db(vdev, cmdq->db_id);
@ -224,55 +233,46 @@ static int ivpu_cmdq_fini(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cm
return 0;
}
static struct ivpu_cmdq *ivpu_cmdq_acquire(struct ivpu_file_priv *file_priv, u16 engine,
u8 priority)
static struct ivpu_cmdq *ivpu_cmdq_acquire(struct ivpu_file_priv *file_priv, u8 priority)
{
int cmdq_idx = IVPU_CMDQ_INDEX(engine, priority);
struct ivpu_cmdq *cmdq = file_priv->cmdq[cmdq_idx];
struct ivpu_cmdq *cmdq;
unsigned long cmdq_id;
int ret;
lockdep_assert_held(&file_priv->lock);
xa_for_each(&file_priv->cmdq_xa, cmdq_id, cmdq)
if (cmdq->priority == priority)
break;
if (!cmdq) {
cmdq = ivpu_cmdq_alloc(file_priv);
if (!cmdq)
return NULL;
file_priv->cmdq[cmdq_idx] = cmdq;
cmdq->priority = priority;
}
ret = ivpu_cmdq_init(file_priv, cmdq, engine, priority);
ret = ivpu_cmdq_init(file_priv, cmdq, priority);
if (ret)
return NULL;
return cmdq;
}
static void ivpu_cmdq_release_locked(struct ivpu_file_priv *file_priv, u16 engine, u8 priority)
void ivpu_cmdq_release_all_locked(struct ivpu_file_priv *file_priv)
{
int cmdq_idx = IVPU_CMDQ_INDEX(engine, priority);
struct ivpu_cmdq *cmdq = file_priv->cmdq[cmdq_idx];
struct ivpu_cmdq *cmdq;
unsigned long cmdq_id;
lockdep_assert_held(&file_priv->lock);
if (cmdq) {
file_priv->cmdq[cmdq_idx] = NULL;
xa_for_each(&file_priv->cmdq_xa, cmdq_id, cmdq) {
xa_erase(&file_priv->cmdq_xa, cmdq_id);
ivpu_cmdq_fini(file_priv, cmdq);
ivpu_cmdq_free(file_priv, cmdq);
}
}
void ivpu_cmdq_release_all_locked(struct ivpu_file_priv *file_priv)
{
u16 engine;
u8 priority;
lockdep_assert_held(&file_priv->lock);
for (engine = 0; engine < IVPU_NUM_ENGINES; engine++)
for (priority = 0; priority < IVPU_NUM_PRIORITIES; priority++)
ivpu_cmdq_release_locked(file_priv, engine, priority);
}
/*
* Mark the doorbell as unregistered
* This function needs to be called when the VPU hardware is restarted
@ -281,20 +281,13 @@ void ivpu_cmdq_release_all_locked(struct ivpu_file_priv *file_priv)
*/
static void ivpu_cmdq_reset(struct ivpu_file_priv *file_priv)
{
u16 engine;
u8 priority;
struct ivpu_cmdq *cmdq;
unsigned long cmdq_id;
mutex_lock(&file_priv->lock);
for (engine = 0; engine < IVPU_NUM_ENGINES; engine++) {
for (priority = 0; priority < IVPU_NUM_PRIORITIES; priority++) {
int cmdq_idx = IVPU_CMDQ_INDEX(engine, priority);
struct ivpu_cmdq *cmdq = file_priv->cmdq[cmdq_idx];
if (cmdq)
cmdq->db_registered = false;
}
}
xa_for_each(&file_priv->cmdq_xa, cmdq_id, cmdq)
cmdq->db_registered = false;
mutex_unlock(&file_priv->lock);
}
@ -314,17 +307,11 @@ void ivpu_cmdq_reset_all_contexts(struct ivpu_device *vdev)
static void ivpu_cmdq_fini_all(struct ivpu_file_priv *file_priv)
{
u16 engine;
u8 priority;
struct ivpu_cmdq *cmdq;
unsigned long cmdq_id;
for (engine = 0; engine < IVPU_NUM_ENGINES; engine++) {
for (priority = 0; priority < IVPU_NUM_PRIORITIES; priority++) {
int cmdq_idx = IVPU_CMDQ_INDEX(engine, priority);
if (file_priv->cmdq[cmdq_idx])
ivpu_cmdq_fini(file_priv, file_priv->cmdq[cmdq_idx]);
}
}
xa_for_each(&file_priv->cmdq_xa, cmdq_id, cmdq)
ivpu_cmdq_fini(file_priv, cmdq);
}
void ivpu_context_abort_locked(struct ivpu_file_priv *file_priv)
@ -335,7 +322,7 @@ void ivpu_context_abort_locked(struct ivpu_file_priv *file_priv)
ivpu_cmdq_fini_all(file_priv);
if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_OS)
if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_OS)
ivpu_jsm_context_release(vdev, file_priv->ctx.id);
}
@ -349,24 +336,29 @@ static int ivpu_cmdq_push_job(struct ivpu_cmdq *cmdq, struct ivpu_job *job)
/* Check if there is space left in job queue */
if (next_entry == header->head) {
ivpu_dbg(vdev, JOB, "Job queue full: ctx %d engine %d db %d head %d tail %d\n",
job->file_priv->ctx.id, job->engine_idx, cmdq->db_id, header->head, tail);
ivpu_dbg(vdev, JOB, "Job queue full: ctx %d cmdq %d db %d head %d tail %d\n",
job->file_priv->ctx.id, cmdq->id, cmdq->db_id, header->head, tail);
return -EBUSY;
}
entry = &cmdq->jobq->job[tail];
entry = &cmdq->jobq->slot[tail].job;
entry->batch_buf_addr = job->cmd_buf_vpu_addr;
entry->job_id = job->job_id;
entry->flags = 0;
if (unlikely(ivpu_test_mode & IVPU_TEST_MODE_NULL_SUBMISSION))
entry->flags = VPU_JOB_FLAGS_NULL_SUBMISSION_MASK;
if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW &&
(unlikely(!(ivpu_test_mode & IVPU_TEST_MODE_PREEMPTION_DISABLE)))) {
entry->primary_preempt_buf_addr = cmdq->primary_preempt_buf->vpu_addr;
entry->primary_preempt_buf_size = ivpu_bo_size(cmdq->primary_preempt_buf);
entry->secondary_preempt_buf_addr = cmdq->secondary_preempt_buf->vpu_addr;
entry->secondary_preempt_buf_size = ivpu_bo_size(cmdq->secondary_preempt_buf);
if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) {
if (cmdq->primary_preempt_buf) {
entry->primary_preempt_buf_addr = cmdq->primary_preempt_buf->vpu_addr;
entry->primary_preempt_buf_size = ivpu_bo_size(cmdq->primary_preempt_buf);
}
if (cmdq->secondary_preempt_buf) {
entry->secondary_preempt_buf_addr = cmdq->secondary_preempt_buf->vpu_addr;
entry->secondary_preempt_buf_size =
ivpu_bo_size(cmdq->secondary_preempt_buf);
}
}
wmb(); /* Ensure that tail is updated after filling entry */
@ -457,6 +449,7 @@ ivpu_job_create(struct ivpu_file_priv *file_priv, u32 engine_idx, u32 bo_count)
job->file_priv = ivpu_file_priv_get(file_priv);
trace_job("create", job);
ivpu_dbg(vdev, JOB, "Job created: ctx %2d engine %d", file_priv->ctx.id, job->engine_idx);
return job;
@ -496,6 +489,7 @@ static int ivpu_job_signal_and_destroy(struct ivpu_device *vdev, u32 job_id, u32
job->bos[CMD_BUF_IDX]->job_status = job_status;
dma_fence_signal(job->done_fence);
trace_job("done", job);
ivpu_dbg(vdev, JOB, "Job complete: id %3u ctx %2d engine %d status 0x%x\n",
job->job_id, job->file_priv->ctx.id, job->engine_idx, job_status);
@ -519,7 +513,6 @@ static int ivpu_job_submit(struct ivpu_job *job, u8 priority)
{
struct ivpu_file_priv *file_priv = job->file_priv;
struct ivpu_device *vdev = job->vdev;
struct xa_limit job_id_range;
struct ivpu_cmdq *cmdq;
bool is_first_job;
int ret;
@ -530,7 +523,7 @@ static int ivpu_job_submit(struct ivpu_job *job, u8 priority)
mutex_lock(&file_priv->lock);
cmdq = ivpu_cmdq_acquire(job->file_priv, job->engine_idx, priority);
cmdq = ivpu_cmdq_acquire(file_priv, priority);
if (!cmdq) {
ivpu_warn_ratelimited(vdev, "Failed to get job queue, ctx %d engine %d prio %d\n",
file_priv->ctx.id, job->engine_idx, priority);
@ -538,13 +531,11 @@ static int ivpu_job_submit(struct ivpu_job *job, u8 priority)
goto err_unlock_file_priv;
}
job_id_range.min = FIELD_PREP(JOB_ID_CONTEXT_MASK, (file_priv->ctx.id - 1));
job_id_range.max = job_id_range.min | JOB_ID_JOB_MASK;
xa_lock(&vdev->submitted_jobs_xa);
is_first_job = xa_empty(&vdev->submitted_jobs_xa);
ret = __xa_alloc(&vdev->submitted_jobs_xa, &job->job_id, job, job_id_range, GFP_KERNEL);
if (ret) {
ret = __xa_alloc_cyclic(&vdev->submitted_jobs_xa, &job->job_id, job, file_priv->job_limit,
&file_priv->job_id_next, GFP_KERNEL);
if (ret < 0) {
ivpu_dbg(vdev, JOB, "Too many active jobs in ctx %d\n",
file_priv->ctx.id);
ret = -EBUSY;
@ -566,6 +557,7 @@ static int ivpu_job_submit(struct ivpu_job *job, u8 priority)
vdev->busy_start_ts = ktime_get();
}
trace_job("submit", job);
ivpu_dbg(vdev, JOB, "Job submitted: id %3u ctx %2d engine %d prio %d addr 0x%llx next %d\n",
job->job_id, file_priv->ctx.id, job->engine_idx, priority,
job->cmd_buf_vpu_addr, cmdq->jobq->header.tail);
@ -673,7 +665,7 @@ int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
int idx, ret;
u8 priority;
if (params->engine > DRM_IVPU_ENGINE_COPY)
if (params->engine != DRM_IVPU_ENGINE_COMPUTE)
return -EINVAL;
if (params->priority > DRM_IVPU_JOB_PRIORITY_REALTIME)

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