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Blackfin arch: cleanup and standardize anomaly.h file format -- no functional changes
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Mike Frysinger
Bryan Wu
parent
c6c4d7bbbb
commit
287050fe13
@ -1,31 +1,9 @@
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/*
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* File: include/asm-blackfin/mach-bf533/anomaly.h
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* Based on:
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* Author:
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* File: include/asm-blackfin/mach-bf533/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Created:
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* Description:
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*
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* Rev:
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*
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* Modified:
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
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||||
* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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* Copyright (C) 2004-2007 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* This file shoule be up to date with:
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@ -43,44 +21,44 @@
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#endif
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/* Issues that are common to 0.5, 0.4, and 0.3 silicon */
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#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \
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#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \
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|| defined(CONFIG_BF_REV_0_3))
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#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
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slot1 and store of a P register in slot 2 is not
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supported */
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* slot1 and store of a P register in slot 2 is not
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* supported */
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#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
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every corresponding match */
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* every corresponding match */
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#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
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Channel DMA stops */
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* Channel DMA stops */
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#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
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registers. */
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* registers. */
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#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
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upper bits*/
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* upper bits*/
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#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
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#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
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syncs */
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* syncs */
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#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
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functional */
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* functional */
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#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
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state */
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* state */
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#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
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#define ANOMALY_05000272 /* Certain data cache write through modes fail for
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VDDint <=0.9V */
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* VDDint <=0.9V */
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#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
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#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
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an edge is detected may clear interrupt */
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* an edge is detected may clear interrupt */
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#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
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DMA system instability */
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* DMA system instability */
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#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
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not restored */
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* not restored */
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#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
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control */
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* control */
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#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
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killed in a particular stage*/
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* killed in a particular stage*/
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#define ANOMALY_05000311 /* Erroneous flag pin operations under specific
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sequences */
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* sequences */
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#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
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registers are interrupted */
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* registers are interrupted */
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#define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer */
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#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On
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* Next System MMR Access */
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@ -91,90 +69,90 @@
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/* These issues only occur on 0.3 or 0.4 BF533 */
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#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
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#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
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updated at the same time. */
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* updated at the same time. */
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#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
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Cache Fill can be corrupted after or during
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Instruction DMA if certain core stalls exist */
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* Cache Fill can be corrupted after or during
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* Instruction DMA if certain core stalls exist */
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#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
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Purpose TX or RX modes */
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* Purpose TX or RX modes */
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#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
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preceding memory read */
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* preceding memory read */
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#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
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inactive channels in certain conditions */
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* inactive channels in certain conditions */
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#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
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situation */
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* situation */
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#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
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#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
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#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
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data*/
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* data*/
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#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
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Differences in certain Conditions */
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* Differences in certain Conditions */
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#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
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#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
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hardware reset */
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* hardware reset */
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#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
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IDLE around a Change of Control causes
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unpredictable results */
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* IDLE around a Change of Control causes
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* unpredictable results */
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#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
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shadow of a conditional branch */
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* shadow of a conditional branch */
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#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
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errors */
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* errors */
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#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
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#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
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interrupt not functional */
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* interrupt not functional */
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#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
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loops may cause the instruction fetch unit to
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malfunction */
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* loops may cause the instruction fetch unit to
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* malfunction */
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#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
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the ICPLB Data registers differ */
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* the ICPLB Data registers differ */
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#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
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#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
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#define ANOMALY_05000262 /* Stores to data cache may be lost */
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#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
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#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
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instruction will cause an infinite stall in the
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second to last instruction in a hardware loop */
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* instruction will cause an infinite stall in the
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* second to last instruction in a hardware loop */
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#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
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SPORT external receive and transmit clocks. */
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* SPORT external receive and transmit clocks. */
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#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
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internal voltage regulator (VDDint) to increase. */
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* internal voltage regulator (VDDint) to increase. */
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#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
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internal voltage regulator (VDDint) to decrease */
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* internal voltage regulator (VDDint) to decrease */
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#endif /* issues only occur on 0.3 or 0.4 BF533 */
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/* These issues are only on 0.4 silicon */
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#if (defined(CONFIG_BF_REV_0_4))
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#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
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#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
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(TDM) */
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* (TDM) */
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#endif /* issues are only on 0.4 silicon */
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/* These issues are only on 0.3 silicon */
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#if defined(CONFIG_BF_REV_0_3)
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#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
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External Frame Syncs */
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* External Frame Syncs */
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#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
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Instruction or Data Fetches, or by Fetches at the
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boundary of reserved memory space */
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* Instruction or Data Fetches, or by Fetches at the
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* boundary of reserved memory space */
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#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
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when polarity setting is changed */
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* when polarity setting is changed */
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#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
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corruption */
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* corruption */
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#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
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fix */
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* fix */
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#define ANOMALY_05000201 /* Receive frame sync not ignored during active
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frames in sport MCM */
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* frames in sport MCM */
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#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
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stopping */
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* stopping */
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#if defined(CONFIG_BF533)
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#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
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allocate cache lines on reads only mode */
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* allocate cache lines on reads only mode */
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#endif /* CONFIG_BF533 */
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#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
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#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
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instructions */
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* instructions */
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#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
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Sync Transmit Mode */
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* Sync Transmit Mode */
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#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
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#endif /* only on 0.3 silicon */
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@ -1,33 +1,9 @@
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/*
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* File: include/asm-blackfin/mach-bf537/anomaly.h
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* Based on:
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* Author:
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* File: include/asm-blackfin/mach-bf537/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Created:
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* Description:
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*
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* Rev:
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*
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* Modified:
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*
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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* Copyright (C) 2004-2007 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* This file shoule be up to date with:
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@ -46,37 +22,37 @@
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#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2))
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#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
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slot1 and store of a P register in slot 2 is not
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supported */
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* slot1 and store of a P register in slot 2 is not
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* supported */
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#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
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Channel DMA stops */
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* Channel DMA stops */
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#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
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registers. */
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* registers. */
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#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
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upper bits*/
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* upper bits*/
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#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
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syncs */
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* syncs */
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#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
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#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
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Changed */
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* Changed */
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#endif
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#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
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SPORT external receive and transmit clocks. */
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* SPORT external receive and transmit clocks. */
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#define ANOMALY_05000272 /* Certain data cache write through modes fail for
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VDDint <=0.9V */
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* VDDint <=0.9V */
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#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
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#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
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an edge is detected may clear interrupt */
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* an edge is detected may clear interrupt */
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#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
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not restored */
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* not restored */
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#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
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control */
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* control */
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#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
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killed in a particular stage*/
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* killed in a particular stage*/
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#define ANOMALY_05000310 /* False hardware errors caused by fetches at the
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* boundary of reserved memory */
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#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
|
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registers are interrupted */
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* registers are interrupted */
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#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */
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#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not
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* received properly */
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@ -84,41 +60,41 @@
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#if defined(CONFIG_BF_REV_0_2)
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#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
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IDLE around a Change of Control causes
|
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unpredictable results */
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* IDLE around a Change of Control causes
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* unpredictable results */
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#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
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(TDM) */
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* (TDM) */
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#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
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#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
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#endif
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#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
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#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
|
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interrupt not functional */
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* interrupt not functional */
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#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
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#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
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#endif
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#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
|
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loops may cause the instruction fetch unit to
|
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malfunction */
|
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* loops may cause the instruction fetch unit to
|
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* malfunction */
|
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#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
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the ICPLB Data registers differ */
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* the ICPLB Data registers differ */
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#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
|
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#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
|
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#define ANOMALY_05000262 /* Stores to data cache may be lost */
|
||||
#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
|
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#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
|
||||
instruction will cause an infinite stall in the
|
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second to last instruction in a hardware loop */
|
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* instruction will cause an infinite stall in the
|
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* second to last instruction in a hardware loop */
|
||||
#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
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and non-zero DEB_TRAFFIC_PERIOD value */
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* and non-zero DEB_TRAFFIC_PERIOD value */
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#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
|
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internal voltage regulator (VDDint) to decrease */
|
||||
* internal voltage regulator (VDDint) to decrease */
|
||||
#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
|
||||
an edge is detected may clear interrupt */
|
||||
* an edge is detected may clear interrupt */
|
||||
#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
|
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DMA system instability */
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* DMA system instability */
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#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
|
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Atmel Dataflash devices */
|
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* Atmel Dataflash devices */
|
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#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context
|
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* is not restored */
|
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#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
|
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@ -134,6 +110,6 @@
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* mode */
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#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with
|
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* status No Carrier */
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#endif /* CONFIG_BF_REV_0_2 */
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#endif /* CONFIG_BF_REV_0_2 */
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#endif /* _MACH_ANOMALY_H_ */
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@ -1,74 +1,51 @@
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/*
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* File: include/asm-blackfin/mach-bf548/anomaly.h
|
||||
* Based on:
|
||||
* Author:
|
||||
* File: include/asm-blackfin/mach-bf548/anomaly.h
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
* Copyright (C) 2004-2007 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
#define _MACH_ANOMALY_H_
|
||||
|
||||
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
|
||||
slot1 and store of a P register in slot 2 is not
|
||||
supported */
|
||||
* slot1 and store of a P register in slot 2 is not
|
||||
* supported */
|
||||
#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
|
||||
Channel DMA stops */
|
||||
* Channel DMA stops */
|
||||
#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
|
||||
registers. */
|
||||
* registers. */
|
||||
#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the
|
||||
Shadow of a Conditional Branch */
|
||||
* Shadow of a Conditional Branch */
|
||||
#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
|
||||
interrupt not functional */
|
||||
* interrupt not functional */
|
||||
#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
|
||||
SPORT external receive and transmit clocks. */
|
||||
* SPORT external receive and transmit clocks. */
|
||||
#define ANOMALY_05000272 /* Certain data cache write through modes fail for
|
||||
VDDint <=0.9V */
|
||||
* VDDint <=0.9V */
|
||||
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
|
||||
not restored */
|
||||
* not restored */
|
||||
#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the
|
||||
Boundary of Reserved Memory */
|
||||
* Boundary of Reserved Memory */
|
||||
#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and
|
||||
LC Registers Are Interrupted */
|
||||
* LC Registers Are Interrupted */
|
||||
#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to
|
||||
the USB FIFO Simultaneously */
|
||||
* the USB FIFO Simultaneously */
|
||||
#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write()
|
||||
function */
|
||||
* function */
|
||||
#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional
|
||||
*/
|
||||
* */
|
||||
#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM
|
||||
Skew */
|
||||
* Skew */
|
||||
#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */
|
||||
#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration
|
||||
of Host DMA Port */
|
||||
* of Host DMA Port */
|
||||
#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent
|
||||
Allowed Configuration on Host DMA Port */
|
||||
* Allowed Configuration on Host DMA Port */
|
||||
#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
|
||||
|
||||
#endif /* _MACH_ANOMALY_H_ */
|
||||
|
||||
@ -1,36 +1,13 @@
|
||||
|
||||
/*
|
||||
* File: include/asm-blackfin/mach-bf561/anomaly.h
|
||||
* Based on:
|
||||
* Author:
|
||||
* File: include/asm-blackfin/mach-bf561/anomaly.h
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Rev:
|
||||
*
|
||||
* Modified:
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING.
|
||||
* If not, write to the Free Software Foundation,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
* Copyright (C) 2004-2007 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision L, 10Aug2006; ADSP-BF561 Silicon Anomaly List
|
||||
* - Revision L, Aug 10, 2006; ADSP-BF561 Silicon Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
@ -42,142 +19,142 @@
|
||||
#endif
|
||||
|
||||
/* Issues that are common to 0.5 and 0.3 silicon */
|
||||
#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3))
|
||||
#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3))
|
||||
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
|
||||
slot1 and store of a P register in slot 2 is not
|
||||
supported */
|
||||
* slot1 and store of a P register in slot 2 is not
|
||||
* supported */
|
||||
#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
|
||||
updated at the same time. */
|
||||
* updated at the same time. */
|
||||
#define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned
|
||||
memory locations */
|
||||
* memory locations */
|
||||
#define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR
|
||||
registers */
|
||||
* registers */
|
||||
#define ANOMALY_05000127 /* Signbits instruction not functional under certain
|
||||
conditions */
|
||||
* conditions */
|
||||
#define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */
|
||||
#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
|
||||
upper bits */
|
||||
* upper bits */
|
||||
#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
|
||||
#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
|
||||
syncs */
|
||||
* syncs */
|
||||
#define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz
|
||||
and higher devices */
|
||||
* and higher devices */
|
||||
#define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */
|
||||
#define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */
|
||||
#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
|
||||
functional */
|
||||
* functional */
|
||||
#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
|
||||
shadow of a conditional branch */
|
||||
* shadow of a conditional branch */
|
||||
#define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop
|
||||
may cause bad instruction fetches */
|
||||
* may cause bad instruction fetches */
|
||||
#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
|
||||
external SPORT TX and RX clocks */
|
||||
* external SPORT TX and RX clocks */
|
||||
#define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */
|
||||
#define ANOMALY_05000269 /* High I/O activity causes output voltage of internal
|
||||
voltage regulator (VDDint) to increase */
|
||||
* voltage regulator (VDDint) to increase */
|
||||
#define ANOMALY_05000270 /* High I/O activity causes output voltage of internal
|
||||
voltage regulator (VDDint) to decrease */
|
||||
* voltage regulator (VDDint) to decrease */
|
||||
#define ANOMALY_05000272 /* Certain data cache write through modes fail for
|
||||
VDDint <=0.9V */
|
||||
* VDDint <=0.9V */
|
||||
#define ANOMALY_05000274 /* Data cache write back to external synchronous memory
|
||||
may be lost */
|
||||
* may be lost */
|
||||
#define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */
|
||||
#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
|
||||
registers are interrupted */
|
||||
* registers are interrupted */
|
||||
|
||||
#endif /* (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */
|
||||
|
||||
#if (defined(CONFIG_BF_REV_0_5))
|
||||
#if (defined(CONFIG_BF_REV_0_5))
|
||||
#define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT
|
||||
mode with external clock */
|
||||
* mode with external clock */
|
||||
#define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to
|
||||
using IMDMA */
|
||||
* using IMDMA */
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_BF_REV_0_3))
|
||||
#if (defined(CONFIG_BF_REV_0_3))
|
||||
#define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input)
|
||||
Mode with 0 Frame Syncs */
|
||||
* Mode with 0 Frame Syncs */
|
||||
#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
|
||||
#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through
|
||||
cache data writes */
|
||||
* cache data writes */
|
||||
#define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */
|
||||
#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
|
||||
#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
|
||||
#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
|
||||
accumulator saturation */
|
||||
* accumulator saturation */
|
||||
#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
|
||||
Purpose TX or RX modes */
|
||||
* Purpose TX or RX modes */
|
||||
#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
|
||||
registers */
|
||||
* registers */
|
||||
#define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with
|
||||
External Frame Syncs */
|
||||
* External Frame Syncs */
|
||||
#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
|
||||
#define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits
|
||||
(not a meaningful mode) */
|
||||
* (not a meaningful mode) */
|
||||
#define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer
|
||||
Placement in Memory */
|
||||
* Placement in Memory */
|
||||
#define ANOMALY_05000189 /* False Protection Exception */
|
||||
#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
|
||||
when polarity setting is changed */
|
||||
* when polarity setting is changed */
|
||||
#define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data
|
||||
corruption */
|
||||
* corruption */
|
||||
#define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding
|
||||
memory read */
|
||||
* memory read */
|
||||
#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
|
||||
fix */
|
||||
* fix */
|
||||
#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
|
||||
inactive channels in certain conditions */
|
||||
* inactive channels in certain conditions */
|
||||
#define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG
|
||||
situation */
|
||||
* situation */
|
||||
#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
|
||||
allocate cache lines on reads only mode */
|
||||
* allocate cache lines on reads only mode */
|
||||
#define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA
|
||||
stopping */
|
||||
* stopping */
|
||||
#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
|
||||
#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
|
||||
instructions */
|
||||
* instructions */
|
||||
#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
|
||||
#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
|
||||
state */
|
||||
* state */
|
||||
#define ANOMALY_05000220 /* Data Corruption with Cached External Memory and
|
||||
Non-Cached On-Chip L2 Memory */
|
||||
* Non-Cached On-Chip L2 Memory */
|
||||
#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
|
||||
#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
|
||||
data */
|
||||
* data */
|
||||
#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
|
||||
Differences in certain Conditions */
|
||||
* Differences in certain Conditions */
|
||||
#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
|
||||
#define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in
|
||||
multichannel mode */
|
||||
* multichannel mode */
|
||||
#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
|
||||
hardware reset */
|
||||
* hardware reset */
|
||||
#define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of
|
||||
Control causes failures */
|
||||
* Control causes failures */
|
||||
#define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */
|
||||
#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
|
||||
(TDM) mode in certain conditions */
|
||||
* (TDM) mode in certain conditions */
|
||||
#define ANOMALY_05000251 /* Exception not generated for MMR accesses in
|
||||
reserved region */
|
||||
* reserved region */
|
||||
#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
|
||||
#define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12
|
||||
of the ICPLB Data registers differ */
|
||||
* of the ICPLB Data registers differ */
|
||||
#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
|
||||
#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
|
||||
#define ANOMALY_05000262 /* Stores to data cache may be lost */
|
||||
#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB
|
||||
exception */
|
||||
* exception */
|
||||
#define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second
|
||||
to last instruction in hardware loop */
|
||||
* to last instruction in hardware loop */
|
||||
#define ANOMALY_05000276 /* Timing requirements change for External Frame
|
||||
Sync PPI Modes with non-zero PPI_DELAY */
|
||||
* Sync PPI Modes with non-zero PPI_DELAY */
|
||||
#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
|
||||
DMA system instability */
|
||||
* DMA system instability */
|
||||
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
|
||||
not restored */
|
||||
* not restored */
|
||||
#define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed
|
||||
in a particular stage */
|
||||
* in a particular stage */
|
||||
#define ANOMALY_05000287 /* A read will receive incorrect data under certain
|
||||
conditions */
|
||||
* conditions */
|
||||
#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user