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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

Browse Source 
Conflicts:
	include/linux/serial_sci.h

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt 2010-07-05 15:46:08 +09:00
commit 285eba57db
1387 changed files with 87476 additions and 10992 deletions
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1
.gitignore vendored
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@ -28,6 +28,7 @@ modules.builtin
*.gz
*.bz2
*.lzma
*.lzo
*.patch
*.gcno

7
Documentation/.gitignore vendored Normal file
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@ -0,0 +1,7 @@
filesystems/dnotify_test
laptops/dslm
timers/hpet_example
vm/hugepage-mmap
vm/hugepage-shm
vm/map_hugetlb

40
Documentation/ABI/testing/sysfs-bus-pci
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@ -133,46 +133,6 @@ Description:
The symbolic link points to the PCI device sysfs entry of the
Physical Function this device associates with.
What: /sys/bus/pci/slots/...
Date: April 2005 (possibly older)
KernelVersion: 2.6.12 (possibly older)
Contact: linux-pci@vger.kernel.org
Description:
When the appropriate driver is loaded, it will create a
directory per claimed physical PCI slot in
/sys/bus/pci/slots/. The names of these directories are
specific to the driver, which in turn, are specific to the
platform, but in general, should match the label on the
machine's physical chassis.
The drivers that can create slot directories include the
PCI hotplug drivers, and as of 2.6.27, the pci_slot driver.
The slot directories contain, at a minimum, a file named
'address' which contains the PCI bus:device:function tuple.
Other files may appear as well, but are specific to the
driver.
What: /sys/bus/pci/slots/.../function[0-7]
Date: March 2010
KernelVersion: 2.6.35
Contact: linux-pci@vger.kernel.org
Description:
If PCI slot directories (as described above) are created,
and the physical slot is actually populated with a device,
symbolic links in the slot directory pointing to the
device's PCI functions are created as well.
What: /sys/bus/pci/devices/.../slot
Date: March 2010
KernelVersion: 2.6.35
Contact: linux-pci@vger.kernel.org
Description:
If PCI slot directories (as described above) are created,
a symbolic link pointing to the slot directory will be
created as well.
What: /sys/bus/pci/slots/.../module
Date: June 2009
Contact: linux-pci@vger.kernel.org

12
Documentation/DocBook/drm.tmpl
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@ -389,7 +389,7 @@
</para>
<para>
If your driver supports memory management (it should!), you'll
need to set that up at load time as well. How you intialize
need to set that up at load time as well. How you initialize
it depends on which memory manager you're using, TTM or GEM.
</para>
<sect3>
@ -399,7 +399,7 @@
aperture space for graphics devices. TTM supports both UMA devices
and devices with dedicated video RAM (VRAM), i.e. most discrete
graphics devices. If your device has dedicated RAM, supporting
TTM is desireable. TTM also integrates tightly with your
TTM is desirable. TTM also integrates tightly with your
driver specific buffer execution function. See the radeon
driver for examples.
</para>
@ -443,7 +443,7 @@
likely eventually calling ttm_bo_global_init and
ttm_bo_global_release, respectively. Also like the previous
object, ttm_global_item_ref is used to create an initial reference
count for the TTM, which will call your initalization function.
count for the TTM, which will call your initialization function.
</para>
</sect3>
<sect3>
@ -557,7 +557,7 @@ void intel_crt_init(struct drm_device *dev)
CRT connector and encoder combination is created. A device
specific i2c bus is also created, for fetching EDID data and
performing monitor detection. Once the process is complete,
the new connector is regsitered with sysfs, to make its
the new connector is registered with sysfs, to make its
properties available to applications.
</para>
<sect4>
@ -581,12 +581,12 @@ void intel_crt_init(struct drm_device *dev)
<para>
For each encoder, CRTC and connector, several functions must
be provided, depending on the object type. Encoder objects
need should provide a DPMS (basically on/off) function, mode fixup
need to provide a DPMS (basically on/off) function, mode fixup
(for converting requested modes into native hardware timings),
and prepare, set and commit functions for use by the core DRM
helper functions. Connector helpers need to provide mode fetch and
validity functions as well as an encoder matching function for
returing an ideal encoder for a given connector. The core
returning an ideal encoder for a given connector. The core
connector functions include a DPMS callback, (deprecated)
save/restore routines, detection, mode probing, property handling,
and cleanup functions.

2
Documentation/DocBook/v4l/v4l2.xml
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@ -58,7 +58,7 @@ MPEG stream embedded, sliced VBI data format in this specification.
</contrib>
<affiliation>
<address>
<email>awalls@radix.net</email>
<email>awalls@md.metrocast.net</email>
</address>
</affiliation>
</author>

6
Documentation/DocBook/v4l/vidioc-query-dv-preset.xml
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@ -53,8 +53,10 @@ input</refpurpose>
automatically, similar to sensing the video standard. To do so, applications
call <constant> VIDIOC_QUERY_DV_PRESET</constant> with a pointer to a
&v4l2-dv-preset; type. Once the hardware detects a preset, that preset is
returned in the preset field of &v4l2-dv-preset;. When detection is not
possible or fails, the value V4L2_DV_INVALID is returned.</para>
returned in the preset field of &v4l2-dv-preset;. If the preset could not be
detected because there was no signal, or the signal was unreliable, or the
signal did not map to a supported preset, then the value V4L2_DV_INVALID is
returned.</para>
</refsect1>
<refsect1>

152
Documentation/edac.txt
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@ -6,6 +6,8 @@ Written by Doug Thompson <dougthompson@xmission.com>
7 Dec 2005
17 Jul 2007 Updated
(c) Mauro Carvalho Chehab <mchehab@redhat.com>
05 Aug 2009 Nehalem interface
EDAC is maintained and written by:
@ -717,3 +719,153 @@ unique drivers for their hardware systems.
The 'test_device_edac' sample driver is located at the
bluesmoke.sourceforge.net project site for EDAC.
=======================================================================
NEHALEM USAGE OF EDAC APIs
This chapter documents some EXPERIMENTAL mappings for EDAC API to handle
Nehalem EDAC driver. They will likely be changed on future versions
of the driver.
Due to the way Nehalem exports Memory Controller data, some adjustments
were done at i7core_edac driver. This chapter will cover those differences
1) On Nehalem, there are one Memory Controller per Quick Patch Interconnect
(QPI). At the driver, the term "socket" means one QPI. This is
associated with a physical CPU socket.
Each MC have 3 physical read channels, 3 physical write channels and
3 logic channels. The driver currenty sees it as just 3 channels.
Each channel can have up to 3 DIMMs.
The minimum known unity is DIMMs. There are no information about csrows.
As EDAC API maps the minimum unity is csrows, the driver sequencially
maps channel/dimm into different csrows.
For example, suposing the following layout:
Ch0 phy rd0, wr0 (0x063f4031): 2 ranks, UDIMMs
dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
dimm 1 1024 Mb offset: 4, bank: 8, rank: 1, row: 0x4000, col: 0x400
Ch1 phy rd1, wr1 (0x063f4031): 2 ranks, UDIMMs
dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
Ch2 phy rd3, wr3 (0x063f4031): 2 ranks, UDIMMs
dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
The driver will map it as:
csrow0: channel 0, dimm0
csrow1: channel 0, dimm1
csrow2: channel 1, dimm0
csrow3: channel 2, dimm0
exports one
DIMM per csrow.
Each QPI is exported as a different memory controller.
2) Nehalem MC has the hability to generate errors. The driver implements this
functionality via some error injection nodes:
For injecting a memory error, there are some sysfs nodes, under
/sys/devices/system/edac/mc/mc?/:
inject_addrmatch/*:
Controls the error injection mask register. It is possible to specify
several characteristics of the address to match an error code:
dimm = the affected dimm. Numbers are relative to a channel;
rank = the memory rank;
channel = the channel that will generate an error;
bank = the affected bank;
page = the page address;
column (or col) = the address column.
each of the above values can be set to "any" to match any valid value.
At driver init, all values are set to any.
For example, to generate an error at rank 1 of dimm 2, for any channel,
any bank, any page, any column:
echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm
echo 1 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank
To return to the default behaviour of matching any, you can do:
echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm
echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank
inject_eccmask:
specifies what bits will have troubles,
inject_section:
specifies what ECC cache section will get the error:
3 for both
2 for the highest
1 for the lowest
inject_type:
specifies the type of error, being a combination of the following bits:
bit 0 - repeat
bit 1 - ecc
bit 2 - parity
inject_enable starts the error generation when something different
than 0 is written.
All inject vars can be read. root permission is needed for write.
Datasheet states that the error will only be generated after a write on an
address that matches inject_addrmatch. It seems, however, that reading will
also produce an error.
For example, the following code will generate an error for any write access
at socket 0, on any DIMM/address on channel 2:
echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/channel
echo 2 >/sys/devices/system/edac/mc/mc0/inject_type
echo 64 >/sys/devices/system/edac/mc/mc0/inject_eccmask
echo 3 >/sys/devices/system/edac/mc/mc0/inject_section
echo 1 >/sys/devices/system/edac/mc/mc0/inject_enable
dd if=/dev/mem of=/dev/null seek=16k bs=4k count=1 >& /dev/null
For socket 1, it is needed to replace "mc0" by "mc1" at the above
commands.
The generated error message will look like:
EDAC MC0: UE row 0, channel-a= 0 channel-b= 0 labels "-": NON_FATAL (addr = 0x0075b980, socket=0, Dimm=0, Channel=2, syndrome=0x00000040, count=1, Err=8c0000400001009f:4000080482 (read error: read ECC error))
3) Nehalem specific Corrected Error memory counters
Nehalem have some registers to count memory errors. The driver uses those
registers to report Corrected Errors on devices with Registered Dimms.
However, those counters don't work with Unregistered Dimms. As the chipset
offers some counters that also work with UDIMMS (but with a worse level of
granularity than the default ones), the driver exposes those registers for
UDIMM memories.
They can be read by looking at the contents of all_channel_counts/
$ for i in /sys/devices/system/edac/mc/mc0/all_channel_counts/*; do echo $i; cat $i; done
/sys/devices/system/edac/mc/mc0/all_channel_counts/udimm0
0
/sys/devices/system/edac/mc/mc0/all_channel_counts/udimm1
0
/sys/devices/system/edac/mc/mc0/all_channel_counts/udimm2
0
What happens here is that errors on different csrows, but at the same
dimm number will increment the same counter.
So, in this memory mapping:
csrow0: channel 0, dimm0
csrow1: channel 0, dimm1
csrow2: channel 1, dimm0
csrow3: channel 2, dimm0
The hardware will increment udimm0 for an error at the first dimm at either
csrow0, csrow2 or csrow3;
The hardware will increment udimm1 for an error at the second dimm at either
csrow0, csrow2 or csrow3;
The hardware will increment udimm2 for an error at the third dimm at either
csrow0, csrow2 or csrow3;
4) Standard error counters
The standard error counters are generated when an mcelog error is received
by the driver. Since, with udimm, this is counted by software, it is
possible that some errors could be lost. With rdimm's, they displays the
contents of the registers

9
Documentation/feature-removal-schedule.txt
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@ -578,15 +578,6 @@ Who: Avi Kivity <avi@redhat.com>
----------------------------
What: "acpi=ht" boot option
When: 2.6.35
Why: Useful in 2003, implementation is a hack.
Generally invoked by accident today.
Seen as doing more harm than good.
Who: Len Brown <len.brown@intel.com>
----------------------------
What: iwlwifi 50XX module parameters
When: 2.6.40
Why: The "..50" modules parameters were used to configure 5000 series and

5
Documentation/filesystems/xfs-delayed-logging-design.txt
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@ -794,11 +794,6 @@ designed.
Roadmap:
2.6.35 Inclusion in mainline as an experimental mount option
=> approximately 2-3 months to merge window
=> needs to be in xfs-dev tree in 4-6 weeks
=> code is nearing readiness for review
2.6.37 Remove experimental tag from mount option
=> should be roughly 6 months after initial merge
=> enough time to:

4
Documentation/i2c/busses/i2c-ali1535
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@ -6,12 +6,12 @@ Supported adapters:
http://www.ali.com.tw/eng/support/datasheet_request.php
Authors:
Frodo Looijaard <frodol@dds.nl>,
Frodo Looijaard <frodol@dds.nl>,
Philip Edelbrock <phil@netroedge.com>,
Mark D. Studebaker <mdsxyz123@yahoo.com>,
Dan Eaton <dan.eaton@rocketlogix.com>,
Stephen Rousset<stephen.rousset@rocketlogix.com>
Description
-----------

2
Documentation/i2c/busses/i2c-ali1563
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@ -18,7 +18,7 @@ For an overview of these chips see http://www.acerlabs.com
The M1563 southbridge is deceptively similar to the M1533, with a few
notable exceptions. One of those happens to be the fact they upgraded the
i2c core to be SMBus 2.0 compliant, and happens to be almost identical to
the i2c controller found in the Intel 801 south bridges.
the i2c controller found in the Intel 801 south bridges.
Features
--------

16
Documentation/i2c/busses/i2c-ali15x3
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@ -6,8 +6,8 @@ Supported adapters:
http://www.ali.com.tw/eng/support/datasheet_request.php
Authors:
Frodo Looijaard <frodol@dds.nl>,
Philip Edelbrock <phil@netroedge.com>,
Frodo Looijaard <frodol@dds.nl>,
Philip Edelbrock <phil@netroedge.com>,
Mark D. Studebaker <mdsxyz123@yahoo.com>
Module Parameters
@ -40,10 +40,10 @@ M1541 and M1543C South Bridges.
The M1543C is a South bridge for desktop systems.
The M1541 is a South bridge for portable systems.
They are part of the following ALI chipsets:
* "Aladdin Pro 2" includes the M1621 Slot 1 North bridge with AGP and
* "Aladdin Pro 2" includes the M1621 Slot 1 North bridge with AGP and
100MHz CPU Front Side bus
* "Aladdin V" includes the M1541 Socket 7 North bridge with AGP and 100MHz
* "Aladdin V" includes the M1541 Socket 7 North bridge with AGP and 100MHz
CPU Front Side bus
Some Aladdin V motherboards:
Asus P5A
@ -77,7 +77,7 @@ output of lspci will show something similar to the following:
** then run lspci.
** If you see the 1533 and 5229 devices but NOT the 7101 device,
** then you must enable ACPI, the PMU, SMB, or something similar
** in the BIOS.
** in the BIOS.
** The driver won't work if it can't find the M7101 device.
The SMB controller is part of the M7101 device, which is an ACPI-compliant
@ -87,8 +87,8 @@ The whole M7101 device has to be enabled for the SMB to work. You can't
just enable the SMB alone. The SMB and the ACPI have separate I/O spaces.
We make sure that the SMB is enabled. We leave the ACPI alone.
Features
--------
Features
--------
This driver controls the SMB Host only. The SMB Slave
controller on the M15X3 is not enabled. This driver does not use

14
Documentation/i2c/busses/i2c-pca-isa
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@ -1,10 +1,10 @@
Kernel driver i2c-pca-isa
Supported adapters:
This driver supports ISA boards using the Philips PCA 9564
Parallel bus to I2C bus controller
This driver supports ISA boards using the Philips PCA 9564
Parallel bus to I2C bus controller
Author: Ian Campbell <icampbell@arcom.com>, Arcom Control Systems
Author: Ian Campbell <icampbell@arcom.com>, Arcom Control Systems
Module Parameters
-----------------
@ -12,12 +12,12 @@ Module Parameters
* base int
I/O base address
* irq int
IRQ interrupt
* clock int
IRQ interrupt
* clock int
Clock rate as described in table 1 of PCA9564 datasheet
Description
-----------
This driver supports ISA boards using the Philips PCA 9564
Parallel bus to I2C bus controller
This driver supports ISA boards using the Philips PCA 9564
Parallel bus to I2C bus controller

56
Documentation/i2c/busses/i2c-sis5595
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@ -1,41 +1,41 @@
Kernel driver i2c-sis5595
Authors:
Authors:
Frodo Looijaard <frodol@dds.nl>,
Mark D. Studebaker <mdsxyz123@yahoo.com>,
Philip Edelbrock <phil@netroedge.com>
Philip Edelbrock <phil@netroedge.com>
Supported adapters:
* Silicon Integrated Systems Corp. SiS5595 Southbridge
Datasheet: Publicly available at the Silicon Integrated Systems Corp. site.
Note: all have mfr. ID 0x1039.
Note: all have mfr. ID 0x1039.
SUPPORTED PCI ID
5595 0008
Note: these chips contain a 0008 device which is incompatible with the
5595. We recognize these by the presence of the listed
"blacklist" PCI ID and refuse to load.
NOT SUPPORTED PCI ID BLACKLIST PCI ID
540 0008 0540
550 0008 0550
5513 0008 5511
5581 0008 5597
5582 0008 5597
5597 0008 5597
5598 0008 5597/5598
630 0008 0630
645 0008 0645
646 0008 0646
648 0008 0648
650 0008 0650
651 0008 0651
730 0008 0730
735 0008 0735
745 0008 0745
746 0008 0746
SUPPORTED PCI ID
5595 0008
Note: these chips contain a 0008 device which is incompatible with the
5595. We recognize these by the presence of the listed
"blacklist" PCI ID and refuse to load.
NOT SUPPORTED PCI ID BLACKLIST PCI ID
540 0008 0540
550 0008 0550
5513 0008 5511
5581 0008 5597
5582 0008 5597
5597 0008 5597
5598 0008 5597/5598
630 0008 0630
645 0008 0645
646 0008 0646
648 0008 0648
650 0008 0650
651 0008 0651
730 0008 0730
735 0008 0735
745 0008 0745
746 0008 0746
Module Parameters
-----------------

8
Documentation/i2c/busses/i2c-sis630
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@ -14,9 +14,9 @@ Module Parameters
* force = [1|0] Forcibly enable the SIS630. DANGEROUS!
This can be interesting for chipsets not named
above to check if it works for you chipset, but DANGEROUS!
* high_clock = [1|0] Forcibly set Host Master Clock to 56KHz (default,
what your BIOS use). DANGEROUS! This should be a bit
* high_clock = [1|0] Forcibly set Host Master Clock to 56KHz (default,
what your BIOS use). DANGEROUS! This should be a bit
faster, but freeze some systems (i.e. my Laptop).
@ -44,6 +44,6 @@ Philip Edelbrock <phil@netroedge.com>
- testing SiS730 support
Mark M. Hoffman <mhoffman@lightlink.com>
- bug fixes
To anyone else which I forgot here ;), thanks!

6
Documentation/i2c/ten-bit-addresses
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@ -1,17 +1,17 @@
The I2C protocol knows about two kinds of device addresses: normal 7 bit
The I2C protocol knows about two kinds of device addresses: normal 7 bit
addresses, and an extended set of 10 bit addresses. The sets of addresses
do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
address 0x10 (though a single device could respond to both of them). You
select a 10 bit address by adding an extra byte after the address
byte:
S Addr7 Rd/Wr ....
S Addr7 Rd/Wr ....
becomes
S 11110 Addr10 Rd/Wr
S is the start bit, Rd/Wr the read/write bit, and if you count the number
of bits, you will see the there are 8 after the S bit for 7 bit addresses,
and 16 after the S bit for 10 bit addresses.
WARNING! The current 10 bit address support is EXPERIMENTAL. There are
WARNING! The current 10 bit address support is EXPERIMENTAL. There are
several places in the code that will cause SEVERE PROBLEMS with 10 bit
addresses, even though there is some basic handling and hooks. Also,
almost no supported adapter handles the 10 bit addresses correctly.

6
Documentation/kbuild/kbuild.txt
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@ -65,7 +65,7 @@ CROSS_COMPILE
Specify an optional fixed part of the binutils filename.
CROSS_COMPILE can be a part of the filename or the full path.
CROSS_COMPILE is also used for ccache is some setups.
CROSS_COMPILE is also used for ccache in some setups.
CF
--------------------------------------------------
@ -162,3 +162,7 @@ For tags/TAGS/cscope targets, you can specify more than one arch
to be included in the databases, separated by blank space. E.g.:
$ make ALLSOURCE_ARCHS="x86 mips arm" tags
To get all available archs you can also specify all. E.g.:
$ make ALLSOURCE_ARCHS=all tags

4
Documentation/kernel-parameters.txt
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@ -2048,7 +2048,9 @@ and is between 256 and 4096 characters. It is defined in the file
WARNING: Forcing ASPM on may cause system lockups.
pcie_pme= [PCIE,PM] Native PCIe PME signaling options:
off Do not use native PCIe PME signaling.
Format: {auto|force}[,nomsi]
auto Use native PCIe PME signaling if the BIOS allows the
kernel to control PCIe config registers of root ports.
force Use native PCIe PME signaling even if the BIOS refuses
to allow the kernel to control the relevant PCIe config
registers.

4
Documentation/mutex-design.txt
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@ -66,14 +66,14 @@ of advantages of mutexes:
c0377ccb <mutex_lock>:
c0377ccb: f0 ff 08 lock decl (%eax)
c0377cce: 78 0e js c0377cde <.text.lock.mutex>
c0377cce: 78 0e js c0377cde <.text..lock.mutex>
c0377cd0: c3 ret
the unlocking fastpath is equally tight:
c0377cd1 <mutex_unlock>:
c0377cd1: f0 ff 00 lock incl (%eax)
c0377cd4: 7e 0f jle c0377ce5 <.text.lock.mutex+0x7>
c0377cd4: 7e 0f jle c0377ce5 <.text..lock.mutex+0x7>
c0377cd6: c3 ret
- 'struct mutex' semantics are well-defined and are enforced if

2
Documentation/timers/Makefile
View File

@ -2,7 +2,7 @@
obj- := dummy.o
# List of programs to build
hostprogs-y := hpet_example
hostprogs-$(CONFIG_X86) := hpet_example
# Tell kbuild to always build the programs
always := $(hostprogs-y)

5
Documentation/video4linux/CARDLIST.saa7134
View File

@ -176,5 +176,6 @@
175 -> Leadtek Winfast DTV1000S [107d:6655]
176 -> Beholder BeholdTV 505 RDS [0000:5051]
177 -> Hawell HW-404M7
179 -> Beholder BeholdTV H7 [5ace:7190]
180 -> Beholder BeholdTV A7 [5ace:7090]
178 -> Beholder BeholdTV H7 [5ace:7190]
179 -> Beholder BeholdTV A7 [5ace:7090]
180 -> Avermedia M733A [1461:4155,1461:4255]

1
Documentation/video4linux/gspca.txt
View File

@ -290,6 +290,7 @@ sonixb 0c45:602e Genius VideoCam Messenger
sonixj 0c45:6040 Speed NVC 350K
sonixj 0c45:607c Sonix sn9c102p Hv7131R
sonixj 0c45:60c0 Sangha Sn535
sonixj 0c45:60ce USB-PC-Camera-168 (TALK-5067)
sonixj 0c45:60ec SN9C105+MO4000
sonixj 0c45:60fb Surfer NoName
sonixj 0c45:60fc LG-LIC300

5
Documentation/watchdog/watchdog-parameters.txt
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@ -125,6 +125,11 @@ ibmasr:
nowayout: Watchdog cannot be stopped once started
(default=kernel config parameter)
-------------------------------------------------
imx2_wdt:
timeout: Watchdog timeout in seconds (default 60 s)
nowayout: Watchdog cannot be stopped once started
(default=kernel config parameter)
-------------------------------------------------
indydog:
nowayout: Watchdog cannot be stopped once started
(default=kernel config parameter)

69
MAINTAINERS
View File

@ -896,11 +896,13 @@ S: Maintained
ARM/SAMSUNG ARM ARCHITECTURES
M: Ben Dooks <ben-linux@fluff.org>
M: Kukjin Kim <kgene.kim@samsung.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.fluff.org/ben/linux/
S: Maintained
F: arch/arm/plat-s3c/
F: arch/arm/plat-samsung/
F: arch/arm/plat-s3c24xx/
F: arch/arm/plat-s5p/
ARM/S3C2410 ARM ARCHITECTURE
M: Ben Dooks <ben-linux@fluff.org>
@ -1149,7 +1151,7 @@ F: drivers/mmc/host/atmel-mci.c
F: drivers/mmc/host/atmel-mci-regs.h
ATMEL AT91 / AT32 SERIAL DRIVER
M: Haavard Skinnemoen <hskinnemoen@atmel.com>
M: Nicolas Ferre <nicolas.ferre@atmel.com>
S: Supported
F: drivers/serial/atmel_serial.c
@ -1161,18 +1163,18 @@ F: drivers/video/atmel_lcdfb.c
F: include/video/atmel_lcdc.h
ATMEL MACB ETHERNET DRIVER
M: Haavard Skinnemoen <hskinnemoen@atmel.com>
M: Nicolas Ferre <nicolas.ferre@atmel.com>
S: Supported
F: drivers/net/macb.*
ATMEL SPI DRIVER
M: Haavard Skinnemoen <hskinnemoen@atmel.com>
M: Nicolas Ferre <nicolas.ferre@atmel.com>
S: Supported
F: drivers/spi/atmel_spi.*
ATMEL USBA UDC DRIVER
M: Haavard Skinnemoen <hskinnemoen@atmel.com>
L: kernel@avr32linux.org
M: Nicolas Ferre <nicolas.ferre@atmel.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://avr32linux.org/twiki/bin/view/Main/AtmelUsbDeviceDriver
S: Supported
F: drivers/usb/gadget/atmel_usba_udc.*
@ -1582,7 +1584,7 @@ F: include/linux/coda*.h
COMMON INTERNET FILE SYSTEM (CIFS)
M: Steve French <sfrench@samba.org>
L: linux-cifs-client@lists.samba.org (moderated for non-subscribers)
L: linux-cifs@vger.kernel.org
L: samba-technical@lists.samba.org (moderated for non-subscribers)
W: http://linux-cifs.samba.org/
Q: http://patchwork.ozlabs.org/project/linux-cifs-client/list/
@ -1732,7 +1734,7 @@ S: Maintained
F: sound/pci/cs5535audio/
CX18 VIDEO4LINUX DRIVER
M: Andy Walls <awalls@radix.net>
M: Andy Walls <awalls@md.metrocast.net>
L: ivtv-devel@ivtvdriver.org (moderated for non-subscribers)
L: linux-media@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6.git
@ -2110,11 +2112,18 @@ F: drivers/edac/i5000_edac.c
EDAC-I5400
M: Mauro Carvalho Chehab <mchehab@redhat.com>
L: bluesmoke-devel@lists.sourceforge.net (moderated for non-subscribers)
L: linux-edac@vger.kernel.org
W: bluesmoke.sourceforge.net
S: Maintained
F: drivers/edac/i5400_edac.c
EDAC-I7CORE
M: Mauro Carvalho Chehab <mchehab@redhat.com>
L: linux-edac@vger.kernel.org
W: bluesmoke.sourceforge.net
S: Maintained
F: drivers/edac/i7core_edac.c linux/edac_mce.h drivers/edac/edac_mce.c
EDAC-I82975X
M: Ranganathan Desikan <ravi@jetztechnologies.com>
M: "Arvind R." <arvind@jetztechnologies.com>
@ -2888,6 +2897,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input.git
S: Maintained
F: drivers/input/
INPUT MULTITOUCH (MT) PROTOCOL
M: Henrik Rydberg <rydberg@euromail.se>
L: linux-input@vger.kernel.org
S: Maintained
F: Documentation/input/multi-touch-protocol.txt
K: \b(ABS|SYN)_MT_
INTEL IDLE DRIVER
M: Len Brown <lenb@kernel.org>
L: linux-pm@lists.linux-foundation.org
@ -2979,22 +2995,14 @@ F: drivers/net/ixgb/
F: drivers/net/ixgbe/
INTEL PRO/WIRELESS 2100 NETWORK CONNECTION SUPPORT
M: Zhu Yi <yi.zhu@intel.com>
M: Reinette Chatre <reinette.chatre@intel.com>
M: Intel Linux Wireless <ilw@linux.intel.com>
L: linux-wireless@vger.kernel.org
W: http://ipw2100.sourceforge.net
S: Odd Fixes
S: Orphan
F: Documentation/networking/README.ipw2100
F: drivers/net/wireless/ipw2x00/ipw2100.*
INTEL PRO/WIRELESS 2915ABG NETWORK CONNECTION SUPPORT
M: Zhu Yi <yi.zhu@intel.com>
M: Reinette Chatre <reinette.chatre@intel.com>
M: Intel Linux Wireless <ilw@linux.intel.com>
L: linux-wireless@vger.kernel.org
W: http://ipw2200.sourceforge.net
S: Odd Fixes
S: Orphan
F: Documentation/networking/README.ipw2200
F: drivers/net/wireless/ipw2x00/ipw2200.*
@ -3020,8 +3028,8 @@ F: drivers/net/wimax/i2400m/
F: include/linux/wimax/i2400m.h
INTEL WIRELESS WIFI LINK (iwlwifi)
M: Zhu Yi <yi.zhu@intel.com>
M: Reinette Chatre <reinette.chatre@intel.com>
M: Wey-Yi Guy <wey-yi.w.guy@intel.com>
M: Intel Linux Wireless <ilw@linux.intel.com>
L: linux-wireless@vger.kernel.org
W: http://intellinuxwireless.org
@ -3031,7 +3039,6 @@ F: drivers/net/wireless/iwlwifi/
INTEL WIRELESS MULTICOMM 3200 WIFI (iwmc3200wifi)
M: Samuel Ortiz <samuel.ortiz@intel.com>
M: Zhu Yi <yi.zhu@intel.com>
M: Intel Linux Wireless <ilw@linux.intel.com>
L: linux-wireless@vger.kernel.org
S: Supported
@ -3166,7 +3173,7 @@ F: Documentation/hwmon/it87
F: drivers/hwmon/it87.c
IVTV VIDEO4LINUX DRIVER
M: Andy Walls <awalls@radix.net>
M: Andy Walls <awalls@md.metrocast.net>
L: ivtv-devel@ivtvdriver.org (moderated for non-subscribers)
L: linux-media@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6.git
@ -3243,7 +3250,7 @@ L: autofs@linux.kernel.org
S: Maintained
F: fs/autofs4/
KERNEL BUILD
KERNEL BUILD + files below scripts/ (unless maintained elsewhere)
M: Michal Marek <mmarek@suse.cz>
T: git git://repo.or.cz/linux-kbuild.git for-next
T: git git://repo.or.cz/linux-kbuild.git for-linus
@ -3252,6 +3259,9 @@ S: Maintained
F: Documentation/kbuild/
F: Makefile
F: scripts/Makefile.*
F: scripts/basic/
F: scripts/mk*
F: scripts/package/
KERNEL JANITORS
L: kernel-janitors@vger.kernel.org
@ -3380,7 +3390,7 @@ KPROBES
M: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
M: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
M: "David S. Miller" <davem@davemloft.net>
M: Masami Hiramatsu <mhiramat@redhat.com>
M: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
S: Maintained
F: Documentation/kprobes.txt
F: include/linux/kprobes.h
@ -3501,9 +3511,8 @@ F: arch/powerpc/platforms/83xx/
LINUX FOR POWERPC PA SEMI PWRFICIENT
M: Olof Johansson <olof@lixom.net>
W: http://www.pasemi.com/
L: linuxppc-dev@ozlabs.org
S: Supported
S: Maintained
F: arch/powerpc/platforms/pasemi/
F: drivers/*/*pasemi*
F: drivers/*/*/*pasemi*
@ -4214,6 +4223,7 @@ OPEN FIRMWARE AND FLATTENED DEVICE TREE
M: Grant Likely <grant.likely@secretlab.ca>
L: devicetree-discuss@lists.ozlabs.org
W: http://fdt.secretlab.ca
T: git git://git.secretlab.ca/git/linux-2.6.git
S: Maintained
F: drivers/of
F: include/linux/of*.h
@ -4628,6 +4638,12 @@ M: Robert Jarzmik <robert.jarzmik@free.fr>
L: rtc-linux@googlegroups.com
S: Maintained
QLOGIC QLA1280 SCSI DRIVER
M: Michael Reed <mdr@sgi.com>
L: linux-scsi@vger.kernel.org
S: Maintained
F: drivers/scsi/qla1280.[ch]
QLOGIC QLA2XXX FC-SCSI DRIVER
M: Andrew Vasquez <andrew.vasquez@qlogic.com>
M: linux-driver@qlogic.com
@ -5386,6 +5402,7 @@ M: David Brownell <dbrownell@users.sourceforge.net>
M: Grant Likely <grant.likely@secretlab.ca>
L: spi-devel-general@lists.sourceforge.net
Q: http://patchwork.kernel.org/project/spi-devel-general/list/
T: git git://git.secretlab.ca/git/linux-2.6.git
S: Maintained
F: Documentation/spi/
F: drivers/spi/

85
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 35
EXTRAVERSION = -rc1
EXTRAVERSION = -rc4
NAME = Sheep on Meth
# *DOCUMENTATION*
@ -183,11 +183,14 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
# CROSS_COMPILE can be set on the command line
# make CROSS_COMPILE=ia64-linux-
# Alternatively CROSS_COMPILE can be set in the environment.
# A third alternative is to store a setting in .config so that plain
# "make" in the configured kernel build directory always uses that.
# Default value for CROSS_COMPILE is not to prefix executables
# Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile
export KBUILD_BUILDHOST := $(SUBARCH)
ARCH ?= $(SUBARCH)
CROSS_COMPILE ?=
CROSS_COMPILE ?= $(CONFIG_CROSS_COMPILE:"%"=%)
# Architecture as present in compile.h
UTS_MACHINE := $(ARCH)
@ -576,9 +579,6 @@ KBUILD_CFLAGS += $(call cc-option,-Wno-pointer-sign,)
# disable invalid "can't wrap" optimizations for signed / pointers
KBUILD_CFLAGS += $(call cc-option,-fno-strict-overflow)
# revert to pre-gcc-4.4 behaviour of .eh_frame
KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm)
# conserve stack if available
KBUILD_CFLAGS += $(call cc-option,-fconserve-stack)
@ -882,73 +882,11 @@ $(sort $(vmlinux-init) $(vmlinux-main)) $(vmlinux-lds): $(vmlinux-dirs) ;
PHONY += $(vmlinux-dirs)
$(vmlinux-dirs): prepare scripts
$(Q)$(MAKE) $(build)=$@
ifdef CONFIG_MODULES
$(Q)$(MAKE) $(modbuiltin)=$@
endif
# Build the kernel release string
#
# The KERNELRELEASE value built here is stored in the file
# include/config/kernel.release, and is used when executing several
# make targets, such as "make install" or "make modules_install."
#
# The eventual kernel release string consists of the following fields,
# shown in a hierarchical format to show how smaller parts are concatenated
# to form the larger and final value, with values coming from places like
# the Makefile, kernel config options, make command line options and/or
# SCM tag information.
#
# $(KERNELVERSION)
# $(VERSION) eg, 2
# $(PATCHLEVEL) eg, 6
# $(SUBLEVEL) eg, 18
# $(EXTRAVERSION) eg, -rc6
# $(localver-full)
# $(localver)
# localversion* (files without backups, containing '~')
# $(CONFIG_LOCALVERSION) (from kernel config setting)
# $(localver-auto) (only if CONFIG_LOCALVERSION_AUTO is set)
# ./scripts/setlocalversion (SCM tag, if one exists)
# $(LOCALVERSION) (from make command line if provided)
#
# Note how the final $(localver-auto) string is included *only* if the
# kernel config option CONFIG_LOCALVERSION_AUTO is selected. Also, at the
# moment, only git is supported but other SCMs can edit the script
# scripts/setlocalversion and add the appropriate checks as needed.
pattern = ".*/localversion[^~]*"
string = $(shell cat /dev/null \
`find $(objtree) $(srctree) -maxdepth 1 -regex $(pattern) | sort -u`)
localver = $(subst $(space),, $(string) \
$(patsubst "%",%,$(CONFIG_LOCALVERSION)))
# If CONFIG_LOCALVERSION_AUTO is set scripts/setlocalversion is called
# and if the SCM is know a tag from the SCM is appended.
# The appended tag is determined by the SCM used.
#
# .scmversion is used when generating rpm packages so we do not loose
# the version information from the SCM when we do the build of the kernel
# from the copied source
ifdef CONFIG_LOCALVERSION_AUTO
ifeq ($(wildcard .scmversion),)
_localver-auto = $(shell $(CONFIG_SHELL) \
$(srctree)/scripts/setlocalversion $(srctree))
else
_localver-auto = $(shell cat .scmversion 2> /dev/null)
endif
localver-auto = $(LOCALVERSION)$(_localver-auto)
endif
localver-full = $(localver)$(localver-auto)
# Store (new) KERNELRELASE string in include/config/kernel.release
kernelrelease = $(KERNELVERSION)$(localver-full)
include/config/kernel.release: include/config/auto.conf FORCE
$(Q)rm -f $@
$(Q)echo $(kernelrelease) > $@
$(Q)echo "$(KERNELVERSION)$$($(CONFIG_SHELL) scripts/setlocalversion $(srctree))" > $@
# Things we need to do before we recursively start building the kernel
@ -1087,13 +1025,18 @@ all: modules
# using awk while concatenating to the final file.
PHONY += modules
modules: $(vmlinux-dirs) $(if $(KBUILD_BUILTIN),vmlinux)
modules: $(vmlinux-dirs) $(if $(KBUILD_BUILTIN),vmlinux) modules.builtin
$(Q)$(AWK) '!x[$$0]++' $(vmlinux-dirs:%=$(objtree)/%/modules.order) > $(objtree)/modules.order
$(Q)$(AWK) '!x[$$0]++' $(vmlinux-dirs:%=$(objtree)/%/modules.builtin) > $(objtree)/modules.builtin
@$(kecho) ' Building modules, stage 2.';
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.fwinst obj=firmware __fw_modbuild
modules.builtin: $(vmlinux-dirs:%=%/modules.builtin)
$(Q)$(AWK) '!x[$$0]++' $^ > $(objtree)/modules.builtin
%/modules.builtin: include/config/auto.conf
$(Q)$(MAKE) $(modbuiltin)=$*
# Target to prepare building external modules
PHONY += modules_prepare
@ -1247,7 +1190,9 @@ help:
@echo ' firmware_install- Install all firmware to INSTALL_FW_PATH'
@echo ' (default: $$(INSTALL_MOD_PATH)/lib/firmware)'
@echo ' dir/ - Build all files in dir and below'
@echo ' dir/file.[ois] - Build specified target only'
@echo ' dir/file.[oisS] - Build specified target only'
@echo ' dir/file.lst - Build specified mixed source/assembly target only'
@echo ' (requires a recent binutils and recent build (System.map))'
@echo ' dir/file.ko - Build module including final link'
@echo ' modules_prepare - Set up for building external modules'
@echo ' tags/TAGS - Generate tags file for editors'

2
arch/alpha/include/asm/bitops.h
View File

@ -410,7 +410,7 @@ static inline unsigned long __arch_hweight64(unsigned long w)
return __kernel_ctpop(w);
}
static inline unsigned int __arch_weight32(unsigned int w)
static inline unsigned int __arch_hweight32(unsigned int w)
{
return __arch_hweight64(w);
}

20
arch/alpha/kernel/Makefile
View File

@ -35,7 +35,7 @@ endif
obj-y += irq_pyxis.o irq_i8259.o irq_srm.o
obj-y += err_ev6.o
obj-y += es1888.o smc37c669.o smc37c93x.o ns87312.o gct.o
obj-y += es1888.o smc37c669.o smc37c93x.o pc873xx.o gct.o
obj-y += srmcons.o
else
@ -63,11 +63,11 @@ obj-$(CONFIG_ALPHA_WILDFIRE) += core_wildfire.o
# Board support
obj-$(CONFIG_ALPHA_ALCOR) += sys_alcor.o irq_i8259.o irq_srm.o
obj-$(CONFIG_ALPHA_CABRIOLET) += sys_cabriolet.o irq_i8259.o irq_srm.o \
ns87312.o
pc873xx.o
obj-$(CONFIG_ALPHA_EB164) += sys_cabriolet.o irq_i8259.o irq_srm.o \
ns87312.o
pc873xx.o
obj-$(CONFIG_ALPHA_EB66P) += sys_cabriolet.o irq_i8259.o irq_srm.o \
ns87312.o
pc873xx.o
obj-$(CONFIG_ALPHA_LX164) += sys_cabriolet.o irq_i8259.o irq_srm.o \
smc37c93x.o
obj-$(CONFIG_ALPHA_PC164) += sys_cabriolet.o irq_i8259.o irq_srm.o \
@ -90,14 +90,14 @@ obj-$(CONFIG_ALPHA_RUFFIAN) += sys_ruffian.o irq_pyxis.o irq_i8259.o
obj-$(CONFIG_ALPHA_RX164) += sys_rx164.o irq_i8259.o
obj-$(CONFIG_ALPHA_SABLE) += sys_sable.o
obj-$(CONFIG_ALPHA_LYNX) += sys_sable.o
obj-$(CONFIG_ALPHA_BOOK1) += sys_sio.o irq_i8259.o irq_srm.o ns87312.o
obj-$(CONFIG_ALPHA_AVANTI) += sys_sio.o irq_i8259.o irq_srm.o ns87312.o
obj-$(CONFIG_ALPHA_NONAME) += sys_sio.o irq_i8259.o irq_srm.o ns87312.o
obj-$(CONFIG_ALPHA_P2K) += sys_sio.o irq_i8259.o irq_srm.o ns87312.o
obj-$(CONFIG_ALPHA_XL) += sys_sio.o irq_i8259.o irq_srm.o ns87312.o
obj-$(CONFIG_ALPHA_BOOK1) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o
obj-$(CONFIG_ALPHA_AVANTI) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o
obj-$(CONFIG_ALPHA_NONAME) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o
obj-$(CONFIG_ALPHA_P2K) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o
obj-$(CONFIG_ALPHA_XL) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o
obj-$(CONFIG_ALPHA_SX164) += sys_sx164.o irq_pyxis.o irq_i8259.o \
irq_srm.o smc37c669.o
obj-$(CONFIG_ALPHA_TAKARA) += sys_takara.o irq_i8259.o ns87312.o
obj-$(CONFIG_ALPHA_TAKARA) += sys_takara.o irq_i8259.o pc873xx.o
obj-$(CONFIG_ALPHA_WILDFIRE) += sys_wildfire.o irq_i8259.o
# Error support

38
arch/alpha/kernel/ns87312.c
View File

@ -1,38 +0,0 @@
/*
* linux/arch/alpha/kernel/ns87312.c
*/
#include <linux/init.h>
#include <asm/io.h>
#include "proto.h"
/*
* The SRM console *disables* the IDE interface, this code ensures it's
* enabled.
*
* This code bangs on a control register of the 87312 Super I/O chip
* that implements parallel port/serial ports/IDE/FDI. Depending on
* the motherboard, the Super I/O chip can be configured through a
* pair of registers that are located either at I/O ports 0x26e/0x26f
* or 0x398/0x399. Unfortunately, autodetecting which base address is
* in use works only once (right after a reset). The Super I/O chip
* has the additional quirk that configuration register data must be
* written twice (I believe this is a safety feature to prevent
* accidental modification---fun, isn't it?).
*/
void __init
ns87312_enable_ide(long ide_base)
{
int data;
unsigned long flags;
local_irq_save(flags);
outb(0, ide_base); /* set the index register for reg #0 */
data = inb(ide_base+1); /* read the current contents */
outb(0, ide_base); /* set the index register for reg #0 */
outb(data | 0x40, ide_base+1); /* turn on IDE */
outb(data | 0x40, ide_base+1); /* turn on IDE, really! */
local_irq_restore(flags);
}

88
arch/alpha/kernel/pc873xx.c Normal file
View File

@ -0,0 +1,88 @@
#include <linux/ioport.h>
#include <asm/io.h>
#include "pc873xx.h"
static unsigned pc873xx_probelist[] = {0x398, 0x26e, 0};
static char *pc873xx_names[] = {
"PC87303", "PC87306", "PC87312", "PC87332", "PC87334"
};
static unsigned int base, model;
unsigned int __init pc873xx_get_base()
{
return base;
}
char *__init pc873xx_get_model()
{
return pc873xx_names[model];
}
static unsigned char __init pc873xx_read(unsigned int base, int reg)
{
outb(reg, base);
return inb(base + 1);
}
static void __init pc873xx_write(unsigned int base, int reg, unsigned char data)
{
unsigned long flags;
local_irq_save(flags);
outb(reg, base);
outb(data, base + 1);
outb(data, base + 1); /* Must be written twice */
local_irq_restore(flags);
}
int __init pc873xx_probe(void)
{
int val, index = 0;
while ((base = pc873xx_probelist[index++])) {
if (request_region(base, 2, "Super IO PC873xx") == NULL)
continue;
val = pc873xx_read(base, REG_SID);
if ((val & 0xf0) == 0x10) {
model = PC87332;
break;
} else if ((val & 0xf8) == 0x70) {
model = PC87306;
break;
} else if ((val & 0xf8) == 0x50) {
model = PC87334;
break;
} else if ((val & 0xf8) == 0x40) {
model = PC87303;
break;
}
release_region(base, 2);
}
return (base == 0) ? -1 : 1;
}
void __init pc873xx_enable_epp19(void)
{
unsigned char data;
printk(KERN_INFO "PC873xx enabling EPP v1.9\n");
data = pc873xx_read(base, REG_PCR);
pc873xx_write(base, REG_PCR, (data & 0xFC) | 0x02);
}
void __init pc873xx_enable_ide(void)
{
unsigned char data;
printk(KERN_INFO "PC873xx enabling IDE interrupt\n");
data = pc873xx_read(base, REG_FER);
pc873xx_write(base, REG_FER, data | 0x40);
}

35
arch/alpha/kernel/pc873xx.h Normal file
View File

@ -0,0 +1,35 @@
#ifndef _PC873xx_H_
#define _PC873xx_H_
/*
* Control Register Values
*/
#define REG_FER 0x00
#define REG_FAR 0x01
#define REG_PTR 0x02
#define REG_FCR 0x03
#define REG_PCR 0x04
#define REG_KRR 0x05
#define REG_PMC 0x06
#define REG_TUP 0x07
#define REG_SID 0x08
#define REG_ASC 0x09
#define REG_IRC 0x0e
/*
* Model numbers
*/
#define PC87303 0
#define PC87306 1
#define PC87312 2
#define PC87332 3
#define PC87334 4
int pc873xx_probe(void);
unsigned int pc873xx_get_base(void);
char *pc873xx_get_model(void);
void pc873xx_enable_epp19(void);
void pc873xx_enable_ide(void);
#endif

3
arch/alpha/kernel/pci-sysfs.c
View File

@ -53,7 +53,6 @@ static int __pci_mmap_fits(struct pci_dev *pdev, int num,
/**
* pci_mmap_resource - map a PCI resource into user memory space
* @filp: open sysfs file
* @kobj: kobject for mapping
* @attr: struct bin_attribute for the file being mapped
* @vma: struct vm_area_struct passed into the mmap
@ -61,7 +60,7 @@ static int __pci_mmap_fits(struct pci_dev *pdev, int num,
*
* Use the bus mapping routines to map a PCI resource into userspace.
*/
static int pci_mmap_resource(struct file *filp, struct kobject *kobj,
static int pci_mmap_resource(struct kobject *kobj,
struct bin_attribute *attr,
struct vm_area_struct *vma, int sparse)
{

23
arch/alpha/kernel/sys_sio.c
View File

@ -34,6 +34,7 @@
#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
#include "pc873xx.h"
#if defined(ALPHA_RESTORE_SRM_SETUP)
/* Save LCA configuration data as the console had it set up. */
@ -208,7 +209,27 @@ noname_init_pci(void)
common_init_pci();
sio_pci_route();
sio_fixup_irq_levels(sio_collect_irq_levels());
ns87312_enable_ide(0x26e);
if (pc873xx_probe() == -1) {
printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
} else {
printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
pc873xx_get_model(), pc873xx_get_base());
/* Enabling things in the Super IO chip doesn't actually
* configure and enable things, the legacy drivers still
* need to do the actual configuration and enabling.
* This only unblocks them.
*/
#if !defined(CONFIG_ALPHA_AVANTI)
/* Don't bother on the Avanti family.
* None of them had on-board IDE.
*/
pc873xx_enable_ide();
#endif
pc873xx_enable_epp19();
}
}
static inline void __init

3
arch/arm/Kconfig
View File

@ -955,7 +955,8 @@ config XSCALE_PMU
default y
config CPU_HAS_PMU
depends on CPU_V6 || CPU_V7 || XSCALE_PMU
depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
(!ARCH_OMAP3 || OMAP3_EMU)
default y
bool

9
arch/arm/common/sa1111.c
View File

@ -951,8 +951,6 @@ static int sa1111_resume(struct platform_device *dev)
if (!save)
return 0;
spin_lock_irqsave(&sachip->lock, flags);
/*
* Ensure that the SA1111 is still here.
* FIXME: shouldn't do this here.
@ -969,6 +967,13 @@ static int sa1111_resume(struct platform_device *dev)
* First of all, wake up the chip.
*/
sa1111_wake(sachip);
/*
* Only lock for write ops. Also, sa1111_wake must be called with
* released spinlock!
*/
spin_lock_irqsave(&sachip->lock, flags);
sa1111_writel(0, sachip->base + SA1111_INTC + SA1111_INTEN0);
sa1111_writel(0, sachip->base + SA1111_INTC + SA1111_INTEN1);

4
arch/arm/include/asm/mach/udc_pxa2xx.h
View File

@ -21,8 +21,8 @@ struct pxa2xx_udc_mach_info {
* here. Note that sometimes the signals go through inverters...
*/
bool gpio_vbus_inverted;
u16 gpio_vbus; /* high == vbus present */
int gpio_vbus; /* high == vbus present */
bool gpio_pullup_inverted;
u16 gpio_pullup; /* high == pullup activated */
int gpio_pullup; /* high == pullup activated */
};

4
arch/arm/include/asm/processor.h
View File

@ -91,7 +91,11 @@ extern void release_thread(struct task_struct *);
unsigned long get_wchan(struct task_struct *p);
#if __LINUX_ARM_ARCH__ == 6
#define cpu_relax() smp_mb()
#else
#define cpu_relax() barrier()
#endif
/*
* Create a new kernel thread

2
arch/arm/kernel/perf_event.c
View File

@ -201,7 +201,7 @@ armpmu_event_update(struct perf_event *event,
{
int shift = 64 - 32;
s64 prev_raw_count, new_raw_count;
s64 delta;
u64 delta;
again:
prev_raw_count = atomic64_read(&hwc->prev_count);

1
arch/arm/mach-msm/dma.c
View File

@ -17,6 +17,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/completion.h>
#include <mach/dma.h>
#define MSM_DMOV_CHANNEL_COUNT 16

33
arch/arm/mach-mx3/mach-mx31lilly.c
View File

@ -115,6 +115,8 @@ static struct platform_device physmap_flash_device = {
/* USB */
#if defined(CONFIG_USB_ULPI)
#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
@ -244,10 +246,20 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
.flags = MXC_EHCI_POWER_PINS_ENABLED,
};
static struct platform_device *devices[] __initdata = {
&smsc91x_device,
&physmap_flash_device,
};
static void lilly1131_usb_init(void)
{
usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
mxc_register_device(&mxc_usbh1, &usbh1_pdata);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
}
#else
static inline void lilly1131_usb_init(void) {}
#endif /* CONFIG_USB_ULPI */
/* SPI */
@ -279,6 +291,11 @@ static struct spi_board_info mc13783_dev __initdata = {
.platform_data = &mc13783_pdata,
};
static struct platform_device *devices[] __initdata = {
&smsc91x_device,
&physmap_flash_device,
};
static int mx31lilly_baseboard;
core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444);
@ -321,13 +338,7 @@ static void __init mx31lilly_board_init(void)
platform_add_devices(devices, ARRAY_SIZE(devices));
/* USB */
usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
mxc_register_device(&mxc_usbh1, &usbh1_pdata);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
lilly1131_usb_init();
}
static void __init mx31lilly_timer_init(void)

11
arch/arm/mach-nomadik/clock.c
View File

@ -32,7 +32,10 @@ void clk_disable(struct clk *clk)
}
EXPORT_SYMBOL(clk_disable);
/* We have a fixed clock alone, for now */
static struct clk clk_24 = {
.rate = 2400000,
};
static struct clk clk_48 = {
.rate = 48 * 1000 * 1000,
};
@ -50,6 +53,8 @@ static struct clk clk_default;
}
static struct clk_lookup lookups[] = {
CLK(&clk_24, "mtu0"),
CLK(&clk_24, "mtu1"),
CLK(&clk_48, "uart0"),
CLK(&clk_48, "uart1"),
CLK(&clk_default, "gpio.0"),
@ -59,10 +64,8 @@ static struct clk_lookup lookups[] = {
CLK(&clk_default, "rng"),
};
static int __init clk_init(void)
int __init clk_init(void)
{
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
return 0;
}
arch_initcall(clk_init);

2
arch/arm/mach-nomadik/clock.h
View File

@ -11,3 +11,5 @@
struct clk {
unsigned long rate;
};
int __init clk_init(void);

8
arch/arm/mach-nomadik/cpu-8815.c
View File

@ -31,6 +31,8 @@
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include "clock.h"
#define __MEM_4K_RESOURCE(x) \
.res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
@ -143,6 +145,12 @@ void __init cpu8815_init_irq(void)
/* This modified VIC cell has two register blocks, at 0 and 0x20 */
vic_init(io_p2v(NOMADIK_IC_BASE + 0x00), IRQ_VIC_START + 0, ~0, 0);
vic_init(io_p2v(NOMADIK_IC_BASE + 0x20), IRQ_VIC_START + 32, ~0, 0);
/*
* Init clocks here so that they are available for system timer
* initialization.
*/
clk_init();
}
/*

4
arch/arm/mach-omap2/board-omap3stalker.c
View File

@ -538,9 +538,7 @@ static void ads7846_dev_init(void)
printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
gpio_direction_input(OMAP3_STALKER_TS_GPIO);
omap_set_gpio_debounce(OMAP3_STALKER_TS_GPIO, 1);
omap_set_gpio_debounce_time(OMAP3_STALKER_TS_GPIO, 0xa);
gpio_set_debounce(OMAP3_STALKER_TS_GPIO, 310);
}
static int ads7846_get_pendown_state(void)

2
arch/arm/mach-omap2/clock44xx_data.c
View File

@ -1369,6 +1369,7 @@ static struct clk emif1_ick = {
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.flags = ENABLE_ON_INIT,
.clkdm_name = "l3_emif_clkdm",
.parent = &ddrphy_ck,
.recalc = &followparent_recalc,
@ -1379,6 +1380,7 @@ static struct clk emif2_ick = {
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.flags = ENABLE_ON_INIT,
.clkdm_name = "l3_emif_clkdm",
.parent = &ddrphy_ck,
.recalc = &followparent_recalc,

9
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -409,10 +409,11 @@ static int _init_main_clk(struct omap_hwmod *oh)
return 0;
oh->_clk = omap_clk_get_by_name(oh->main_clk);
if (!oh->_clk)
if (!oh->_clk) {
pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
oh->name, oh->main_clk);
return -EINVAL;
}
if (!oh->_clk->clkdm)
pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
@ -444,10 +445,11 @@ static int _init_interface_clks(struct omap_hwmod *oh)
continue;
c = omap_clk_get_by_name(os->clk);
if (!c)
if (!c) {
pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
oh->name, os->clk);
ret = -EINVAL;
}
os->_clk = c;
}
@ -470,10 +472,11 @@ static int _init_opt_clks(struct omap_hwmod *oh)
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
c = omap_clk_get_by_name(oc->clk);
if (!c)
if (!c) {
pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
oh->name, oc->clk);
ret = -EINVAL;
}
oc->_clk = c;
}

4
arch/arm/mach-omap2/pm34xx.c
View File

@ -99,7 +99,7 @@ static void omap3_enable_io_chain(void)
/* Do a readback to assure write has been done */
prm_read_mod_reg(WKUP_MOD, PM_WKEN);
while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
OMAP3430_ST_IO_CHAIN_MASK)) {
timeout++;
if (timeout > 1000) {
@ -108,7 +108,7 @@ static void omap3_enable_io_chain(void)
return;
}
prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
WKUP_MOD, PM_WKST);
WKUP_MOD, PM_WKEN);
}
}
}

2
arch/arm/mach-omap2/usb-ehci.c
View File

@ -20,6 +20,8 @@
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <asm/io.h>
#include <plat/mux.h>

2
arch/arm/mach-pxa/mioa701.c
View File

@ -697,7 +697,7 @@ static struct i2c_board_info __initdata mioa701_pi2c_devices[] = {
};
/* Board I2C devices. */
static struct i2c_board_info __initdata mioa701_i2c_devices[] = {
static struct i2c_board_info mioa701_i2c_devices[] = {
{
I2C_BOARD_INFO("mt9m111", 0x5d),
},

4
arch/arm/mach-pxa/palmtc.c
View File

@ -263,11 +263,11 @@ const struct matrix_keymap_data palmtc_keymap_data = {
.keymap_size = ARRAY_SIZE(palmtc_matrix_keys),
};
const static unsigned int palmtc_keypad_row_gpios[] = {
static const unsigned int palmtc_keypad_row_gpios[] = {
0, 9, 10, 11
};
const static unsigned int palmtc_keypad_col_gpios[] = {
static const unsigned int palmtc_keypad_col_gpios[] = {
18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 79, 80
};

3
arch/arm/mach-pxa/spitz.c
View File

@ -818,6 +818,9 @@ static struct i2c_board_info akita_i2c_board_info[] = {
.type = "max7310",
.addr = 0x18,
.platform_data = &akita_ioexp,
}, {
.type = "wm8750",
.addr = 0x1b,
},
};

26
arch/arm/mach-pxa/z2.c
View File

@ -3,8 +3,9 @@
*
* Support for the Zipit Z2 Handheld device.
*
* Author: Ken McGuire
* Created: Jan 25, 2009
* Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
*
* Based on research and code by: Ken McGuire
* Based on mainstone.c as modified for the Zipit Z2.
*
* This program is free software; you can redistribute it and/or modify
@ -157,21 +158,14 @@ static struct mtd_partition z2_flash_parts[] = {
{
.name = "U-Boot Bootloader",
.offset = 0x0,
.size = 0x20000,
},
{
.name = "Linux Kernel",
.offset = 0x20000,
.size = 0x220000,
},
{
.name = "Filesystem",
.offset = 0x240000,
.size = 0x5b0000,
},
{
.size = 0x40000,
}, {
.name = "U-Boot Environment",
.offset = 0x7f0000,
.offset = 0x40000,
.size = 0x60000,
}, {
.name = "Flash",
.offset = 0x60000,
.size = MTDPART_SIZ_FULL,
},
};

2
arch/arm/mach-realview/Kconfig
View File

@ -18,6 +18,7 @@ config REALVIEW_EB_ARM11MP
bool "Support ARM11MPCore tile"
depends on MACH_REALVIEW_EB
select CPU_V6
select ARCH_HAS_BARRIERS if SMP
help
Enable support for the ARM11MPCore tile on the Realview platform.
@ -35,6 +36,7 @@ config MACH_REALVIEW_PB11MP
select CPU_V6
select ARM_GIC
select HAVE_PATA_PLATFORM
select ARCH_HAS_BARRIERS if SMP
help
Include support for the ARM(R) RealView MPCore Platform Baseboard.
PB11MPCore is a platform with an on-board ARM11MPCore and has

8
arch/arm/mach-realview/include/mach/barriers.h Normal file
View File

@ -0,0 +1,8 @@
/*
* Barriers redefined for RealView ARM11MPCore platforms with L220 cache
* controller to work around hardware errata causing the outer_sync()
* operation to deadlock the system.
*/
#define mb() dsb()
#define rmb() dmb()
#define wmb() mb()

3
arch/arm/mach-realview/realview_eb.c
View File

@ -32,6 +32,7 @@
#include <asm/leds.h>
#include <asm/mach-types.h>
#include <asm/pmu.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/localtimer.h>
@ -457,7 +458,7 @@ static void __init realview_eb_init(void)
MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
.phys_io = REALVIEW_EB_UART0_BASE,
.phys_io = REALVIEW_EB_UART0_BASE & SECTION_MASK,
.io_pg_offst = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x00000100,
.fixup = realview_fixup,

3
arch/arm/mach-realview/realview_pb1176.c
View File

@ -32,6 +32,7 @@
#include <asm/leds.h>
#include <asm/mach-types.h>
#include <asm/pmu.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
@ -351,7 +352,7 @@ static void __init realview_pb1176_init(void)
MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
.phys_io = REALVIEW_PB1176_UART0_BASE,
.phys_io = REALVIEW_PB1176_UART0_BASE & SECTION_MASK,
.io_pg_offst = (IO_ADDRESS(REALVIEW_PB1176_UART0_BASE) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x00000100,
.fixup = realview_pb1176_fixup,

3
arch/arm/mach-realview/realview_pb11mp.c
View File

@ -32,6 +32,7 @@
#include <asm/leds.h>
#include <asm/mach-types.h>
#include <asm/pmu.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/localtimer.h>
@ -373,7 +374,7 @@ static void __init realview_pb11mp_init(void)
MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
.phys_io = REALVIEW_PB11MP_UART0_BASE,
.phys_io = REALVIEW_PB11MP_UART0_BASE & SECTION_MASK,
.io_pg_offst = (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x00000100,
.fixup = realview_fixup,

3
arch/arm/mach-realview/realview_pba8.c
View File

@ -31,6 +31,7 @@
#include <asm/leds.h>
#include <asm/mach-types.h>
#include <asm/pmu.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
@ -323,7 +324,7 @@ static void __init realview_pba8_init(void)
MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
.phys_io = REALVIEW_PBA8_UART0_BASE,
.phys_io = REALVIEW_PBA8_UART0_BASE & SECTION_MASK,
.io_pg_offst = (IO_ADDRESS(REALVIEW_PBA8_UART0_BASE) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x00000100,
.fixup = realview_fixup,

3
arch/arm/mach-realview/realview_pbx.c
View File

@ -31,6 +31,7 @@
#include <asm/mach-types.h>
#include <asm/pmu.h>
#include <asm/smp_twd.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
@ -409,7 +410,7 @@ static void __init realview_pbx_init(void)
MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
.phys_io = REALVIEW_PBX_UART0_BASE,
.phys_io = REALVIEW_PBX_UART0_BASE & SECTION_MASK,
.io_pg_offst = (IO_ADDRESS(REALVIEW_PBX_UART0_BASE) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x00000100,
.fixup = realview_pbx_fixup,

3
arch/arm/mach-ux500/Makefile
View File

@ -7,4 +7,5 @@ obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o
obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o
obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o
obj-$(CONFIG_MACH_U5500) += board-u5500.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o

104
arch/arm/mach-ux500/clock.c
View File

@ -16,6 +16,7 @@
#include <asm/clkdev.h>
#include <plat/mtu.h>
#include <mach/hardware.h>
#include "clock.h"
@ -59,6 +60,9 @@
#define PRCM_DMACLK_MGT 0x074
#define PRCM_B2R2CLK_MGT 0x078
#define PRCM_TVCLK_MGT 0x07C
#define PRCM_TCR 0x1C8
#define PRCM_TCR_STOPPED (1 << 16)
#define PRCM_TCR_DOZE_MODE (1 << 17)
#define PRCM_UNIPROCLK_MGT 0x278
#define PRCM_SSPCLK_MGT 0x280
#define PRCM_RNGCLK_MGT 0x284
@ -120,10 +124,95 @@ void clk_disable(struct clk *clk)
}
EXPORT_SYMBOL(clk_disable);
/*
* The MTU has a separate, rather complex muxing setup
* with alternative parents (peripheral cluster or
* ULP or fixed 32768 Hz) depending on settings
*/
static unsigned long clk_mtu_get_rate(struct clk *clk)
{
void __iomem *addr = __io_address(U8500_PRCMU_BASE)
+ PRCM_TCR;
u32 tcr = readl(addr);
int mtu = (int) clk->data;
/*
* One of these is selected eventually
* TODO: Replace the constant with a reference
* to the ULP source once this is modeled.
*/
unsigned long clk32k = 32768;
unsigned long mturate;
unsigned long retclk;
/* Get the rate from the parent as a default */
if (clk->parent_periph)
mturate = clk_get_rate(clk->parent_periph);
else if (clk->parent_cluster)
mturate = clk_get_rate(clk->parent_cluster);
else
/* We need to be connected SOMEWHERE */
BUG();
/*
* Are we in doze mode?
* In this mode the parent peripheral or the fixed 32768 Hz
* clock is fed into the block.
*/
if (!(tcr & PRCM_TCR_DOZE_MODE)) {
/*
* Here we're using the clock input from the APE ULP
* clock domain. But first: are the timers stopped?
*/
if (tcr & PRCM_TCR_STOPPED) {
clk32k = 0;
mturate = 0;
} else {
/* Else default mode: 0 and 2.4 MHz */
clk32k = 0;
if (cpu_is_u5500())
/* DB5500 divides by 8 */
mturate /= 8;
else if (cpu_is_u8500ed()) {
/*
* This clocking setting must not be used
* in the ED chip, it is simply not
* connected anywhere!
*/
mturate = 0;
BUG();
} else
/*
* In this mode the ulp38m4 clock is divided
* by a factor 16, on the DB8500 typically
* 38400000 / 16 ~ 2.4 MHz.
* TODO: Replace the constant with a reference
* to the ULP source once this is modeled.
*/
mturate = 38400000 / 16;
}
}
/* Return the clock selected for this MTU */
if (tcr & (1 << mtu))
retclk = clk32k;
else
retclk = mturate;
pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk);
return retclk;
}
unsigned long clk_get_rate(struct clk *clk)
{
unsigned long rate;
/*
* If there is a custom getrate callback for this clock,
* it will take precedence.
*/
if (clk->get_rate)
return clk->get_rate(clk);
if (clk->ops && clk->ops->get_rate)
return clk->ops->get_rate(clk);
@ -341,8 +430,9 @@ static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL);
/* Peripheral Cluster #6 */
static DEFINE_PRCC_CLK(6, mtu1_v1, 8, -1, NULL);
static DEFINE_PRCC_CLK(6, mtu0_v1, 7, -1, NULL);
/* MTU ID in data */
static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1);
static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0);
static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL);
static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL);
static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL);
@ -357,8 +447,9 @@ static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk);
/* Peripheral Cluster #7 */
static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL);
static DEFINE_PRCC_CLK(7, mtu1_ed, 3, -1, NULL);
static DEFINE_PRCC_CLK(7, mtu0_ed, 2, -1, NULL);
/* MTU ID in data */
static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1);
static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL);
static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL);
@ -503,15 +594,17 @@ static struct clk_lookup u8500_v1_clks[] = {
CLK(uiccclk, "uicc", NULL),
};
static int __init clk_init(void)
int __init clk_init(void)
{
if (cpu_is_u8500ed()) {
clk_prcmu_ops.enable = clk_prcmu_ed_enable;
clk_prcmu_ops.disable = clk_prcmu_ed_disable;
clk_per6clk.rate = 100000000;
} else if (cpu_is_u5500()) {
/* Clock tree for U5500 not implemented yet */
clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
clk_per6clk.rate = 26000000;
}
clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
@ -522,4 +615,3 @@ static int __init clk_init(void)
return 0;
}
arch_initcall(clk_init);

22
arch/arm/mach-ux500/clock.h
View File

@ -28,6 +28,9 @@ struct clkops {
* @ops: pointer to clkops struct used to control this clock
* @name: name, for debugging
* @enabled: refcount. positive if enabled, zero if disabled
* @get_rate: custom callback for getting the clock rate
* @data: custom per-clock data for example for the get_rate
* callback
* @rate: fixed rate for clocks which don't implement
* ops->getrate
* @prcmu_cg_off: address offset of the combined enable/disable register
@ -67,6 +70,8 @@ struct clk {
const struct clkops *ops;
const char *name;
unsigned int enabled;
unsigned long (*get_rate)(struct clk *);
void *data;
unsigned long rate;
struct list_head list;
@ -117,9 +122,26 @@ struct clk clk_##_name = { \
.parent_periph = _kernclk \
}
#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \
struct clk clk_##_name = { \
.name = #_name, \
.ops = &clk_prcc_ops, \
.cluster = _pclust, \
.prcc_bus = _bus_en, \
.prcc_kernel = _kernel_en, \
.parent_cluster = &clk_per##_pclust##clk, \
.parent_periph = _kernclk, \
.get_rate = _callback, \
.data = (void *) _data \
}
#define CLK(_clk, _devname, _conname) \
{ \
.clk = &clk_##_clk, \
.dev_id = _devname, \
.con_id = _conname, \
}
int __init clk_db8500_ed_fixup(void);
int __init clk_init(void);

6
arch/arm/mach-ux500/cpu.c
View File

@ -62,6 +62,12 @@ void __init ux500_init_irq(void)
{
gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29);
gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
/*
* Init clocks here so that they are available for system timer
* initialization.
*/
clk_init();
}
#ifdef CONFIG_CACHE_L2X0

4
arch/arm/mach-vexpress/ct-ca9x4.c
View File

@ -2,6 +2,7 @@
* Versatile Express Core Tile Cortex A9x4 Support
*/
#include <linux/init.h>
#include <linux/gfp.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
@ -9,6 +10,7 @@
#include <linux/amba/clcd.h>
#include <asm/clkdev.h>
#include <asm/pgtable.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
@ -235,7 +237,7 @@ static void ct_ca9x4_init(void)
}
MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
.phys_io = V2M_UART0,
.phys_io = V2M_UART0 & SECTION_MASK,
.io_pg_offst = (__MMIO_P2V(V2M_UART0) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x00000100,
.map_io = ct_ca9x4_map_io,

21
arch/arm/mm/Kconfig
View File

@ -735,6 +735,25 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
Forget about fast user space cmpxchg support.
It is just not possible.
config DMA_CACHE_RWFO
bool "Enable read/write for ownership DMA cache maintenance"
depends on CPU_V6 && SMP
default y
help
The Snoop Control Unit on ARM11MPCore does not detect the
cache maintenance operations and the dma_{map,unmap}_area()
functions may leave stale cache entries on other CPUs. By
enabling this option, Read or Write For Ownership in the ARMv6
DMA cache maintenance functions is performed. These LDR/STR
instructions change the cache line state to shared or modified
so that the cache operation has the desired effect.
Note that the workaround is only valid on processors that do
not perform speculative loads into the D-cache. For such
processors, if cache maintenance operations are not broadcast
in hardware, other workarounds are needed (e.g. cache
maintenance broadcasting in software via FIQ).
config OUTER_CACHE
bool
@ -794,6 +813,8 @@ config ARM_L1_CACHE_SHIFT
config ARM_DMA_MEM_BUFFERABLE
bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7
depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
MACH_REALVIEW_PB11MP)
default y if CPU_V6 || CPU_V7
help
Historically, the kernel has used strongly ordered mappings to

18
arch/arm/mm/cache-v6.S
View File

@ -211,8 +211,9 @@ v6_dma_inv_range:
mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
#endif
1:
#ifdef CONFIG_SMP
str r0, [r0] @ write for ownership
#ifdef CONFIG_DMA_CACHE_RWFO
ldr r2, [r0] @ read for ownership
str r2, [r0] @ write for ownership
#endif
#ifdef HARVARD_CACHE
mcr p15, 0, r0, c7, c6, 1 @ invalidate D line
@ -234,7 +235,7 @@ v6_dma_inv_range:
v6_dma_clean_range:
bic r0, r0, #D_CACHE_LINE_SIZE - 1
1:
#ifdef CONFIG_SMP
#ifdef CONFIG_DMA_CACHE_RWFO
ldr r2, [r0] @ read for ownership
#endif
#ifdef HARVARD_CACHE
@ -257,7 +258,7 @@ v6_dma_clean_range:
ENTRY(v6_dma_flush_range)
bic r0, r0, #D_CACHE_LINE_SIZE - 1
1:
#ifdef CONFIG_SMP
#ifdef CONFIG_DMA_CACHE_RWFO
ldr r2, [r0] @ read for ownership
str r2, [r0] @ write for ownership
#endif
@ -283,9 +284,13 @@ ENTRY(v6_dma_map_area)
add r1, r1, r0
teq r2, #DMA_FROM_DEVICE
beq v6_dma_inv_range
#ifndef CONFIG_DMA_CACHE_RWFO
b v6_dma_clean_range
#else
teq r2, #DMA_TO_DEVICE
beq v6_dma_clean_range
b v6_dma_flush_range
#endif
ENDPROC(v6_dma_map_area)
/*
@ -295,6 +300,11 @@ ENDPROC(v6_dma_map_area)
* - dir - DMA direction
*/
ENTRY(v6_dma_unmap_area)
#ifndef CONFIG_DMA_CACHE_RWFO
add r1, r1, r0
teq r2, #DMA_TO_DEVICE
bne v6_dma_inv_range
#endif
mov pc, lr
ENDPROC(v6_dma_unmap_area)

4
arch/arm/mm/copypage-feroceon.c
View File

@ -18,7 +18,7 @@ feroceon_copy_user_page(void *kto, const void *kfrom)
{
asm("\
stmfd sp!, {r4-r9, lr} \n\
mov ip, %0 \n\
mov ip, %2 \n\
1: mov lr, r1 \n\
ldmia r1!, {r2 - r9} \n\
pld [lr, #32] \n\
@ -64,7 +64,7 @@ feroceon_copy_user_page(void *kto, const void *kfrom)
mcr p15, 0, ip, c7, c10, 4 @ drain WB\n\
ldmfd sp!, {r4-r9, pc}"
:
: "I" (PAGE_SIZE));
: "r" (kto), "r" (kfrom), "I" (PAGE_SIZE));
}
void feroceon_copy_user_highpage(struct page *to, struct page *from,

4
arch/arm/mm/copypage-v4wb.c
View File

@ -27,7 +27,7 @@ v4wb_copy_user_page(void *kto, const void *kfrom)
{
asm("\
stmfd sp!, {r4, lr} @ 2\n\
mov r2, %0 @ 1\n\
mov r2, %2 @ 1\n\
ldmia r1!, {r3, r4, ip, lr} @ 4\n\
1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
stmia r0!, {r3, r4, ip, lr} @ 4\n\
@ -44,7 +44,7 @@ v4wb_copy_user_page(void *kto, const void *kfrom)
mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB\n\
ldmfd sp!, {r4, pc} @ 3"
:
: "I" (PAGE_SIZE / 64));
: "r" (kto), "r" (kfrom), "I" (PAGE_SIZE / 64));
}
void v4wb_copy_user_highpage(struct page *to, struct page *from,

4
arch/arm/mm/copypage-v4wt.c
View File

@ -25,7 +25,7 @@ v4wt_copy_user_page(void *kto, const void *kfrom)
{
asm("\
stmfd sp!, {r4, lr} @ 2\n\
mov r2, %0 @ 1\n\
mov r2, %2 @ 1\n\
ldmia r1!, {r3, r4, ip, lr} @ 4\n\
1: stmia r0!, {r3, r4, ip, lr} @ 4\n\
ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\
@ -40,7 +40,7 @@ v4wt_copy_user_page(void *kto, const void *kfrom)
mcr p15, 0, r2, c7, c7, 0 @ flush ID cache\n\
ldmfd sp!, {r4, pc} @ 3"
:
: "I" (PAGE_SIZE / 64));
: "r" (kto), "r" (kfrom), "I" (PAGE_SIZE / 64));
}
void v4wt_copy_user_highpage(struct page *to, struct page *from,

4
arch/arm/mm/copypage-xsc3.c
View File

@ -34,7 +34,7 @@ xsc3_mc_copy_user_page(void *kto, const void *kfrom)
{
asm("\
stmfd sp!, {r4, r5, lr} \n\
mov lr, %0 \n\
mov lr, %2 \n\
\n\
pld [r1, #0] \n\
pld [r1, #32] \n\
@ -67,7 +67,7 @@ xsc3_mc_copy_user_page(void *kto, const void *kfrom)
\n\
ldmfd sp!, {r4, r5, pc}"
:
: "I" (PAGE_SIZE / 64 - 1));
: "r" (kto), "r" (kfrom), "I" (PAGE_SIZE / 64 - 1));
}
void xsc3_mc_copy_user_highpage(struct page *to, struct page *from,

18
arch/arm/mm/dma-mapping.c
View File

@ -24,15 +24,6 @@
#include <asm/tlbflush.h>
#include <asm/sizes.h>
/* Sanity check size */
#if (CONSISTENT_DMA_SIZE % SZ_2M)
#error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
#endif
#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
static u64 get_coherent_dma_mask(struct device *dev)
{
u64 mask = ISA_DMA_THRESHOLD;
@ -123,6 +114,15 @@ static void __dma_free_buffer(struct page *page, size_t size)
}
#ifdef CONFIG_MMU
/* Sanity check size */
#if (CONSISTENT_DMA_SIZE % SZ_2M)
#error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
#endif
#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
/*
* These are the page tables (2MB each) covering uncached, DMA consistent allocations
*/

3
arch/arm/mm/fault.c
View File

@ -393,6 +393,9 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
if (addr < TASK_SIZE)
return do_page_fault(addr, fsr, regs);
if (user_mode(regs))
goto bad_area;
index = pgd_index(addr);
/*

11
arch/arm/mm/highmem.c
View File

@ -48,7 +48,16 @@ void *kmap_atomic(struct page *page, enum km_type type)
debug_kmap_atomic(type);
kmap = kmap_high_get(page);
#ifdef CONFIG_DEBUG_HIGHMEM
/*
* There is no cache coherency issue when non VIVT, so force the
* dedicated kmap usage for better debugging purposes in that case.
*/
if (!cache_is_vivt())
kmap = NULL;
else
#endif
kmap = kmap_high_get(page);
if (kmap)
return kmap;

6
arch/arm/mm/init.c
View File

@ -678,10 +678,10 @@ void __init mem_init(void)
void free_initmem(void)
{
#ifdef CONFIG_HAVE_TCM
extern char *__tcm_start, *__tcm_end;
extern char __tcm_start, __tcm_end;
totalram_pages += free_area(__phys_to_pfn(__pa(__tcm_start)),
__phys_to_pfn(__pa(__tcm_end)),
totalram_pages += free_area(__phys_to_pfn(__pa(&__tcm_start)),
__phys_to_pfn(__pa(&__tcm_end)),
"TCM link");
#endif

26
arch/arm/plat-nomadik/timer.c
View File

@ -13,7 +13,9 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/jiffies.h>
#include <linux/err.h>
#include <asm/mach/time.h>
#include <plat/mtu.h>
@ -124,13 +126,25 @@ static struct irqaction nmdk_timer_irq = {
void __init nmdk_timer_init(void)
{
unsigned long rate;
u32 cr = MTU_CRn_32BITS;;
struct clk *clk0;
struct clk *clk1;
u32 cr;
clk0 = clk_get_sys("mtu0", NULL);
BUG_ON(IS_ERR(clk0));
clk1 = clk_get_sys("mtu1", NULL);
BUG_ON(IS_ERR(clk1));
clk_enable(clk0);
clk_enable(clk1);
/*
* Tick rate is 2.4MHz for Nomadik and 110MHz for ux500:
* use a divide-by-16 counter if it's more than 16MHz
*/
rate = CLOCK_TICK_RATE;
cr = MTU_CRn_32BITS;;
rate = clk_get_rate(clk0);
if (rate > 16 << 20) {
rate /= 16;
cr |= MTU_CRn_PRESCALE_16;
@ -153,6 +167,14 @@ void __init nmdk_timer_init(void)
nmdk_clksrc.name);
/* Timer 1 is used for events, fix according to rate */
cr = MTU_CRn_32BITS;
rate = clk_get_rate(clk1);
if (rate > 16 << 20) {
rate /= 16;
cr |= MTU_CRn_PRESCALE_16;
} else {
cr |= MTU_CRn_PRESCALE_1;
}
writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift);
nmdk_clkevt.max_delta_ns =

6
arch/arm/plat-omap/dmtimer.c
View File

@ -541,11 +541,11 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer)
* timer is stopped
*/
udelay(3500000 / clk_get_rate(timer->fclk) + 1);
/* Ack possibly pending interrupt */
omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
OMAP_TIMER_INT_OVERFLOW);
#endif
}
/* Ack possibly pending interrupt */
omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
OMAP_TIMER_INT_OVERFLOW);
}
EXPORT_SYMBOL_GPL(omap_dm_timer_stop);

1
arch/arm/plat-omap/gpio.c
View File

@ -673,6 +673,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
if (cpu_is_omap34xx() || cpu_is_omap44xx())
clk_disable(bank->dbck);
}
bank->dbck_enable_mask = val;
__raw_writel(val, reg);
}

4
arch/arm/plat-omap/iovmm.c
View File

@ -140,8 +140,10 @@ static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags)
return ERR_PTR(-ENOMEM);
err = sg_alloc_table(sgt, nr_entries, GFP_KERNEL);
if (err)
if (err) {
kfree(sgt);
return ERR_PTR(err);
}
pr_debug("%s: sgt:%p(%d entries)\n", __func__, sgt, nr_entries);

3
arch/arm/plat-pxa/Makefile
View File

@ -2,8 +2,9 @@
# Makefile for code common across different PXA processor families
#
obj-y := dma.o pmu.o
obj-y := dma.o
obj-$(CONFIG_ARCH_PXA) += pmu.o
obj-$(CONFIG_GENERIC_GPIO) += gpio.o
obj-$(CONFIG_PXA3xx) += mfp.o
obj-$(CONFIG_ARCH_MMP) += mfp.o

2
arch/arm/vfp/vfphw.S
View File

@ -277,7 +277,7 @@ ENTRY(vfp_put_double)
#ifdef CONFIG_VFPv3
@ d16 - d31 registers
.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1: mcrr p11, 3, r1, r2, c\dr @ fmdrr r1, r2, d\dr
1: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr
mov pc, lr
.org 1b + 8
.endr

20
arch/cris/arch-v10/drivers/ds1302.c
View File

@ -19,6 +19,7 @@
#include <linux/module.h>
#include <linux/miscdevice.h>
#include <linux/delay.h>
#include <linux/smp_lock.h>
#include <linux/bcd.h>
#include <linux/capability.h>
@ -238,9 +239,7 @@ static unsigned char days_in_mo[] =
/* ioctl that supports RTC_RD_TIME and RTC_SET_TIME (read and set time/date). */
static int
rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
unsigned long arg)
static int rtc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
unsigned long flags;
@ -354,6 +353,17 @@ rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
}
}
static long rtc_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
int ret;
lock_kernel();
ret = rtc_ioctl(file, cmd, arg);
unlock_kernel();
return ret;
}
static void
print_rtc_status(void)
{
@ -375,8 +385,8 @@ print_rtc_status(void)
/* The various file operations we support. */
static const struct file_operations rtc_fops = {
.owner = THIS_MODULE,
.ioctl = rtc_ioctl,
.owner = THIS_MODULE,
.unlocked_ioctl = rtc_unlocked_ioctl,
};
/* Probe for the chip by writing something to its RAM and try reading it back. */

19
arch/cris/arch-v10/drivers/pcf8563.c
View File

@ -27,6 +27,7 @@
#include <linux/delay.h>
#include <linux/bcd.h>
#include <linux/mutex.h>
#include <linux/smp_lock.h>
#include <asm/uaccess.h>
#include <asm/system.h>
@ -53,7 +54,7 @@ static DEFINE_MUTEX(rtc_lock); /* Protect state etc */
static const unsigned char days_in_month[] =
{ 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
static long pcf8563_unlocked_ioctl(struct file *, unsigned int, unsigned long);
/* Cache VL bit value read at driver init since writing the RTC_SECOND
* register clears the VL status.
@ -62,7 +63,7 @@ static int voltage_low;
static const struct file_operations pcf8563_fops = {
.owner = THIS_MODULE,
.ioctl = pcf8563_ioctl,
.unlocked_ioctl = pcf8563_unlocked_ioctl,
};
unsigned char
@ -212,8 +213,7 @@ pcf8563_exit(void)
* ioctl calls for this driver. Why return -ENOTTY upon error? Because
* POSIX says so!
*/
int pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
unsigned long arg)
static int pcf8563_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
/* Some sanity checks. */
if (_IOC_TYPE(cmd) != RTC_MAGIC)
@ -339,6 +339,17 @@ int pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
return 0;
}
static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
int ret;
lock_kernel();
return pcf8563_ioctl(filp, cmd, arg);
unlock_kernel();
return ret;
}
static int __init pcf8563_register(void)
{
if (pcf8563_init() < 0) {

8
arch/cris/arch-v10/kernel/irq.c
View File

@ -17,8 +17,8 @@
#include <linux/kernel.h>
#include <linux/init.h>
#define mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));
#define unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));
#define crisv10_mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));
#define crisv10_unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));
/* don't use set_int_vector, it bypasses the linux interrupt handlers. it is
* global just so that the kernel gdb can use it.
@ -116,12 +116,12 @@ static unsigned int startup_crisv10_irq(unsigned int irq)
static void enable_crisv10_irq(unsigned int irq)
{
unmask_irq(irq);
crisv10_unmask_irq(irq);
}
static void disable_crisv10_irq(unsigned int irq)
{
mask_irq(irq);
crisv10_mask_irq(irq);
}
static void ack_crisv10_irq(unsigned int irq)

15
arch/cris/arch-v10/lib/dmacopy.c
View File

@ -1,5 +1,4 @@
/* $Id: dmacopy.c,v 1.1 2001/12/17 13:59:27 bjornw Exp $
*
/*
* memcpy for large blocks, using memory-memory DMA channels 6 and 7 in Etrax
*/
@ -13,11 +12,11 @@ void *dma_memcpy(void *pdst,
unsigned int pn)
{
static etrax_dma_descr indma, outdma;
D(printk("dma_memcpy %d bytes... ", pn));
D(printk(KERN_DEBUG "dma_memcpy %d bytes... ", pn));
#if 0
*R_GEN_CONFIG = genconfig_shadow =
*R_GEN_CONFIG = genconfig_shadow =
(genconfig_shadow & ~0x3c0000) |
IO_STATE(R_GEN_CONFIG, dma6, intdma7) |
IO_STATE(R_GEN_CONFIG, dma7, intdma6);
@ -32,11 +31,11 @@ void *dma_memcpy(void *pdst,
*R_DMA_CH7_FIRST = &outdma;
*R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, start);
*R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, start);
while(*R_DMA_CH7_CMD == 1) /* wait for completion */ ;
D(printk("done\n"));
while (*R_DMA_CH7_CMD == 1)
/* wait for completion */;
D(printk(KERN_DEBUG "done\n"));
}

14
arch/cris/arch-v10/lib/hw_settings.S
View File

@ -1,13 +1,11 @@
/*
* $Id: hw_settings.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
*
* This table is used by some tools to extract hardware parameters.
* The table should be included in the kernel and the decompressor.
* Don't forget to update the tools if you change this table.
*
* Copyright (C) 2001 Axis Communications AB
*
* Authors: Mikael Starvik (starvik@axis.com)
* Authors: Mikael Starvik (starvik@axis.com)
*/
#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \
@ -15,13 +13,13 @@
#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \
(CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \
(CONFIG_ETRAX_DEF_R_PORT_PB_DATA))
.ascii "HW_PARAM_MAGIC" ; Magic number
.dword 0xc0004000 ; Kernel start address
; Debug port
#ifdef CONFIG_ETRAX_DEBUG_PORT0
.dword 0
.dword 0
#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
.dword 1
#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
@ -30,7 +28,7 @@
.dword 3
#else
.dword 4 ; No debug
#endif
#endif
; SDRAM or EDO DRAM?
#ifdef CONFIG_ETRAX_SDRAM
@ -39,7 +37,7 @@
.dword 0
#endif
; Register values
; Register values
.dword R_WAITSTATES
.dword CONFIG_ETRAX_DEF_R_WAITSTATES
.dword R_BUS_CONFIG
@ -56,7 +54,7 @@
.dword CONFIG_ETRAX_DEF_R_DRAM_TIMING
#endif
.dword R_PORT_PA_SET
.dword PA_SET_VALUE
.dword PA_SET_VALUE
.dword R_PORT_PB_SET
.dword PB_SET_VALUE
.dword 0 ; No more register values

16
arch/cris/arch-v32/drivers/Kconfig
View File

@ -360,24 +360,10 @@ config ETRAX_SER4_DSR_BIT
string "Ser 4 DSR bit (empty = not used)"
depends on ETRAX_SERIAL_PORT4
config ETRAX_SER3_CD_BIT
config ETRAX_SER4_CD_BIT
string "Ser 4 CD bit (empty = not used)"
depends on ETRAX_SERIAL_PORT4
config ETRAX_RS485
bool "RS-485 support"
depends on ETRAXFS_SERIAL
help
Enables support for RS-485 serial communication. For a primer on
RS-485, see <http://www.hw.cz/english/docs/rs485/rs485.html>.
config ETRAX_RS485_DISABLE_RECEIVER
bool "Disable serial receiver"
depends on ETRAX_RS485
help
It is necessary to disable the serial receiver to avoid serial
loopback. Not all products are able to do this in software only.
config ETRAX_SYNCHRONOUS_SERIAL
bool "Synchronous serial-port support"
depends on ETRAX_ARCH_V32

22
arch/cris/arch-v32/drivers/i2c.c
View File

@ -649,10 +649,10 @@ i2c_release(struct inode *inode, struct file *filp)
/* Main device API. ioctl's to write or read to/from i2c registers.
*/
static int
i2c_ioctl(struct inode *inode, struct file *file,
unsigned int cmd, unsigned long arg)
static long
i2c_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
int ret;
if(_IOC_TYPE(cmd) != ETRAXI2C_IOCTYPE) {
return -ENOTTY;
}
@ -665,9 +665,13 @@ i2c_ioctl(struct inode *inode, struct file *file,
I2C_ARGREG(arg),
I2C_ARGVALUE(arg)));
return i2c_writereg(I2C_ARGSLAVE(arg),
lock_kernel();
ret = i2c_writereg(I2C_ARGSLAVE(arg),
I2C_ARGREG(arg),
I2C_ARGVALUE(arg));
unlock_kernel();
return ret;
case I2C_READREG:
{
unsigned char val;
@ -675,7 +679,9 @@ i2c_ioctl(struct inode *inode, struct file *file,
D(printk("i2cr %d %d ",
I2C_ARGSLAVE(arg),
I2C_ARGREG(arg)));
lock_kernel();
val = i2c_readreg(I2C_ARGSLAVE(arg), I2C_ARGREG(arg));
unlock_kernel();
D(printk("= %d\n", val));
return val;
}
@ -688,10 +694,10 @@ i2c_ioctl(struct inode *inode, struct file *file,
}
static const struct file_operations i2c_fops = {
.owner = THIS_MODULE,
.ioctl = i2c_ioctl,
.open = i2c_open,
.release = i2c_release,
.owner = THIS_MODULE,
.unlocked_ioctl = i2c_ioctl,
.open = i2c_open,
.release = i2c_release,
};
static int __init i2c_init(void)

21
arch/cris/arch-v32/drivers/pcf8563.c
View File

@ -24,6 +24,7 @@
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/ioctl.h>
#include <linux/smp_lock.h>
#include <linux/delay.h>
#include <linux/bcd.h>
#include <linux/mutex.h>
@ -49,7 +50,7 @@ static DEFINE_MUTEX(rtc_lock); /* Protect state etc */
static const unsigned char days_in_month[] =
{ 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
/* Cache VL bit value read at driver init since writing the RTC_SECOND
* register clears the VL status.
@ -57,8 +58,8 @@ int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
static int voltage_low;
static const struct file_operations pcf8563_fops = {
.owner = THIS_MODULE,
.ioctl = pcf8563_ioctl
.owner = THIS_MODULE,
.unlocked_ioctl = pcf8563_unlocked_ioctl,
};
unsigned char
@ -208,8 +209,7 @@ pcf8563_exit(void)
* ioctl calls for this driver. Why return -ENOTTY upon error? Because
* POSIX says so!
*/
int pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
unsigned long arg)
static int pcf8563_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
/* Some sanity checks. */
if (_IOC_TYPE(cmd) != RTC_MAGIC)
@ -335,6 +335,17 @@ int pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
return 0;
}
static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
int ret;
lock_kernel();
return pcf8563_ioctl(filp, cmd, arg);
unlock_kernel();
return ret;
}
static int __init pcf8563_register(void)
{
if (pcf8563_init() < 0) {

4
arch/cris/arch-v32/kernel/crisksyms.c
View File

@ -24,5 +24,5 @@ EXPORT_SYMBOL(crisv32_io_get_name);
EXPORT_SYMBOL(crisv32_io_get);
/* Functions masking/unmasking interrupts */
EXPORT_SYMBOL(mask_irq);
EXPORT_SYMBOL(unmask_irq);
EXPORT_SYMBOL(crisv32_mask_irq);
EXPORT_SYMBOL(crisv32_unmask_irq);

14
arch/cris/arch-v32/kernel/irq.c
View File

@ -280,8 +280,7 @@ out:
return cpu;
}
void
mask_irq(int irq)
void crisv32_mask_irq(int irq)
{
int cpu;
@ -289,8 +288,7 @@ mask_irq(int irq)
block_irq(irq, cpu);
}
void
unmask_irq(int irq)
void crisv32_unmask_irq(int irq)
{
unblock_irq(irq, irq_cpu(irq));
}
@ -298,23 +296,23 @@ unmask_irq(int irq)
static unsigned int startup_crisv32_irq(unsigned int irq)
{
unmask_irq(irq);
crisv32_unmask_irq(irq);
return 0;
}
static void shutdown_crisv32_irq(unsigned int irq)
{
mask_irq(irq);
crisv32_mask_irq(irq);
}
static void enable_crisv32_irq(unsigned int irq)
{
unmask_irq(irq);
crisv32_unmask_irq(irq);
}
static void disable_crisv32_irq(unsigned int irq)
{
mask_irq(irq);
crisv32_mask_irq(irq);
}
static void ack_crisv32_irq(unsigned int irq)

4
arch/cris/arch-v32/kernel/smp.c
View File

@ -168,8 +168,8 @@ void __init smp_callin(void)
/* Enable IRQ and idle */
REG_WR(intr_vect, irq_regs[cpu], rw_mask, vect_mask);
unmask_irq(IPI_INTR_VECT);
unmask_irq(TIMER0_INTR_VECT);
crisv32_unmask_irq(IPI_INTR_VECT);
crisv32_unmask_irq(TIMER0_INTR_VECT);
preempt_disable();
notify_cpu_starting(cpu);
local_irq_enable();

9
arch/cris/include/arch-v10/arch/irq.h
View File

@ -93,15 +93,16 @@ void set_break_vector(int n, irqvectptr addr);
"push $r10\n\t" /* push orig_r10 */ \
"clear.d [$sp=$sp-4]\n\t" /* frametype - this is a normal stackframe */
/* BLOCK_IRQ and UNBLOCK_IRQ do the same as mask_irq and unmask_irq */
/* BLOCK_IRQ and UNBLOCK_IRQ do the same as
* crisv10_mask_irq and crisv10_unmask_irq */
#define BLOCK_IRQ(mask,nr) \
"move.d " #mask ",$r0\n\t" \
"move.d $r0,[0xb00000d8]\n\t"
"move.d $r0,[0xb00000d8]\n\t"
#define UNBLOCK_IRQ(mask) \
"move.d " #mask ",$r0\n\t" \
"move.d $r0,[0xb00000dc]\n\t"
"move.d $r0,[0xb00000dc]\n\t"
#define IRQ_NAME2(nr) nr##_interrupt(void)
#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)

4
arch/cris/include/arch-v32/arch/irq.h
View File

@ -23,8 +23,8 @@ struct etrax_interrupt_vector {
extern struct etrax_interrupt_vector *etrax_irv; /* head.S */
void mask_irq(int irq);
void unmask_irq(int irq);
void crisv32_mask_irq(int irq);
void crisv32_unmask_irq(int irq);
void set_exception_vector(int n, irqvectptr addr);

17
arch/cris/include/asm/param.h
View File

@ -2,22 +2,9 @@
#define _ASMCRIS_PARAM_H
/* Currently we assume that HZ=100 is good for CRIS. */
#ifdef __KERNEL__
# define HZ CONFIG_HZ /* Internal kernel timer frequency */
# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
#endif
#ifndef HZ
#define HZ 100
#endif
#define EXEC_PAGESIZE 8192
#ifndef NOGROUP
#define NOGROUP (-1)
#endif
#include <asm-generic/param.h>
#define MAXHOSTNAMELEN 64 /* max length of hostname */
#endif
#endif /* _ASMCRIS_PARAM_H */

4
arch/frv/kernel/break.S
View File

@ -21,7 +21,7 @@
#
# the break handler has its own stack
#
.section .bss.stack
.section .bss..stack
.globl __break_user_context
.balign THREAD_SIZE
__break_stack:
@ -63,7 +63,7 @@ __break_trace_through_exceptions:
# entry point for Break Exceptions/Interrupts
#
###############################################################################
.section .text.break
.section .text..break
.balign 4
.globl __entry_break
__entry_break:

2
arch/frv/kernel/entry.S
View File

@ -38,7 +38,7 @@
#define nr_syscalls ((syscall_table_size)/4)
.section .text.entry
.section .text..entry
.balign 4
.macro LEDS val

6
arch/frv/kernel/gdb-stub.c
View File

@ -1789,6 +1789,12 @@ void gdbstub(int sigval)
flush_cache = 1;
break;
/* pNN: Read value of reg N and return it */
case 'p':
/* return no value, indicating that we don't support
* this command and that gdb should use 'g' instead */
break;
/* PNN,=RRRRRRRR: Write value R to reg N return OK */
case 'P':
ptr = &input_buffer[1];

2
arch/frv/kernel/head.S
View File

@ -542,7 +542,7 @@ __head_end:
.size _boot, .-_boot
# provide a point for GDB to place a break
.section .text.start,"ax"
.section .text..start,"ax"
.globl _start
.balign 4
_start:

10
arch/frv/kernel/vmlinux.lds.S
View File

@ -57,10 +57,10 @@ SECTIONS
_text = .;
_stext = .;
.text : {
*(.text.start)
*(.text.entry)
*(.text.break)
*(.text.tlbmiss)
*(.text..start)
*(.text..entry)
*(.text..break)
*(.text..tlbmiss)
TEXT_TEXT
SCHED_TEXT
LOCK_TEXT
@ -114,7 +114,7 @@ SECTIONS
.sbss : { *(.sbss .sbss.*) }
.bss : { *(.bss .bss.*) }
.bss.stack : { *(.bss) }
.bss..stack : { *(.bss) }
__bss_stop = .;
_end = . ;

8
arch/frv/mm/fault.c
View File

@ -257,10 +257,10 @@ asmlinkage void do_page_fault(int datammu, unsigned long esr0, unsigned long ear
*/
out_of_memory:
up_read(&mm->mmap_sem);
printk("VM: killing process %s\n", current->comm);
if (user_mode(__frame))
do_group_exit(SIGKILL);
goto no_context;
if (!user_mode(__frame))
goto no_context;
pagefault_out_of_memory();
return;
do_sigbus:
up_read(&mm->mmap_sem);

2
arch/frv/mm/tlb-miss.S
View File

@ -15,7 +15,7 @@
#include <asm/pgtable.h>
#include <asm/spr-regs.h>
.section .text.tlbmiss
.section .text..tlbmiss
.balign 4
.globl __entry_insn_mmu_miss

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