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x86/fpu: Avoid writing LBR bit to IA32_XSS unless supported
There are two distinct CPU features related to the use of XSAVES and LBR:
whether LBR is itself supported and whether XSAVES supports LBR. The LBR
subsystem correctly checks both in intel_pmu_arch_lbr_init(), but the
XSTATE subsystem does not.
The LBR bit is only removed from xfeatures_mask_independent when LBR is not
supported by the CPU, but there is no validation of XSTATE support.
If XSAVES does not support LBR the write to IA32_XSS causes a #GP fault,
leaving the state of IA32_XSS unchanged, i.e. zero. The fault is handled
with a warning and the boot continues.
Consequently the next XRSTORS which tries to restore supervisor state fails
with #GP because the RFBM has zero for all supervisor features, which does
not match the XCOMP_BV field.
As XFEATURE_MASK_FPSTATE includes supervisor features setting up the FPU
causes a #GP, which ends up in fpu_reset_from_exception_fixup(). That fails
due to the same problem resulting in recursive #GPs until the kernel runs
out of stack space and double faults.
Prevent this by storing the supported independent features in
fpu_kernel_cfg during XSTATE initialization and use that cached value for
retrieving the independent feature bits to be written into IA32_XSS.
[ tglx: Massaged change log ]
Fixes: f0dccc9da4
("x86/fpu/xstate: Support dynamic supervisor feature for LBR")
Suggested-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Mitchell Levy <levymitchell0@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/all/20240812-xsave-lbr-fix-v3-1-95bac1bf62f4@gmail.com
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@ -591,6 +591,13 @@ struct fpu_state_config {
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* even without XSAVE support, i.e. legacy features FP + SSE
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*/
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u64 legacy_features;
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/*
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* @independent_features:
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*
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* Features that are supported by XSAVES, but not managed as part of
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* the FPU core, such as LBR
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*/
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u64 independent_features;
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};
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/* FPU state configuration information */
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@ -788,6 +788,9 @@ void __init fpu__init_system_xstate(unsigned int legacy_size)
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goto out_disable;
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}
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fpu_kernel_cfg.independent_features = fpu_kernel_cfg.max_features &
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XFEATURE_MASK_INDEPENDENT;
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/*
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* Clear XSAVE features that are disabled in the normal CPUID.
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*/
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@ -62,9 +62,9 @@ static inline u64 xfeatures_mask_supervisor(void)
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static inline u64 xfeatures_mask_independent(void)
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{
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if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR))
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return XFEATURE_MASK_INDEPENDENT & ~XFEATURE_MASK_LBR;
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return fpu_kernel_cfg.independent_features & ~XFEATURE_MASK_LBR;
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return XFEATURE_MASK_INDEPENDENT;
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return fpu_kernel_cfg.independent_features;
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}
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/* XSAVE/XRSTOR wrapper functions */
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