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media: renesas: vsp1: Add new formats (2-10-10-10 ARGB, Y210, Y212)

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Add new pixel formats: RGBX1010102, RGBA1010102, ARGB2101010, Y210 and
Y212.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This commit is contained in:
Tomi Valkeinen 2022-12-21 11:24:46 +02:00 committed by Laurent Pinchart
parent e0106bd776
commit 2768fbf100
3 changed files with 93 additions and 0 deletions
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18
drivers/media/platform/renesas/vsp1/vsp1_pipe.c
View File

@ -146,6 +146,18 @@ static const struct vsp1_format_info vsp1_video_formats[] = {
VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
1, { 32, 0, 0 }, false, false, 1, 1, false },
{ V4L2_PIX_FMT_RGBX1010102, MEDIA_BUS_FMT_ARGB8888_1X32,
VI6_FMT_RGB10_RGB10A2_A2RGB10,
VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
1, { 32, 0, 0 }, false, false, 1, 1, false },
{ V4L2_PIX_FMT_RGBA1010102, MEDIA_BUS_FMT_ARGB8888_1X32,
VI6_FMT_RGB10_RGB10A2_A2RGB10,
VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
1, { 32, 0, 0 }, false, false, 1, 1, false },
{ V4L2_PIX_FMT_ARGB2101010, MEDIA_BUS_FMT_ARGB8888_1X32,
VI6_FMT_RGB10_RGB10A2_A2RGB10,
VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
1, { 32, 0, 0 }, false, false, 1, 1, false },
{ V4L2_PIX_FMT_UYVY, MEDIA_BUS_FMT_AYUV8_1X32,
VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
@ -202,6 +214,12 @@ static const struct vsp1_format_info vsp1_video_formats[] = {
VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
3, { 8, 8, 8 }, false, true, 1, 1, false },
{ V4L2_PIX_FMT_Y210, MEDIA_BUS_FMT_AYUV8_1X32,
VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
1, { 32, 0, 0 }, false, false, 2, 1, false },
{ V4L2_PIX_FMT_Y212, MEDIA_BUS_FMT_AYUV8_1X32,
VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
1, { 32, 0, 0 }, false, false, 2, 1, false },
};
/**

23
drivers/media/platform/renesas/vsp1/vsp1_regs.h
View File

@ -228,6 +228,28 @@
#define VI6_RPF_MULT_ALPHA_RATIO_MASK (0xff << 0)
#define VI6_RPF_MULT_ALPHA_RATIO_SHIFT 0
#define VI6_RPF_EXT_INFMT0 0x0370
#define VI6_RPF_EXT_INFMT0_F2B BIT(12)
#define VI6_RPF_EXT_INFMT0_IPBD_Y_8 (0 << 8)
#define VI6_RPF_EXT_INFMT0_IPBD_Y_10 (1 << 8)
#define VI6_RPF_EXT_INFMT0_IPBD_Y_12 (2 << 8)
#define VI6_RPF_EXT_INFMT0_IPBD_C_8 (0 << 4)
#define VI6_RPF_EXT_INFMT0_IPBD_C_10 (1 << 4)
#define VI6_RPF_EXT_INFMT0_IPBD_C_12 (2 << 4)
#define VI6_RPF_EXT_INFMT0_BYPP_M1_RGB10 (3 << 0)
#define VI6_RPF_EXT_INFMT1 0x0374
#define VI6_RPF_EXT_INFMT1_PACK_CPOS(a, b, c, d) \
(((a) << 24) | ((b) << 16) | ((c) << 8) | ((d) << 0))
#define VI6_RPF_EXT_INFMT2 0x0378
#define VI6_RPF_EXT_INFMT2_PACK_CLEN(a, b, c, d) \
(((a) << 24) | ((b) << 16) | ((c) << 8) | ((d) << 0))
#define VI6_RPF_BRDITH_CTRL 0x03e0
#define VI6_RPF_BRDITH_CTRL_ODE BIT(8)
#define VI6_RPF_BRDITH_CTRL_CBRM BIT(0)
/* -----------------------------------------------------------------------------
* WPF Control Registers
*/
@ -846,6 +868,7 @@
#define VI6_FMT_XBXGXR_262626 0x21
#define VI6_FMT_ABGR_8888 0x22
#define VI6_FMT_XXRGB_88565 0x23
#define VI6_FMT_RGB10_RGB10A2_A2RGB10 0x30
#define VI6_FMT_Y_UV_444 0x40
#define VI6_FMT_Y_UV_422 0x41

52
drivers/media/platform/renesas/vsp1/vsp1_rpf.c
View File

@ -109,6 +109,58 @@ static void rpf_configure_stream(struct vsp1_entity *entity,
vsp1_rpf_write(rpf, dlb, VI6_RPF_INFMT, infmt);
vsp1_rpf_write(rpf, dlb, VI6_RPF_DSWAP, fmtinfo->swap);
if (entity->vsp1->info->gen == 4) {
u32 ext_infmt0;
u32 ext_infmt1;
u32 ext_infmt2;
switch (fmtinfo->fourcc) {
case V4L2_PIX_FMT_RGBX1010102:
ext_infmt0 = VI6_RPF_EXT_INFMT0_BYPP_M1_RGB10;
ext_infmt1 = VI6_RPF_EXT_INFMT1_PACK_CPOS(0, 10, 20, 0);
ext_infmt2 = VI6_RPF_EXT_INFMT2_PACK_CLEN(10, 10, 10, 0);
break;
case V4L2_PIX_FMT_RGBA1010102:
ext_infmt0 = VI6_RPF_EXT_INFMT0_BYPP_M1_RGB10;
ext_infmt1 = VI6_RPF_EXT_INFMT1_PACK_CPOS(0, 10, 20, 30);
ext_infmt2 = VI6_RPF_EXT_INFMT2_PACK_CLEN(10, 10, 10, 2);
break;
case V4L2_PIX_FMT_ARGB2101010:
ext_infmt0 = VI6_RPF_EXT_INFMT0_BYPP_M1_RGB10;
ext_infmt1 = VI6_RPF_EXT_INFMT1_PACK_CPOS(2, 12, 22, 0);
ext_infmt2 = VI6_RPF_EXT_INFMT2_PACK_CLEN(10, 10, 10, 2);
break;
case V4L2_PIX_FMT_Y210:
ext_infmt0 = VI6_RPF_EXT_INFMT0_F2B |
VI6_RPF_EXT_INFMT0_IPBD_Y_10 |
VI6_RPF_EXT_INFMT0_IPBD_C_10;
ext_infmt1 = 0x0;
ext_infmt2 = 0x0;
break;
case V4L2_PIX_FMT_Y212:
ext_infmt0 = VI6_RPF_EXT_INFMT0_F2B |
VI6_RPF_EXT_INFMT0_IPBD_Y_12 |
VI6_RPF_EXT_INFMT0_IPBD_C_12;
ext_infmt1 = 0x0;
ext_infmt2 = 0x0;
break;
default:
ext_infmt0 = 0;
ext_infmt1 = 0;
ext_infmt2 = 0;
break;
}
vsp1_rpf_write(rpf, dlb, VI6_RPF_EXT_INFMT0, ext_infmt0);
vsp1_rpf_write(rpf, dlb, VI6_RPF_EXT_INFMT1, ext_infmt1);
vsp1_rpf_write(rpf, dlb, VI6_RPF_EXT_INFMT2, ext_infmt2);
}
/* Output location. */
if (pipe->brx) {
const struct v4l2_rect *compose;