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[PATCH] x86-64: wakeup.S misc cleanups
o Various cleanups. One of the main purpose of cleanups is that make wakeup.S as close as possible to trampoline.S. o Following are the changes - Indentations for comments. - Changed the gdt table to compact form and to resemble the one in trampoline.S - Take the jump to 32bit from real mode using ljmpl. Makes code more readable. - After enabling long mode, directly take a long jump for 64bit mode. No need to take an extra jump to "reach_comaptibility_mode" - Stack is not used after real mode. So don't load stack in 32 bit mode. - No need to enable PGE here. - No need to do extra EFER read, anyway we trash the read contents. - No need to enable system call (EFER_SCE). Anyway it will be enabled when original EFER is restored. - No need to set MP, ET, NE, WP, AM bits in cr0. Very soon we will reload the original cr0 while restroing the processor state. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Signed-off-by: Vivek Goyal <vgoyal@in.ibm.com> Signed-off-by: Andi Kleen <ak@suse.de>
This commit is contained in:
Vivek Goyal
Andi Kleen
parent
7db681d7e4
commit
275f55170e
@ -30,11 +30,12 @@ wakeup_code:
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cld
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# setup data segment
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movw %cs, %ax
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movw %ax, %ds # Make ds:0 point to wakeup_start
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movw %ax, %ds # Make ds:0 point to wakeup_start
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movw %ax, %ss
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mov $(wakeup_stack - wakeup_code), %sp # Private stack is needed for ASUS board
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# Private stack is needed for ASUS board
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mov $(wakeup_stack - wakeup_code), %sp
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pushl $0 # Kill any dangerous flags
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pushl $0 # Kill any dangerous flags
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popfl
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movl real_magic - wakeup_code, %eax
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@ -45,7 +46,7 @@ wakeup_code:
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jz 1f
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lcall $0xc000,$3
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movw %cs, %ax
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movw %ax, %ds # Bios might have played with that
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movw %ax, %ds # Bios might have played with that
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movw %ax, %ss
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1:
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@ -75,9 +76,12 @@ wakeup_code:
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jmp 1f
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1:
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.byte 0x66, 0xea # prefix + jmpi-opcode
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.long wakeup_32 - __START_KERNEL_map
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.word __KERNEL_CS
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ljmpl *(wakeup_32_vector - wakeup_code)
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.balign 4
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wakeup_32_vector:
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.long wakeup_32 - __START_KERNEL_map
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.word __KERNEL32_CS, 0
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.code32
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wakeup_32:
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@ -96,65 +100,50 @@ wakeup_32:
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jnc bogus_cpu
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movl %edx,%edi
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movw $__KERNEL_DS, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %fs
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movw %ax, %gs
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movl $__KERNEL_DS, %eax
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movl %eax, %ds
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movw $__KERNEL_DS, %ax
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movw %ax, %ss
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mov $(wakeup_stack - __START_KERNEL_map), %esp
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movl saved_magic - __START_KERNEL_map, %eax
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cmpl $0x9abcdef0, %eax
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jne bogus_32_magic
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movw $0x0e00 + 'i', %ds:(0xb8012)
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movb $0xa8, %al ; outb %al, $0x80;
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/*
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* Prepare for entering 64bits mode
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*/
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/* Enable PAE mode and PGE */
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/* Enable PAE */
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xorl %eax, %eax
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btsl $5, %eax
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btsl $7, %eax
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movl %eax, %cr4
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/* Setup early boot stage 4 level pagetables */
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movl $(wakeup_level4_pgt - __START_KERNEL_map), %eax
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movl %eax, %cr3
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/* Setup EFER (Extended Feature Enable Register) */
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movl $MSR_EFER, %ecx
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rdmsr
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/* Fool rdmsr and reset %eax to avoid dependences */
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xorl %eax, %eax
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/* Enable Long Mode */
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xorl %eax, %eax
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btsl $_EFER_LME, %eax
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/* Enable System Call */
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btsl $_EFER_SCE, %eax
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/* No Execute supported? */
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btl $20,%edi
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jnc 1f
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btsl $_EFER_NX, %eax
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1:
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/* Make changes effective */
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1: movl $MSR_EFER, %ecx
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xorl %edx, %edx
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wrmsr
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wbinvd
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xorl %eax, %eax
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btsl $31, %eax /* Enable paging and in turn activate Long Mode */
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btsl $0, %eax /* Enable protected mode */
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btsl $1, %eax /* Enable MP */
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btsl $4, %eax /* Enable ET */
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btsl $5, %eax /* Enable NE */
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btsl $16, %eax /* Enable WP */
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btsl $18, %eax /* Enable AM */
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/* Make changes effective */
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movl %eax, %cr0
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/* At this point:
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CR4.PAE must be 1
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CS.L must be 0
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@ -162,11 +151,6 @@ wakeup_32:
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Next instruction must be a branch
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This must be on identity-mapped page
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*/
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jmp reach_compatibility_mode
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reach_compatibility_mode:
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movw $0x0e00 + 'i', %ds:(0xb8012)
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movb $0xa8, %al ; outb %al, $0x80;
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/*
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* At this point we're in long mode but in 32bit compatibility mode
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* with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn
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@ -174,24 +158,19 @@ reach_compatibility_mode:
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* the new gdt/idt that has __KERNEL_CS with CS.L = 1.
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*/
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movw $0x0e00 + 'n', %ds:(0xb8014)
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movb $0xa9, %al ; outb %al, $0x80
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/* Load new GDT with the 64bit segment using 32bit descriptor */
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movl $(pGDT32 - __START_KERNEL_map), %eax
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lgdt (%eax)
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movl $(wakeup_jumpvector - __START_KERNEL_map), %eax
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/* Finally jump in 64bit mode */
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ljmp *(%eax)
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ljmp *(wakeup_long64_vector - __START_KERNEL_map)
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wakeup_jumpvector:
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.long wakeup_long64 - __START_KERNEL_map
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.word __KERNEL_CS
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.balign 4
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wakeup_long64_vector:
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.long wakeup_long64 - __START_KERNEL_map
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.word __KERNEL_CS, 0
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.code64
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/* Hooray, we are in Long 64-bit mode (but still running in low memory) */
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/* Hooray, we are in Long 64-bit mode (but still running in
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* low memory)
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*/
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wakeup_long64:
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/*
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* We must switch to a new descriptor in kernel space for the GDT
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@ -201,6 +180,9 @@ wakeup_long64:
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*/
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lgdt cpu_gdt_descr - __START_KERNEL_map
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movw $0x0e00 + 'n', %ds:(0xb8014)
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movb $0xa9, %al ; outb %al, $0x80
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movw $0x0e00 + 'u', %ds:(0xb8016)
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nop
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@ -227,33 +209,19 @@ wakeup_long64:
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.align 64
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gdta:
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/* Its good to keep gdt in sync with one in trampoline.S */
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.word 0, 0, 0, 0 # dummy
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.word 0, 0, 0, 0 # unused
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.word 0xFFFF # 4Gb - (0x100000*0x1000 = 4Gb)
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.word 0 # base address = 0
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.word 0x9B00 # code read/exec. ??? Why I need 0x9B00 (as opposed to 0x9A00 in order for this to work?)
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.word 0x00CF # granularity = 4096, 386
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# (+5th nibble of limit)
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.word 0xFFFF # 4Gb - (0x100000*0x1000 = 4Gb)
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.word 0 # base address = 0
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.word 0x9200 # data read/write
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.word 0x00CF # granularity = 4096, 386
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# (+5th nibble of limit)
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# this is 64bit descriptor for code
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.word 0xFFFF
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.word 0
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.word 0x9A00 # code read/exec
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.word 0x00AF # as above, but it is long mode and with D=0
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/* ??? Why I need the accessed bit set in order for this to work? */
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.quad 0x00cf9b000000ffff # __KERNEL32_CS
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.quad 0x00af9b000000ffff # __KERNEL_CS
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.quad 0x00cf93000000ffff # __KERNEL_DS
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idt_48a:
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.word 0 # idt limit = 0
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.word 0, 0 # idt base = 0L
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gdt_48a:
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.word 0x8000 # gdt limit=2048,
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.word 0x800 # gdt limit=2048,
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# 256 GDT entries
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.word 0, 0 # gdt base (filled in later)
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