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accel/habanalabs: change Greco to Gaudi2
Greco was not upstreamed so no point of mentioning it here. Signed-off-by: Oded Gabbay <ogabbay@kernel.org> Reviewed-by: Ofir Bitton <obitton@habana.ai>
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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*
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* Copyright 2016-2022 HabanaLabs, Ltd.
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* Copyright 2016-2023 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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@ -885,11 +885,11 @@ enum hl_server_type {
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* @dram_enabled: Whether the DRAM is enabled.
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* @security_enabled: Whether security is enabled on device.
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* @mme_master_slave_mode: Indicate whether the MME is working in master/slave
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* configuration. Relevant for Greco and later.
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* configuration. Relevant for Gaudi2 and later.
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* @cpucp_version: The CPUCP f/w version.
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* @card_name: The card name as passed by the f/w.
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* @tpc_enabled_mask_ext: Bit-mask that represents which TPCs are enabled.
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* Relevant for Greco and later.
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* Relevant for Gaudi2 and later.
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* @dram_page_size: The DRAM physical page size.
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* @edma_enabled_mask: Bit-mask that represents which EDMAs are enabled.
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* Relevant for Gaudi2 and later.
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@ -1425,7 +1425,7 @@ union hl_cb_args {
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*
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* HL_CS_CHUNK_FLAGS_USER_ALLOC_CB:
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* Indicates if the CB was allocated and mapped by userspace
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* (relevant to greco and above). User allocated CB is a command buffer,
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* (relevant to Gaudi2 and later). User allocated CB is a command buffer,
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* allocated by the user, via malloc (or similar). After allocating the
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* CB, the user invokes - “memory ioctl” to map the user memory into a
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* device virtual address. The user provides this address via the
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@ -1450,7 +1450,7 @@ struct hl_cs_chunk {
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* a DRAM address of the internal CB. In Gaudi, this might also
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* represent a mapped host address of the CB.
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*
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* Greco onwards:
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* Gaudi2 onwards:
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* For H/W queue, this represents either a Handle of CB on the
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* Host, or an SRAM, a DRAM, or a mapped host address of the CB.
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*
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@ -2227,7 +2227,7 @@ struct hl_debug_args {
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* internal. The driver will get completion notifications from the device only
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* on JOBS which are enqueued in the external queues.
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*
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* Greco onwards:
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* Gaudi2 onwards:
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* There is a single type of queue for all types of engines, either DMA engines
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* for transfers from/to the host or inside the device, or compute engines.
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* The driver will get completion notifications from the device for all queues.
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