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[PATCH] powerpc: Merge cacheflush.h and cache.h

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The ppc32 and ppc64 versions of cacheflush.h were almost identical.
The two versions of cache.h are fairly similar, except for a bunch of
register definitions in the ppc32 version which probably belong better
elsewhere.  This patch, therefore, merges both headers.  Notable
points:
	- there are several functions in cacheflush.h which exist only
on ppc32 or only on ppc64.  These are handled by #ifdef for now, but
these should probably be consolidated, along with the actual code
behind them later.
	- Confusingly, both ppc32 and ppc64 have a
flush_dcache_range(), but they're subtly different: it uses dcbf on
ppc32 and dcbst on ppc64, ppc64 has a flush_inval_dcache_range() which
uses dcbf.  These too should be merged and consolidated later.
	- Also flush_dcache_range() was defined in cacheflush.h on
ppc64, and in cache.h on ppc32.  In the merged version it's in
cacheflush.h
	- On ppc32 flush_icache_range() is a normal function from
misc.S.  On ppc64, it was wrapper, testing a feature bit before
calling __flush_icache_range() which does the actual flush.  This
patch takes the ppc64 approach, which amounts to no change on ppc32,
since CPU_FTR_COHERENT_ICACHE will never be set there, but does mean
renaming flush_icache_range() to __flush_icache_range() in
arch/ppc/kernel/misc.S and arch/powerpc/kernel/misc_32.S
	- The PReP register info from asm-ppc/cache.h has moved to
arch/ppc/platforms/prep_setup.c
	- The 8xx register info from asm-ppc/cache.h has moved to a
new asm-powerpc/reg_8xx.h, included from reg.h
	- flush_dcache_all() was defined on ppc32 (only), but was
never called (although it was exported).  Thus this patch removes it
from cacheflush.h and from ARCH=powerpc (misc_32.S) entirely.  It's
left in ARCH=ppc for now, with the prototype moved to ppc_ksyms.c.

Built for Walnut (ARCH=ppc), 32-bit multiplatform (pmac, CHRP and PReP
ARCH=ppc, pmac and CHRP ARCH=powerpc).  Built and booted on POWER5
LPAR (ARCH=powerpc and ARCH=ppc64).

Built for 32-bit powermac (ARCH=ppc and ARCH=powerpc).  Built and
booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64).  Built and booted
on G5 (ARCH=powerpc)

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
David Gibson 2005-11-10 11:50:16 +11:00 committed by Paul Mackerras
parent e130bedb7c
commit 26ef5c0957
10 changed files with 105 additions and 179 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
arch/powerpc/kernel/misc_32.S
View File

@ -519,7 +519,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
* *
* flush_icache_range(unsigned long start, unsigned long stop) * flush_icache_range(unsigned long start, unsigned long stop)
*/ */
_GLOBAL(flush_icache_range) _GLOBAL(__flush_icache_range)
BEGIN_FTR_SECTION BEGIN_FTR_SECTION
blr /* for 601, do nothing */ blr /* for 601, do nothing */
END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
@ -607,27 +607,6 @@ _GLOBAL(invalidate_dcache_range)
sync /* wait for dcbi's to get to ram */ sync /* wait for dcbi's to get to ram */
blr blr
#ifdef CONFIG_NOT_COHERENT_CACHE
/*
* 40x cores have 8K or 16K dcache and 32 byte line size.
* 44x has a 32K dcache and 32 byte line size.
* 8xx has 1, 2, 4, 8K variants.
* For now, cover the worst case of the 44x.
* Must be called with external interrupts disabled.
*/
#define CACHE_NWAYS 64
#define CACHE_NLINES 16
_GLOBAL(flush_dcache_all)
li r4, (2 * CACHE_NWAYS * CACHE_NLINES)
mtctr r4
lis r5, KERNELBASE@h
1: lwz r3, 0(r5) /* Load one word from every line */
addi r5, r5, L1_CACHE_BYTES
bdnz 1b
blr
#endif /* CONFIG_NOT_COHERENT_CACHE */
/* /*
* Flush a particular page from the data cache to RAM. * Flush a particular page from the data cache to RAM.
* Note: this is necessary because the instruction cache does *not* * Note: this is necessary because the instruction cache does *not*

4
arch/ppc/kernel/misc.S
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@ -497,9 +497,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
* and invalidate the corresponding instruction cache blocks. * and invalidate the corresponding instruction cache blocks.
* This is a no-op on the 601. * This is a no-op on the 601.
* *
* flush_icache_range(unsigned long start, unsigned long stop) * __flush_icache_range(unsigned long start, unsigned long stop)
*/ */
_GLOBAL(flush_icache_range) _GLOBAL(__flush_icache_range)
BEGIN_FTR_SECTION BEGIN_FTR_SECTION
blr /* for 601, do nothing */ blr /* for 601, do nothing */
END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)

1
arch/ppc/kernel/ppc_ksyms.c
View File

@ -175,6 +175,7 @@ EXPORT_SYMBOL(pci_bus_to_phys);
#endif /* CONFIG_PCI */ #endif /* CONFIG_PCI */
#ifdef CONFIG_NOT_COHERENT_CACHE #ifdef CONFIG_NOT_COHERENT_CACHE
extern void flush_dcache_all(void);
EXPORT_SYMBOL(flush_dcache_all); EXPORT_SYMBOL(flush_dcache_all);
#endif #endif

9
arch/ppc/platforms/prep_setup.c
View File

@ -61,6 +61,15 @@
#include <asm/pci-bridge.h> #include <asm/pci-bridge.h>
#include <asm/todc.h> #include <asm/todc.h>
/* prep registers for L2 */
#define CACHECRBA 0x80000823 /* Cache configuration register address */
#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
#define L2CACHE_512KB 0x00 /* 512KB */
#define L2CACHE_256KB 0x01 /* 256KB */
#define L2CACHE_1MB 0x02 /* 1MB */
#define L2CACHE_NONE 0x03 /* NONE */
#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
TODC_ALLOC(); TODC_ALLOC();
unsigned char ucSystemType; unsigned char ucSystemType;

40
include/asm-powerpc/cache.h Normal file
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@ -0,0 +1,40 @@
#ifndef _ASM_POWERPC_CACHE_H
#define _ASM_POWERPC_CACHE_H
#ifdef __KERNEL__
#include <linux/config.h>
/* bytes per L1 cache line */
#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
#define L1_CACHE_SHIFT 4
#define MAX_COPY_PREFETCH 1
#elif defined(CONFIG_PPC32)
#define L1_CACHE_SHIFT 5
#define MAX_COPY_PREFETCH 4
#else /* CONFIG_PPC64 */
#define L1_CACHE_SHIFT 7
#endif
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
struct ppc64_caches {
u32 dsize; /* L1 d-cache size */
u32 dline_size; /* L1 d-cache line size */
u32 log_dline_size;
u32 dlines_per_page;
u32 isize; /* L1 i-cache size */
u32 iline_size; /* L1 i-cache line size */
u32 log_iline_size;
u32 ilines_per_page;
};
extern struct ppc64_caches ppc64_caches;
#endif /* __powerpc64__ && ! __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_CACHE_H */

66
include/asm-ppc64/cacheflush.h → include/asm-powerpc/cacheflush.h
View File

@ -1,13 +1,20 @@
#ifndef _PPC64_CACHEFLUSH_H /*
#define _PPC64_CACHEFLUSH_H * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef _ASM_POWERPC_CACHEFLUSH_H
#define _ASM_POWERPC_CACHEFLUSH_H
#ifdef __KERNEL__
#include <linux/mm.h> #include <linux/mm.h>
#include <asm/cputable.h> #include <asm/cputable.h>
/* /*
* No cache flushing is required when address mappings are * No cache flushing is required when address mappings are changed,
* changed, because the caches on PowerPCs are physically * because the caches on PowerPCs are physically addressed.
* addressed.
*/ */
#define flush_cache_all() do { } while (0) #define flush_cache_all() do { } while (0)
#define flush_cache_mm(mm) do { } while (0) #define flush_cache_mm(mm) do { } while (0)
@ -22,27 +29,40 @@ extern void flush_dcache_page(struct page *page);
#define flush_dcache_mmap_unlock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0)
extern void __flush_icache_range(unsigned long, unsigned long); extern void __flush_icache_range(unsigned long, unsigned long);
extern void flush_icache_user_range(struct vm_area_struct *vma,
struct page *page, unsigned long addr,
int len);
extern void flush_dcache_range(unsigned long start, unsigned long stop);
extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
do { memcpy(dst, src, len); \
flush_icache_user_range(vma, page, vaddr, len); \
} while (0)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
memcpy(dst, src, len)
extern void __flush_dcache_icache(void *page_va);
static inline void flush_icache_range(unsigned long start, unsigned long stop) static inline void flush_icache_range(unsigned long start, unsigned long stop)
{ {
if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
__flush_icache_range(start, stop); __flush_icache_range(start, stop);
} }
#endif /* _PPC64_CACHEFLUSH_H */ extern void flush_icache_user_range(struct vm_area_struct *vma,
struct page *page, unsigned long addr,
int len);
extern void __flush_dcache_icache(void *page_va);
extern void flush_dcache_icache_page(struct page *page);
#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
extern void __flush_dcache_icache_phys(unsigned long physaddr);
#endif /* CONFIG_PPC32 && !CONFIG_BOOKE */
extern void flush_dcache_range(unsigned long start, unsigned long stop);
#ifdef CONFIG_PPC32
extern void clean_dcache_range(unsigned long start, unsigned long stop);
extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
#endif /* CONFIG_PPC32 */
#ifdef CONFIG_PPC64
extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
#endif
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
do { \
memcpy(dst, src, len); \
flush_icache_user_range(vma, page, vaddr, len); \
} while (0)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
memcpy(dst, src, len)
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_CACHEFLUSH_H */

6
include/asm-powerpc/reg.h
View File

@ -16,7 +16,11 @@
/* Pickup Book E specific registers. */ /* Pickup Book E specific registers. */
#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
#include <asm/reg_booke.h> #include <asm/reg_booke.h>
#endif #endif /* CONFIG_BOOKE || CONFIG_40x */
#ifdef CONFIG_8xx
#include <asm/reg_8xx.h>
#endif /* CONFIG_8xx */
#define MSR_SF_LG 63 /* Enable 64 bit mode */ #define MSR_SF_LG 63 /* Enable 64 bit mode */
#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */

50
include/asm-ppc/cache.h → include/asm-powerpc/reg_8xx.h
View File

@ -1,49 +1,9 @@
/* /*
* include/asm-ppc/cache.h * Contains register definitions common to PowerPC 8xx CPUs. Notice
*/ */
#ifdef __KERNEL__ #ifndef _ASM_POWERPC_REG_8xx_H
#ifndef __ARCH_PPC_CACHE_H #define _ASM_POWERPC_REG_8xx_H
#define __ARCH_PPC_CACHE_H
#include <linux/config.h>
/* bytes per L1 cache line */
#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
#define L1_CACHE_SHIFT 4
#define MAX_COPY_PREFETCH 1
#elif defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_SHIFT 7
#define MAX_COPY_PREFETCH 1
#else
#define L1_CACHE_SHIFT 5
#define MAX_COPY_PREFETCH 4
#endif
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
#define L1_CACHE_PAGES 8
#ifndef __ASSEMBLY__
extern void clean_dcache_range(unsigned long start, unsigned long stop);
extern void flush_dcache_range(unsigned long start, unsigned long stop);
extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
extern void flush_dcache_all(void);
#endif /* __ASSEMBLY__ */
/* prep registers for L2 */
#define CACHECRBA 0x80000823 /* Cache configuration register address */
#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
#define L2CACHE_512KB 0x00 /* 512KB */
#define L2CACHE_256KB 0x01 /* 256KB */
#define L2CACHE_1MB 0x02 /* 1MB */
#define L2CACHE_NONE 0x03 /* NONE */
#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
#ifdef CONFIG_8xx
/* Cache control on the MPC8xx is provided through some additional /* Cache control on the MPC8xx is provided through some additional
* special purpose registers. * special purpose registers.
*/ */
@ -78,7 +38,5 @@ extern void flush_dcache_all(void);
#define DC_DFWT 0x40000000 /* Data cache is forced write through */ #define DC_DFWT 0x40000000 /* Data cache is forced write through */
#define DC_LES 0x20000000 /* Caches are little endian mode */ #define DC_LES 0x20000000 /* Caches are little endian mode */
#endif /* CONFIG_8xx */
#endif #endif /* _ASM_POWERPC_REG_8xx_H */
#endif /* __KERNEL__ */

49
include/asm-ppc/cacheflush.h
View File

@ -1,49 +0,0 @@
/*
* include/asm-ppc/cacheflush.h
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifdef __KERNEL__
#ifndef _PPC_CACHEFLUSH_H
#define _PPC_CACHEFLUSH_H
#include <linux/mm.h>
/*
* No cache flushing is required when address mappings are
* changed, because the caches on PowerPCs are physically
* addressed. -- paulus
* Also, when SMP we use the coherency (M) bit of the
* BATs and PTEs. -- Cort
*/
#define flush_cache_all() do { } while (0)
#define flush_cache_mm(mm) do { } while (0)
#define flush_cache_range(vma, a, b) do { } while (0)
#define flush_cache_page(vma, p, pfn) do { } while (0)
#define flush_icache_page(vma, page) do { } while (0)
#define flush_cache_vmap(start, end) do { } while (0)
#define flush_cache_vunmap(start, end) do { } while (0)
extern void flush_dcache_page(struct page *page);
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
extern void flush_icache_range(unsigned long, unsigned long);
extern void flush_icache_user_range(struct vm_area_struct *vma,
struct page *page, unsigned long addr, int len);
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
do { memcpy(dst, src, len); \
flush_icache_user_range(vma, page, vaddr, len); \
} while (0)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
memcpy(dst, src, len)
extern void __flush_dcache_icache(void *page_va);
extern void __flush_dcache_icache_phys(unsigned long physaddr);
extern void flush_dcache_icache_page(struct page *page);
#endif /* _PPC_CACHEFLUSH_H */
#endif /* __KERNEL__ */

36
include/asm-ppc64/cache.h
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@ -1,36 +0,0 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __ARCH_PPC64_CACHE_H
#define __ARCH_PPC64_CACHE_H
#include <asm/types.h>
/* bytes per L1 cache line */
#define L1_CACHE_SHIFT 7
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
#ifndef __ASSEMBLY__
struct ppc64_caches {
u32 dsize; /* L1 d-cache size */
u32 dline_size; /* L1 d-cache line size */
u32 log_dline_size;
u32 dlines_per_page;
u32 isize; /* L1 i-cache size */
u32 iline_size; /* L1 i-cache line size */
u32 log_iline_size;
u32 ilines_per_page;
};
extern struct ppc64_caches ppc64_caches;
#endif
#endif