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mmc: sunxi: Keep default timing phase settings for new timing mode

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The register for the "new timing mode" also has bit fields for setting
output and sample timing phases. According to comments in Allwinner's
BSP kernel, the default values are good enough.

Keep the default values already in the hardware when setting new timing
mode, instead of overwriting the whole register.

Fixes: 9a37e53e45 ("mmc: sunxi: Enable the new timings for the A64 MMC
controllers")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Chen-Yu Tsai 2017-07-14 14:42:55 +08:00 committed by Ulf Hansson
parent 5771a8c088
commit 26cb2be4c7
1 changed files with 6 additions and 2 deletions
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8
drivers/mmc/host/sunxi-mmc.c
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@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
}
mmc_writel(host, REG_CLKCR, rval);
if (host->cfg->needs_new_timings)
mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
if (host->cfg->needs_new_timings) {
/* Don't touch the delay bits */
rval = mmc_readl(host, REG_SD_NTSR);
rval |= SDXC_2X_TIMING_MODE;
mmc_writel(host, REG_SD_NTSR, rval);
}
ret = sunxi_mmc_clk_set_phase(host, ios, rate);
if (ret)