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arm64: dts: ti: k3-am65: restrict PCIe to Gen2 speed

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Per errata i2104 documented in AM65x device errata document (TI document
number SPRZ452E, revised June 2019), Gen3 operation is not supported for
both PCIe Root Complex and Endpoint modes of operation.

See: https://www.ti.com/lit/er/sprz452e/sprz452e.pdf

Restrict speed to Gen2 to address the errata.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20200802165356.10285-1-nsekhar@ti.com
This commit is contained in:
Sekhar Nori 2020-08-02 22:23:56 +05:30 committed by Nishanth Menon
parent 67cfbb6213
commit 269a5641b1
1 changed files with 4 additions and 4 deletions
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8
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
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@ -704,7 +704,7 @@
ti,syscon-pcie-mode = <&pcie0_mode>;
bus-range = <0x0 0xff>;
num-viewport = <16>;
max-link-speed = <3>;
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
@ -718,7 +718,7 @@
ti,syscon-pcie-mode = <&pcie0_mode>;
num-ib-windows = <16>;
num-ob-windows = <16>;
max-link-speed = <3>;
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
};
@ -736,7 +736,7 @@
ti,syscon-pcie-mode = <&pcie1_mode>;
bus-range = <0x0 0xff>;
num-viewport = <16>;
max-link-speed = <3>;
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x10000 0x10000>;
@ -750,7 +750,7 @@
ti,syscon-pcie-mode = <&pcie1_mode>;
num-ib-windows = <16>;
num-ob-windows = <16>;
max-link-speed = <3>;
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
};