korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-11-11 12:28:41 +08:00
Code Issues Packages Projects Releases Wiki Activity

Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

Browse Source 
No conflicts.

Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2022-08-18 21:17:10 -07:00
commit 268603d79c
657 changed files with 109765 additions and 11572 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/ABI/testing/sysfs-driver-xen-blkback
View File

@ -42,5 +42,5 @@ KernelVersion: 5.10
Contact: Maximilian Heyne <mheyne@amazon.de>
Description:
Whether to enable the persistent grants feature or not. Note
that this option only takes effect on newly created backends.
that this option only takes effect on newly connected backends.
The default is Y (enable).

2
Documentation/ABI/testing/sysfs-driver-xen-blkfront
View File

@ -15,5 +15,5 @@ KernelVersion: 5.10
Contact: Maximilian Heyne <mheyne@amazon.de>
Description:
Whether to enable the persistent grants feature or not. Note
that this option only takes effect on newly created frontends.
that this option only takes effect on newly connected frontends.
The default is Y (enable).

2
Documentation/PCI/endpoint/index.rst
View File

@ -13,6 +13,8 @@ PCI Endpoint Framework
pci-test-howto
pci-ntb-function
pci-ntb-howto
pci-vntb-function
pci-vntb-howto
function/binding/pci-test
function/binding/pci-ntb

129
Documentation/PCI/endpoint/pci-vntb-function.rst Normal file
View File

@ -0,0 +1,129 @@
.. SPDX-License-Identifier: GPL-2.0
=================
PCI vNTB Function
=================
:Author: Frank Li <Frank.Li@nxp.com>
The difference between PCI NTB function and PCI vNTB function is
PCI NTB function need at two endpoint instances and connect HOST1
and HOST2.
PCI vNTB function only use one host and one endpoint(EP), use NTB
connect EP and PCI host
.. code-block:: text
+------------+ +---------------------------------------+
| | | |
+------------+ | +--------------+
| NTB | | | NTB |
| NetDev | | | NetDev |
+------------+ | +--------------+
| NTB | | | NTB |
| Transfer | | | Transfer |
+------------+ | +--------------+
| | | | |
| PCI NTB | | | |
| EPF | | | |
| Driver | | | PCI Virtual |
| | +---------------+ | NTB Driver |
| | | PCI EP NTB |<------>| |
| | | FN Driver | | |
+------------+ +---------------+ +--------------+
| | | | | |
| PCI BUS | <-----> | PCI EP BUS | | Virtual PCI |
| | PCI | | | BUS |
+------------+ +---------------+--------+--------------+
PCI RC PCI EP
Constructs used for Implementing vNTB
=====================================
1) Config Region
2) Self Scratchpad Registers
3) Peer Scratchpad Registers
4) Doorbell (DB) Registers
5) Memory Window (MW)
Config Region:
--------------
It is same as PCI NTB Function driver
Scratchpad Registers:
---------------------
It is appended after Config region.
.. code-block:: text
+--------------------------------------------------+ Base
| |
| |
| |
| Common Config Register |
| |
| |
| |
+-----------------------+--------------------------+ Base + span_offset
| | |
| Peer Span Space | Span Space |
| | |
| | |
+-----------------------+--------------------------+ Base + span_offset
| | | + span_count * 4
| | |
| Span Space | Peer Span Space |
| | |
+-----------------------+--------------------------+
Virtual PCI Pcie Endpoint
NTB Driver NTB Driver
Doorbell Registers:
-------------------
Doorbell Registers are used by the hosts to interrupt each other.
Memory Window:
--------------
Actual transfer of data between the two hosts will happen using the
memory window.
Modeling Constructs:
====================
32-bit BARs.
====== ===============
BAR NO CONSTRUCTS USED
====== ===============
BAR0 Config Region
BAR1 Doorbell
BAR2 Memory Window 1
BAR3 Memory Window 2
BAR4 Memory Window 3
BAR5 Memory Window 4
====== ===============
64-bit BARs.
====== ===============================
BAR NO CONSTRUCTS USED
====== ===============================
BAR0 Config Region + Scratchpad
BAR1
BAR2 Doorbell
BAR3
BAR4 Memory Window 1
BAR5
====== ===============================

167
Documentation/PCI/endpoint/pci-vntb-howto.rst Normal file
View File

@ -0,0 +1,167 @@
.. SPDX-License-Identifier: GPL-2.0
===================================================================
PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide
===================================================================
:Author: Frank Li <Frank.Li@nxp.com>
This document is a guide to help users use pci-epf-vntb function driver
and ntb_hw_epf host driver for NTB functionality. The list of steps to
be followed in the host side and EP side is given below. For the hardware
configuration and internals of NTB using configurable endpoints see
Documentation/PCI/endpoint/pci-vntb-function.rst
Endpoint Device
===============
Endpoint Controller Devices
---------------------------
To find the list of endpoint controller devices in the system::
# ls /sys/class/pci_epc/
5f010000.pcie_ep
If PCI_ENDPOINT_CONFIGFS is enabled::
# ls /sys/kernel/config/pci_ep/controllers
5f010000.pcie_ep
Endpoint Function Drivers
-------------------------
To find the list of endpoint function drivers in the system::
# ls /sys/bus/pci-epf/drivers
pci_epf_ntb pci_epf_test pci_epf_vntb
If PCI_ENDPOINT_CONFIGFS is enabled::
# ls /sys/kernel/config/pci_ep/functions
pci_epf_ntb pci_epf_test pci_epf_vntb
Creating pci-epf-vntb Device
----------------------------
PCI endpoint function device can be created using the configfs. To create
pci-epf-vntb device, the following commands can be used::
# mount -t configfs none /sys/kernel/config
# cd /sys/kernel/config/pci_ep/
# mkdir functions/pci_epf_vntb/func1
The "mkdir func1" above creates the pci-epf-ntb function device that will
be probed by pci_epf_vntb driver.
The PCI endpoint framework populates the directory with the following
configurable fields::
# ls functions/pci_epf_ntb/func1
baseclass_code deviceid msi_interrupts pci-epf-ntb.0
progif_code secondary subsys_id vendorid
cache_line_size interrupt_pin msix_interrupts primary
revid subclass_code subsys_vendor_id
The PCI endpoint function driver populates these entries with default values
when the device is bound to the driver. The pci-epf-vntb driver populates
vendorid with 0xffff and interrupt_pin with 0x0001::
# cat functions/pci_epf_vntb/func1/vendorid
0xffff
# cat functions/pci_epf_vntb/func1/interrupt_pin
0x0001
Configuring pci-epf-vntb Device
-------------------------------
The user can configure the pci-epf-vntb device using its configfs entry. In order
to change the vendorid and the deviceid, the following
commands can be used::
# echo 0x1957 > functions/pci_epf_vntb/func1/vendorid
# echo 0x0809 > functions/pci_epf_vntb/func1/deviceid
In order to configure NTB specific attributes, a new sub-directory to func1
should be created::
# mkdir functions/pci_epf_vntb/func1/pci_epf_vntb.0/
The NTB function driver will populate this directory with various attributes
that can be configured by the user::
# ls functions/pci_epf_vntb/func1/pci_epf_vntb.0/
db_count mw1 mw2 mw3 mw4 num_mws
spad_count
A sample configuration for NTB function is given below::
# echo 4 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/db_count
# echo 128 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/spad_count
# echo 1 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/num_mws
# echo 0x100000 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/mw1
A sample configuration for virtual NTB driver for virutal PCI bus::
# echo 0x1957 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/vntb_vid
# echo 0x080A > functions/pci_epf_vntb/func1/pci_epf_vntb.0/vntb_pid
# echo 0x10 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/vbus_number
Binding pci-epf-ntb Device to EP Controller
--------------------------------------------
NTB function device should be attached to PCI endpoint controllers
connected to the host.
# ln -s controllers/5f010000.pcie_ep functions/pci-epf-ntb/func1/primary
Once the above step is completed, the PCI endpoint controllers are ready to
establish a link with the host.
Start the Link
--------------
In order for the endpoint device to establish a link with the host, the _start_
field should be populated with '1'. For NTB, both the PCI endpoint controllers
should establish link with the host (imx8 don't need this steps)::
# echo 1 > controllers/5f010000.pcie_ep/start
RootComplex Device
==================
lspci Output at Host side
-------------------------
Note that the devices listed here correspond to the values populated in
"Creating pci-epf-ntb Device" section above::
# lspci
00:00.0 PCI bridge: Freescale Semiconductor Inc Device 0000 (rev 01)
01:00.0 RAM memory: Freescale Semiconductor Inc Device 0809
Endpoint Device / Virtual PCI bus
=================================
lspci Output at EP Side / Virtual PCI bus
-----------------------------------------
Note that the devices listed here correspond to the values populated in
"Creating pci-epf-ntb Device" section above::
# lspci
10:00.0 Unassigned class [ffff]: Dawicontrol Computersysteme GmbH Device 1234 (rev ff)
Using ntb_hw_epf Device
-----------------------
The host side software follows the standard NTB software architecture in Linux.
All the existing client side NTB utilities like NTB Transport Client and NTB
Netdev, NTB Ping Pong Test Client and NTB Tool Test Client can be used with NTB
function device.
For more information on NTB see
:doc:`Non-Transparent Bridge <../../driver-api/ntb>`

29
Documentation/admin-guide/kernel-parameters.txt
View File

@ -5274,20 +5274,33 @@
Speculative Code Execution with Return Instructions)
vulnerability.
AMD-based UNRET and IBPB mitigations alone do not stop
sibling threads from influencing the predictions of other
sibling threads. For that reason, STIBP is used on pro-
cessors that support it, and mitigate SMT on processors
that don't.
off - no mitigation
auto - automatically select a migitation
auto,nosmt - automatically select a mitigation,
disabling SMT if necessary for
the full mitigation (only on Zen1
and older without STIBP).
ibpb - mitigate short speculation windows on
basic block boundaries too. Safe, highest
perf impact.
unret - force enable untrained return thunks,
only effective on AMD f15h-f17h
based systems.
unret,nosmt - like unret, will disable SMT when STIBP
is not available.
ibpb - On AMD, mitigate short speculation
windows on basic block boundaries too.
Safe, highest perf impact. It also
enables STIBP if present. Not suitable
on Intel.
ibpb,nosmt - Like "ibpb" above but will disable SMT
when STIBP is not available. This is
the alternative for systems which do not
have STIBP.
unret - Force enable untrained return thunks,
only effective on AMD f15h-f17h based
systems.
unret,nosmt - Like unret, but will disable SMT when STIBP
is not available. This is the alternative for
systems which do not have STIBP.
Selecting 'auto' will choose a mitigation method at run
time according to the CPU.

2
Documentation/atomic_bitops.txt
View File

@ -59,7 +59,7 @@ Like with atomic_t, the rule of thumb is:
- RMW operations that have a return value are fully ordered.
- RMW operations that are conditional are unordered on FAILURE,
otherwise the above rules apply. In the case of test_and_{}_bit() operations,
otherwise the above rules apply. In the case of test_and_set_bit_lock(),
if the bit in memory is unchanged by the operation then it is deemed to have
failed.

4
Documentation/devicetree/bindings/Makefile
View File

@ -42,9 +42,7 @@ quiet_cmd_chk_bindings = CHKDT $@
quiet_cmd_mk_schema = SCHEMA $@
cmd_mk_schema = f=$$(mktemp) ; \
$(if $(DT_MK_SCHEMA_FLAGS), \
printf '%s\n' $(real-prereqs), \
$(find_all_cmd)) > $$f ; \
$(find_all_cmd) > $$f ; \
$(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \
rm -f $$f

15
Documentation/devicetree/bindings/arm/atmel-sysregs.txt
View File

@ -25,21 +25,6 @@ System Timer (ST) required properties:
Its subnodes can be:
- watchdog: compatible should be "atmel,at91rm9200-wdt"
RSTC Reset Controller required properties:
- compatible: Should be "atmel,<chip>-rstc".
<chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7"
it also can be "microchip,sam9x60-rstc"
- reg: Should contain registers location and length
- clocks: phandle to input clock.
Example:
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;
};
RAMC SDRAM/DDR Controller required properties:
- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
"atmel,at91sam9260-sdramc",

15
Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
View File

@ -20,13 +20,24 @@ properties:
compatible:
const: google,cros-ec-typec
connector:
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
'^connector@[0-9a-f]+$':
$ref: /schemas/connector/usb-connector.yaml#
unevaluatedProperties: false
properties:
reg:
maxItems: 1
required:
- compatible
additionalProperties: true #fixme
additionalProperties: false
examples:
- |+

27
Documentation/devicetree/bindings/display/ilitek,ili9341.txt
View File

@ -1,27 +0,0 @@
Ilitek ILI9341 display panels
This binding is for display panels using an Ilitek ILI9341 controller in SPI
mode.
Required properties:
- compatible: "adafruit,yx240qv29", "ilitek,ili9341"
- dc-gpios: D/C pin
- reset-gpios: Reset pin
The node for this driver must be a child node of a SPI controller, hence
all mandatory properties described in ../spi/spi-bus.txt must be specified.
Optional properties:
- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
- backlight: phandle of the backlight device attached to the panel
Example:
display@0{
compatible = "adafruit,yx240qv29", "ilitek,ili9341";
reg = <0>;
spi-max-frequency = <32000000>;
dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
rotation = <270>;
backlight = <&backlight>;
};

49
Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
View File

@ -21,8 +21,10 @@ properties:
compatible:
items:
- enum:
- adafruit,yx240qv29
# ili9341 240*320 Color on stm32f429-disco board
- st,sf-tc240t-9370-t
- canaan,kd233-tft
- const: ilitek,ili9341
reg: true
@ -47,31 +49,50 @@ properties:
vddi-led-supply:
description: Voltage supply for the LED driver (1.65 .. 3.3 V)
additionalProperties: false
unevaluatedProperties: false
required:
- compatible
- reg
- dc-gpios
- port
if:
properties:
compatible:
contains:
enum:
- st,sf-tc240t-9370-t
then:
required:
- port
examples:
- |+
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
panel: display@0 {
compatible = "st,sf-tc240t-9370-t",
"ilitek,ili9341";
reg = <0>;
spi-3wire;
spi-max-frequency = <10000000>;
dc-gpios = <&gpiod 13 0>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
compatible = "st,sf-tc240t-9370-t",
"ilitek,ili9341";
reg = <0>;
spi-3wire;
spi-max-frequency = <10000000>;
dc-gpios = <&gpiod 13 0>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
display@1{
compatible = "adafruit,yx240qv29", "ilitek,ili9341";
reg = <1>;
spi-max-frequency = <10000000>;
dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
rotation = <270>;
backlight = <&backlight>;
};
};
...

1
Documentation/devicetree/bindings/display/simple-framebuffer.yaml
View File

@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Simple Framebuffer Device Tree Bindings
maintainers:
- Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
- Hans de Goede <hdegoede@redhat.com>
description: |+

4
Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
View File

@ -46,6 +46,10 @@ properties:
maximum: 32
default: 16
gpio-line-names:
minItems: 1
maxItems: 32
gpio-controller: true
required:

1
Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml
View File

@ -8,7 +8,6 @@ title: Analog Devices ADM1177 Hot Swap Controller and Digital Power Monitor
maintainers:
- Michael Hennerich <michael.hennerich@analog.com>
- Beniamin Bia <beniamin.bia@analog.com>
description: |
Analog Devices ADM1177 Hot Swap Controller and Digital Power Monitor

1
Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml
View File

@ -27,6 +27,7 @@ properties:
- const: mediatek,mt8173-i2c
- const: mediatek,mt8183-i2c
- const: mediatek,mt8186-i2c
- const: mediatek,mt8188-i2c
- const: mediatek,mt8192-i2c
- items:
- enum:

96
Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt
View File

@ -1,96 +0,0 @@
Qualcomm Camera Control Interface (CCI) I2C controller
PROPERTIES:
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,msm8916-cci"
"qcom,msm8974-cci"
"qcom,msm8996-cci"
"qcom,sdm845-cci"
"qcom,sm8250-cci"
"qcom,sm8450-cci"
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: base address CCI I2C controller and length of memory
mapped region.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: specifies the CCI I2C interrupt. The format of the
specifier is defined by the binding document describing
the node's interrupt parent.
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: a list of phandle, should contain an entry for each
entries in clock-names.
- clock-names
Usage: required
Value type: <string>
Definition: a list of clock names, must include "cci" clock.
- power-domains
Usage: required for "qcom,msm8996-cci"
Value type: <prop-encoded-array>
Definition:
SUBNODES:
The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8974,
msm8996, sdm845, sm8250 and sm8450), described as subdevices named "i2c-bus@0"
and "i2c-bus@1".
PROPERTIES:
- reg:
Usage: required
Value type: <u32>
Definition: Index of the CCI bus/master
- clock-frequency:
Usage: optional
Value type: <u32>
Definition: Desired I2C bus clock frequency in Hz, defaults to 100
kHz if omitted.
Example:
cci@a0c000 {
compatible = "qcom,msm8996-cci";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa0c000 0x1000>;
interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>,
<&mmcc CAMSS_TOP_AHB_CLK>,
<&mmcc CAMSS_CCI_AHB_CLK>,
<&mmcc CAMSS_CCI_CLK>,
<&mmcc CAMSS_AHB_CLK>;
clock-names = "mmss_mmagic_ahb",
"camss_top_ahb",
"cci_ahb",
"cci",
"camss_ahb";
i2c-bus@0 {
reg = <0>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c-bus@1 {
reg = <1>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
};

242
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml Normal file
View File

@ -0,0 +1,242 @@
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/qcom,i2c-cci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Control Interface (CCI) I2C controller
maintainers:
- Loic Poulain <loic.poulain@linaro.org>
- Robert Foss <robert.foss@linaro.org>
properties:
compatible:
enum:
- qcom,msm8916-cci
- qcom,msm8974-cci
- qcom,msm8996-cci
- qcom,sdm845-cci
- qcom,sm8250-cci
- qcom,sm8450-cci
"#address-cells":
const: 1
"#size-cells":
const: 0
clocks:
minItems: 4
maxItems: 6
clock-names:
minItems: 4
maxItems: 6
interrupts:
maxItems: 1
power-domains:
maxItems: 1
reg:
maxItems: 1
patternProperties:
"^i2c-bus@[01]$":
$ref: /schemas/i2c/i2c-controller.yaml#
unevaluatedProperties: false
properties:
reg:
maxItems: 1
clock-frequency:
default: 100000
required:
- compatible
- clock-names
- clocks
- interrupts
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8996-cci
then:
required:
- power-domains
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8916-cci
then:
properties:
i2c-bus@1: false
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8916-cci
- qcom,msm8996-cci
then:
properties:
clocks:
maxItems: 4
clock-names:
items:
- const: camss_top_ahb
- const: cci_ahb
- const: cci
- const: camss_ahb
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm845-cci
then:
properties:
clocks:
minItems: 6
clock-names:
items:
- const: camnoc_axi
- const: soc_ahb
- const: slow_ahb_src
- const: cpas_ahb
- const: cci
- const: cci_src
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8250-cci
then:
properties:
clocks:
minItems: 5
maxItems: 5
clock-names:
items:
- const: camnoc_axi
- const: slow_ahb_src
- const: cpas_ahb
- const: cci
- const: cci_src
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,camcc-sdm845.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
cci@ac4a000 {
reg = <0x0ac4a000 0x4000>;
compatible = "qcom,sdm845-cci";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
power-domains = <&clock_camcc TITAN_TOP_GDSC>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
<&clock_camcc CAM_CC_CCI_CLK>,
<&clock_camcc CAM_CC_CCI_CLK_SRC>;
clock-names = "camnoc_axi",
"soc_ahb",
"slow_ahb_src",
"cpas_ahb",
"cci",
"cci_src";
assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_CCI_CLK>;
assigned-clock-rates = <80000000>,
<37500000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cci0_default &cci1_default>;
pinctrl-1 = <&cci0_sleep &cci1_sleep>;
i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
camera@10 {
compatible = "ovti,ov8856";
reg = <0x10>;
reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&cam0_default>;
clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
clock-names = "xvclk";
clock-frequency = <19200000>;
dovdd-supply = <&vreg_lvs1a_1p8>;
avdd-supply = <&cam0_avdd_2v8>;
dvdd-supply = <&cam0_dvdd_1v2>;
port {
ov8856_ep: endpoint {
link-frequencies = /bits/ 64 <360000000 180000000>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csiphy0_ep>;
};
};
};
};
cci_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
camera@60 {
compatible = "ovti,ov7251";
reg = <0x60>;
enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam3_default>;
clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
clock-names = "xclk";
clock-frequency = <24000000>;
vdddo-supply = <&vreg_lvs1a_1p8>;
vdda-supply = <&cam3_avdd_2v8>;
port {
ov7251_ep: endpoint {
data-lanes = <0 1>;
remote-endpoint = <&csiphy3_ep>;
};
};
};
};
};

1
Documentation/devicetree/bindings/iio/accel/fsl,mma7455.yaml
View File

@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale MMA7455 and MMA7456 three axis accelerometers
maintainers:
- Joachim Eastwood <manabian@gmail.com>
- Jonathan Cameron <jic23@kernel.org>
description:

2
Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD7091R5 4-Channel 12-Bit ADC
maintainers:
- Beniamin Bia <beniamin.bia@analog.com>
- Michael Hennerich <michael.hennerich@analog.com>
description: |
Analog Devices AD7091R5 4-Channel 12-Bit ADC

3
Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml
View File

@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD7606 Simultaneous Sampling ADC
maintainers:
- Beniamin Bia <beniamin.bia@analog.com>
- Stefan Popa <stefan.popa@analog.com>
- Michael Hennerich <michael.hennerich@analog.com>
description: |
Analog Devices AD7606 Simultaneous Sampling ADC

2
Documentation/devicetree/bindings/iio/adc/nxp,lpc1850-adc.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC1850 ADC bindings
maintainers:
- Joachim Eastwood <manabian@gmail.com>
- Jonathan Cameron <jic23@kernel.org>
description:
Supports the ADC found on the LPC1850 SoC.

2
Documentation/devicetree/bindings/iio/adc/ti,adc108s102.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments ADC108S102 and ADC128S102
maintainers:
- Bogdan Pricop <bogdan.pricop@emutex.com>
- Jonathan Cameron <jic23@kernel.org>
description: |
Family of 8 channel, 10/12 bit, SPI, single ended ADCs.

2
Documentation/devicetree/bindings/iio/adc/ti,ads124s08.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments' ads124s08 and ads124s06 ADC chip
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Andrew Davis <afd@ti.com>
properties:
compatible:

1
Documentation/devicetree/bindings/iio/amplifiers/adi,hmc425a.yaml
View File

@ -8,7 +8,6 @@ title: HMC425A 6-bit Digital Step Attenuator
maintainers:
- Michael Hennerich <michael.hennerich@analog.com>
- Beniamin Bia <beniamin.bia@analog.com>
description: |
Digital Step Attenuator IIO device with gpio interface.

2
Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale FXOS8700 Inertial Measurement Unit
maintainers:
- Robert Jones <rjones@gateworks.com>
- Jonathan Cameron <jic23@kernel.org>
description: |
Accelerometer and magnetometer combo device with an i2c and SPI interface.

2
Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common properties for the multicolor LED class.
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Andrew Davis <afd@ti.com>
description: |
Bindings for multi color LEDs show how to describe current outputs of

2
Documentation/devicetree/bindings/leds/leds-lp50xx.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: LED driver for LP50XX RGB LED from Texas Instruments.
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The LP50XX is multi-channel, I2C RGB LED Drivers that can group RGB LEDs into

1
Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
View File

@ -57,6 +57,7 @@ properties:
maxItems: 1
interrupts:
minItems: 2
items:
- description: low-priority non-secure
- description: high-priority non-secure

52
Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml Normal file
View File

@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/canaan,k210-sram.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Canaan K210 SRAM memory controller
description:
The Canaan K210 SRAM memory controller is responsible for the system's 8 MiB
of SRAM. The controller is initialised by the bootloader, which configures
its clocks, before OS bringup.
maintainers:
- Conor Dooley <conor@kernel.org>
properties:
compatible:
enum:
- canaan,k210-sram
clocks:
minItems: 1
items:
- description: sram0 clock
- description: sram1 clock
- description: aisram clock
clock-names:
minItems: 1
items:
- const: sram0
- const: sram1
- const: aisram
required:
- compatible
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/k210-clk.h>
memory-controller {
compatible = "canaan,k210-sram";
clocks = <&sysclk K210_CLK_SRAM0>,
<&sysclk K210_CLK_SRAM1>,
<&sysclk K210_CLK_AI>;
clock-names = "sram0", "sram1", "aisram";
};

1
Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml
View File

@ -19,7 +19,6 @@ description: |
maintainers:
- Tim Harvey <tharvey@gateworks.com>
- Robert Jones <rjones@gateworks.com>
properties:
$nodename:

94
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
View File

@ -1,94 +0,0 @@
Qualcomm SPMI PMICs multi-function device bindings
The Qualcomm SPMI series presently includes PM8941, PM8841 and PMA8084
PMICs. These PMICs use a QPNP scheme through SPMI interface.
QPNP is effectively a partitioning scheme for dividing the SPMI extended
register space up into logical pieces, and set of fixed register
locations/definitions within these regions, with some of these regions
specifically used for interrupt handling.
The QPNP PMICs are used with the Qualcomm Snapdragon series SoCs, and are
interfaced to the chip via the SPMI (System Power Management Interface) bus.
Support for multiple independent functions are implemented by splitting the
16-bit SPMI slave address space into 256 smaller fixed-size regions, 256 bytes
each. A function can consume one or more of these fixed-size register regions.
Required properties:
- compatible: Should contain one of:
"qcom,pm660",
"qcom,pm660l",
"qcom,pm7325",
"qcom,pm8004",
"qcom,pm8005",
"qcom,pm8019",
"qcom,pm8028",
"qcom,pm8110",
"qcom,pm8150",
"qcom,pm8150b",
"qcom,pm8150c",
"qcom,pm8150l",
"qcom,pm8226",
"qcom,pm8350c",
"qcom,pm8841",
"qcom,pm8901",
"qcom,pm8909",
"qcom,pm8916",
"qcom,pm8941",
"qcom,pm8950",
"qcom,pm8953",
"qcom,pm8994",
"qcom,pm8998",
"qcom,pma8084",
"qcom,pmd9635",
"qcom,pmi8950",
"qcom,pmi8962",
"qcom,pmi8994",
"qcom,pmi8998",
"qcom,pmk8002",
"qcom,pmk8350",
"qcom,pmr735a",
"qcom,smb2351",
or generalized "qcom,spmi-pmic".
- reg: Specifies the SPMI USID slave address for this device.
For more information see:
Documentation/devicetree/bindings/spmi/spmi.yaml
Required properties for peripheral child nodes:
- compatible: Should contain "qcom,xxx", where "xxx" is a peripheral name.
Optional properties for peripheral child nodes:
- interrupts: Interrupts are specified as a 4-tuple. For more information
see:
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
- interrupt-names: Corresponding interrupt name to the interrupts property
Each child node of SPMI slave id represents a function of the PMIC. In the
example below the rtc device node represents a peripheral of pm8941
SID = 0. The regulator device node represents a peripheral of pm8941 SID = 1.
Example:
spmi {
compatible = "qcom,spmi-pmic-arb";
pm8941@0 {
compatible = "qcom,pm8941", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
rtc {
compatible = "qcom,rtc";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "alarm";
};
};
pm8941@1 {
compatible = "qcom,pm8941", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
regulator {
compatible = "qcom,regulator";
regulator-name = "8941_boost";
};
};
};

190
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml Normal file
View File

@ -0,0 +1,190 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SPMI PMICs multi-function device
description: |
Some Qualcomm PMICs used with the Snapdragon series SoCs are interfaced
to the chip via the SPMI (System Power Management Interface) bus.
Support for multiple independent functions are implemented by splitting the
16-bit SPMI peripheral address space into 256 smaller fixed-size regions, 256 bytes
each. A function can consume one or more of these fixed-size register regions.
The Qualcomm SPMI series includes the PM8941, PM8841, PMA8084, PM8998 and other
PMICs. These PMICs use a "QPNP" scheme through SPMI interface.
QPNP is effectively a partitioning scheme for dividing the SPMI extended
register space up into logical pieces, and set of fixed register
locations/definitions within these regions, with some of these regions
specifically used for interrupt handling.
maintainers:
- Stephen Boyd <sboyd@kernel.org>
properties:
$nodename:
oneOf:
- pattern: '^pmic@.*$'
- pattern: '^pm(a|s)?[0-9]*@.*$'
deprecated: true
compatible:
items:
- enum:
- qcom,pm660
- qcom,pm660l
- qcom,pm6150
- qcom,pm6150l
- qcom,pm6350
- qcom,pm7325
- qcom,pm8004
- qcom,pm8005
- qcom,pm8009
- qcom,pm8019
- qcom,pm8110
- qcom,pm8150
- qcom,pm8150b
- qcom,pm8150l
- qcom,pm8226
- qcom,pm8350
- qcom,pm8350b
- qcom,pm8350c
- qcom,pm8841
- qcom,pm8909
- qcom,pm8916
- qcom,pm8941
- qcom,pm8950
- qcom,pm8994
- qcom,pm8998
- qcom,pma8084
- qcom,pmd9635
- qcom,pmi8950
- qcom,pmi8962
- qcom,pmi8994
- qcom,pmi8998
- qcom,pmk8350
- qcom,pmm8155au
- qcom,pmr735a
- qcom,pmr735b
- qcom,pms405
- qcom,pmx55
- qcom,pmx65
- qcom,smb2351
- const: qcom,spmi-pmic
reg:
minItems: 1
maxItems: 2
'#address-cells':
const: 1
'#size-cells':
const: 0
labibb:
type: object
$ref: /schemas/regulator/qcom-labibb-regulator.yaml#
regulators:
type: object
$ref: /schemas/regulator/regulator.yaml#
patternProperties:
"^adc@[0-9a-f]+$":
type: object
$ref: /schemas/iio/adc/qcom,spmi-vadc.yaml#
"^adc-tm@[0-9a-f]+$":
type: object
$ref: /schemas/thermal/qcom-spmi-adc-tm5.yaml#
"^audio-codec@[0-9a-f]+$":
type: object
additionalProperties: true # FIXME qcom,pm8916-wcd-analog-codec binding not converted yet
"extcon@[0-9a-f]+$":
type: object
$ref: /schemas/extcon/qcom,pm8941-misc.yaml#
"gpio(s)?@[0-9a-f]+$":
type: object
$ref: /schemas/pinctrl/qcom,pmic-gpio.yaml#
"pon@[0-9a-f]+$":
type: object
$ref: /schemas/power/reset/qcom,pon.yaml#
"pwm@[0-9a-f]+$":
type: object
$ref: /schemas/leds/leds-qcom-lpg.yaml#
"^rtc@[0-9a-f]+$":
type: object
$ref: /schemas/rtc/qcom-pm8xxx-rtc.yaml#
"^temp-alarm@[0-9a-f]+$":
type: object
$ref: /schemas/thermal/qcom,spmi-temp-alarm.yaml#
"^vibrator@[0-9a-f]+$":
type: object
additionalProperties: true # FIXME qcom,pm8916-vib binding not converted yet
"^mpps@[0-9a-f]+$":
type: object
$ref: /schemas/pinctrl/qcom,pmic-mpp.yaml#
"(.*)?(wled|leds)@[0-9a-f]+$":
type: object
$ref: /schemas/leds/backlight/qcom-wled.yaml#
unevaluatedProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0c440000 0x1100>,
<0x0c600000 0x2000000>,
<0x0e600000 0x100000>,
<0x0e700000 0xa0000>,
<0x0c40a000 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
pmi8998_lsid0: pmic@2 {
compatible = "qcom,pmi8998", "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmi8998_gpio: gpios@c000 {
compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pmi8998_gpio 0 0 14>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

2
Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
View File

@ -137,6 +137,8 @@ properties:
max-frequency: true
operating-points-v2: true
patternProperties:
'^opp-table(-[a-z0-9]+)?$':
if:

2
Documentation/devicetree/bindings/net/qcom-emac.txt
View File

@ -14,7 +14,7 @@ MAC node:
- mac-address : The 6-byte MAC address. If present, it is the default
MAC address.
- internal-phy : phandle to the internal PHY node
- phy-handle : phandle the external PHY node
- phy-handle : phandle to the external PHY node
Internal PHY node:
- compatible : Should be "qcom,fsm9900-emac-sgmii" or "qcom,qdf2432-emac-sgmii".

2
Documentation/devicetree/bindings/net/ti,dp83822.yaml
View File

@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: TI DP83822 ethernet PHY
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It

2
Documentation/devicetree/bindings/net/ti,dp83867.yaml
View File

@ -11,7 +11,7 @@ allOf:
- $ref: "ethernet-controller.yaml#"
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The DP83867 device is a robust, low power, fully featured Physical Layer

2
Documentation/devicetree/bindings/net/ti,dp83869.yaml
View File

@ -11,7 +11,7 @@ allOf:
- $ref: "ethernet-phy.yaml#"
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver

2
Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
View File

@ -144,7 +144,7 @@ examples:
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 80>;
gpio-ranges = <&tlmm 0 0 80>;
serial3-pinmux {
pins = "gpio44", "gpio45";

17
Documentation/devicetree/bindings/power/reset/msm-poweroff.txt
View File

@ -1,17 +0,0 @@
MSM Restart Driver
A power supply hold (ps-hold) bit is set to power the msm chipsets.
Clearing that bit allows us to restart/poweroff. The difference
between poweroff and restart is determined by unique power manager IC
settings.
Required Properties:
-compatible: "qcom,pshold"
-reg: Specifies the physical address of the ps-hold register
Example:
restart@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};

35
Documentation/devicetree/bindings/power/reset/qcom,pshold.yaml Normal file
View File

@ -0,0 +1,35 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/reset/qcom,pshold.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SoC restart and power off
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description:
A power supply hold (ps-hold) bit is set to power the Qualcomm chipsets.
Clearing that bit allows us to restart/power off. The difference between
power off and restart is determined by unique power manager IC settings.
properties:
compatible:
const: qcom,pshold
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
reset-controller@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};

2
Documentation/devicetree/bindings/power/supply/bq24190.yaml
View File

@ -28,7 +28,7 @@ properties:
maxItems: 1
usb-otg-vbus:
type: object
$ref: /schemas/regulator/regulator.yaml#
description: |
Regulator that is used to control the VBUS voltage direction for
either USB host mode or for charging on the OTG port

3
Documentation/devicetree/bindings/power/supply/bq2515x.yaml
View File

@ -8,8 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI bq2515x 500-mA Linear charger family
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Ricardo Rivera-Matos <r-rivera-matos@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The BQ2515x family is a highly integrated battery charge management IC that

2
Documentation/devicetree/bindings/power/supply/bq256xx.yaml
View File

@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI bq256xx Switch Mode Buck Charger
maintainers:
- Ricardo Rivera-Matos <r-rivera-matos@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The bq256xx devices are a family of highly-integrated battery charge

3
Documentation/devicetree/bindings/power/supply/bq25980.yaml
View File

@ -8,8 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI BQ25980 Flash Charger
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Ricardo Rivera-Matos <r-rivera-matos@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The BQ25980, BQ25975, and BQ25960 are a series of flash chargers intended

9
Documentation/devicetree/bindings/power/supply/qcom,pm8941-charger.yaml
View File

@ -117,11 +117,18 @@ properties:
be done externally to fully comply with the JEITA safety guidelines if this flag
is set.
usb-charge-current-limit:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 100000
maximum: 2500000
description: |
Default USB charge current limit in uA.
usb-otg-in-supply:
description: Reference to the regulator supplying power to the USB_OTG_IN pin.
otg-vbus:
type: object
$ref: /schemas/regulator/regulator.yaml#
description: |
This node defines a regulator used to control the direction of VBUS voltage.
Specifically whether to supply voltage to VBUS for host mode operation of the OTG port,

2
Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml
View File

@ -82,7 +82,7 @@ properties:
- 1 # SMB3XX_SYSOK_INOK_ACTIVE_HIGH
usb-vbus:
$ref: "../../regulator/regulator.yaml#"
$ref: /schemas/regulator/regulator.yaml#
type: object
properties:

11
Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml
View File

@ -47,12 +47,6 @@ properties:
description:
Properties for single LDO regulator.
properties:
regulator-name:
pattern: "^LDO[1-5]$"
description:
should be "LDO1", ..., "LDO5"
unevaluatedProperties: false
"^BUCK[1-6]$":
@ -62,11 +56,6 @@ properties:
Properties for single BUCK regulator.
properties:
regulator-name:
pattern: "^BUCK[1-6]$"
description:
should be "BUCK1", ..., "BUCK6"
nxp,dvs-run-voltage:
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 600000

68
Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml Normal file
View File

@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/atmel,at91sam9260-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel/Microchip System Reset Controller
maintainers:
- Claudiu Beznea <claudiu.beznea@microchip.com>
description: |
The system reset controller can be used to reset the CPU. In case of
SAMA7G5 it can also reset some devices (e.g. USB PHYs).
properties:
compatible:
oneOf:
- items:
- enum:
- atmel,at91sam9260-rstc
- atmel,at91sam9g45-rstc
- atmel,sama5d3-rstc
- microchip,sam9x60-rstc
- microchip,sama7g5-rstc
- items:
- const: atmel,sama5d3-rstc
- const: atmel,at91sam9g45-rstc
reg:
minItems: 1
items:
- description: base registers for system reset control
- description: registers for device specific reset control
clocks:
maxItems: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
- clocks
allOf:
- if:
properties:
compatible:
contains:
enum:
- microchip,sama7g5-rstc
then:
required:
- "#reset-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/at91.h>
reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
};

5
Documentation/devicetree/bindings/riscv/cpus.yaml
View File

@ -63,6 +63,11 @@ properties:
- riscv,sv48
- riscv,none
riscv,cbom-block-size:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The blocksize in bytes for the Zicbom cache operations.
riscv,isa:
description:
Identifies the specific RISC-V instruction set architecture

6
Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
View File

@ -46,7 +46,7 @@ properties:
const: 2
cache-sets:
const: 1024
enum: [1024, 2048]
cache-size:
const: 2097152
@ -84,6 +84,8 @@ then:
description: |
Must contain entries for DirError, DataError and DataFail signals.
maxItems: 3
cache-sets:
const: 1024
else:
properties:
@ -91,6 +93,8 @@ else:
description: |
Must contain entries for DirError, DataError, DataFail, DirFail signals.
minItems: 4
cache-sets:
const: 2048
additionalProperties: false

1
Documentation/devicetree/bindings/rtc/microcrystal,rv3032.yaml
View File

@ -32,6 +32,7 @@ properties:
- 11000
trickle-voltage-millivolt:
$ref: /schemas/types.yaml#/definitions/uint32
enum:
- 1750
- 3000

45
Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml Normal file
View File

@ -0,0 +1,45 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/nuvoton,nct3018y.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NUVOTON NCT3018Y Real Time Clock
allOf:
- $ref: "rtc.yaml#"
maintainers:
- Medad CChien <ctcchien@nuvoton.com>
- Mia Lin <mimi05633@gmail.com>
properties:
compatible:
const: nuvoton,nct3018y
reg:
maxItems: 1
start-year: true
reset-source: true
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
rtc@6f {
compatible = "nuvoton,nct3018y";
reg = <0x6f>;
};
};
...

32
Documentation/devicetree/bindings/rtc/nxp,pcf85063.txt
View File

@ -1,32 +0,0 @@
* NXP PCF85063 Real Time Clock
Required properties:
- compatible: Should one of contain:
"nxp,pca85073a",
"nxp,pcf85063",
"nxp,pcf85063a",
"nxp,pcf85063tp",
"microcrystal,rv8263"
- reg: I2C address for chip.
Optional property:
- quartz-load-femtofarads: The capacitive load of the quartz(x-tal),
expressed in femto Farad (fF). Valid values are 7000 and 12500.
Default value (if no value is specified) is 7000fF.
Optional child node:
- clock: Provide this if the square wave pin is used as boot-enabled fixed clock.
Example:
pcf85063: rtc@51 {
compatible = "nxp,pcf85063";
reg = <0x51>;
quartz-load-femtofarads = <12500>;
clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};

92
Documentation/devicetree/bindings/rtc/nxp,pcf85063.yaml Normal file
View File

@ -0,0 +1,92 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/nxp,pcf85063.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP PCF85063 Real Time Clock
maintainers:
- Alexander Stein <alexander.stein@ew.tq-group.com>
properties:
compatible:
enum:
- microcrystal,rv8263
- nxp,pcf85063
- nxp,pcf85063a
- nxp,pcf85063tp
- nxp,pca85073a
reg:
maxItems: 1
"#clock-cells":
const: 0
clock-output-names:
maxItems: 1
interrupts:
maxItems: 1
quartz-load-femtofarads:
description:
The capacitive load of the quartz(x-tal).
enum: [7000, 12500]
default: 7000
clock:
$ref: /schemas/clock/fixed-clock.yaml
description:
Provide this if the square wave pin is used as boot-enabled
fixed clock.
wakeup-source: true
allOf:
- $ref: rtc.yaml#
- if:
properties:
compatible:
contains:
enum:
- microcrystal,rv8263
then:
properties:
quartz-load-femtofarads: false
- if:
properties:
compatible:
contains:
enum:
- nxp,pcf85063
then:
properties:
quartz-load-femtofarads:
const: 7000
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
rtc@51 {
compatible = "nxp,pcf85063a";
reg = <0x51>;
quartz-load-femtofarads = <12500>;
clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
};

2
Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm PM8xxx PMIC RTC device
maintainers:
- Satya Priya <skakit@codeaurora.org>
- Satya Priya <quic_c_skakit@quicinc.com>
properties:
compatible:

2
Documentation/devicetree/bindings/rtc/rtc-mt6397.txt
View File

@ -14,6 +14,8 @@ For MediaTek PMIC wrapper bus bindings, see:
Required properties:
- compatible: Should be one of follows
"mediatek,mt6323-rtc": for MT6323 PMIC
"mediatek,mt6358-rtc": for MT6358 PMIC
"mediatek,mt6366-rtc", "mediatek,mt6358-rtc": for MT6366 PMIC
"mediatek,mt6397-rtc": for MT6397 PMIC
Example:

62
Documentation/devicetree/bindings/rtc/ti,k3-rtc.yaml Normal file
View File

@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/ti,k3-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments K3 Real Time Clock
maintainers:
- Nishanth Menon <nm@ti.com>
description: |
This RTC appears in the AM62x family of SoCs.
allOf:
- $ref: "rtc.yaml#"
properties:
compatible:
enum:
- ti,am62-rtc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: VBUS Interface clock
- description: 32k Clock source (external or internal).
clock-names:
items:
- const: vbus
- const: osc32k
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
rtc@2b1f0000 {
compatible = "ti,am62-rtc";
reg = <0x2b1f0000 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&bar 0>;
clocks = <&foo 0>, <&foo 1>;
clock-names = "vbus", "osc32k";
wakeup-source;
};

12
Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
View File

@ -23,8 +23,15 @@ properties:
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: rtc
interrupts:
minItems: 2
maxItems: 2
interrupt-names:
items:
@ -39,6 +46,7 @@ properties:
minimum: 0x1
maximum: 0x1FFFFF
default: 0x198233
deprecated: true
required:
- compatible
@ -61,5 +69,7 @@ examples:
interrupts = <0 26 4>, <0 27 4>;
interrupt-names = "alarm", "sec";
calibration = <0x198233>;
clock-names = "rtc";
clocks = <&rtc_clk>;
};
};

2
Documentation/devicetree/bindings/sound/tas2562.yaml
View File

@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Texas Instruments TAS2562 Smart PA
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The TAS2562 is a mono, digital input Class-D audio amplifier optimized for

2
Documentation/devicetree/bindings/sound/tlv320adcx140.yaml
View File

@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
maintainers:
- Dan Murphy <dmurphy@ti.com>
- Andrew Davis <afd@ti.com>
description: |
The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital

2
Documentation/devicetree/bindings/spi/cdns,qspi-nor-peripheral-props.yaml
View File

@ -10,7 +10,7 @@ description:
See spi-peripheral-props.yaml for more info.
maintainers:
- Pratyush Yadav <p.yadav@ti.com>
- Vaishnav Achath <vaishnav.a@ti.com>
properties:
# cdns,qspi-nor.yaml

2
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence Quad SPI controller
maintainers:
- Pratyush Yadav <p.yadav@ti.com>
- Vaishnav Achath <vaishnav.a@ti.com>
allOf:
- $ref: spi-controller.yaml#

2
Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
View File

@ -16,7 +16,7 @@ description:
their own separate schema that should be referenced from here.
maintainers:
- Pratyush Yadav <p.yadav@ti.com>
- Mark Brown <broonie@kernel.org>
properties:
reg:

2
Documentation/devicetree/bindings/thermal/rcar-thermal.yaml
View File

@ -42,7 +42,7 @@ properties:
description:
Address ranges of the thermal registers. If more then one range is given
the first one must be the common registers followed by each sensor
according the datasheet.
according to the datasheet.
minItems: 1
maxItems: 4

4
Documentation/devicetree/bindings/virtio/mmio.yaml
View File

@ -33,6 +33,10 @@ properties:
description: Required for devices making accesses thru an IOMMU.
maxItems: 1
wakeup-source:
type: boolean
description: Required for setting irq of a virtio_mmio device as wakeup source.
required:
- compatible
- reg

11
Documentation/i2c/i2c-protocol.rst
View File

@ -2,7 +2,8 @@
The I2C Protocol
================
This document describes the I2C protocol. Or will, when it is finished :-)
This document is an overview of the basic I2C transactions and the kernel
APIs to perform them.
Key to symbols
==============
@ -12,13 +13,9 @@ S Start condition
P Stop condition
Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0.
A, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit
Addr (7 bits) I2C 7 bit address. Note that this can be expanded as usual to
Addr (7 bits) I2C 7 bit address. Note that this can be expanded to
get a 10 bit I2C address.
Comm (8 bits) Command byte, a data byte which often selects a register on
the device.
Data (8 bits) A plain data byte. Sometimes, I write DataLow, DataHigh
for 16 bit data.
Count (8 bits) A data byte containing the length of a block operation.
Data (8 bits) A plain data byte.
[..] Data sent by I2C device, as opposed to data sent by the
host adapter.

24
Documentation/i2c/i2c-sysfs.rst
View File

@ -51,11 +51,10 @@ Google Pixel 3 phone for example::
``i2c-2`` is an I2C bus whose number is 2, and ``2-0049`` is an I2C device
on bus 2 address 0x49 bound with a kernel driver.
Terminologies
=============
Terminology
===========
First, let us define a couple of terminologies to avoid confusions in the later
sections.
First, let us define some terms to avoid confusion in later sections.
(Physical) I2C Bus Controller
-----------------------------
@ -100,9 +99,7 @@ Caveat
This may be a confusing part for people who only know about the physical I2C
design of a board. It is actually possible to rename the I2C bus physical number
to a different number in logical I2C bus level in Device Tree Source (DTS) under
section ``aliases``. See
`arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
<../../arch/arm/boot/dts/nuvoton-npcm730-gsj.dts>`_
section ``aliases``. See ``arch/arm/boot/dts/nuvoton-npcm730-gsj.dts``
for an example of DTS file.
Best Practice: **(To kernel software developers)** It is better to keep the I2C
@ -117,7 +114,7 @@ Walk through Logical I2C Bus
For the following content, we will use a more complex I2C topology as an
example. Here is a brief graph for the I2C topology. If you do not understand
this graph at the first glance, do not be afraid to continue reading this doc
this graph at first glance, do not be afraid to continue reading this doc
and review it when you finish reading.
::
@ -290,8 +287,7 @@ MUX channel 0, and all the way to ``i2c-19`` for the MUX channel 3.
The kernel software developer is able to pin the fanout MUX channels to a static
logical I2C bus number in the DTS. This doc will not go through the details on
how to implement this in DTS, but we can see an example in:
`arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts
<../../arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts>`_
``arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts``
In the above example, there is an 8-channel I2C MUX at address 0x70 on physical
I2C bus 2. The channel 2 of the MUX is defined as ``imux18`` in DTS,
@ -383,13 +379,9 @@ Sysfs for the I2C sensor device::
For more info on the Hwmon Sysfs, refer to the doc:
`Naming and data format standards for sysfs files
<../hwmon/sysfs-interface.rst>`_
../hwmon/sysfs-interface.rst
Instantiate I2C Devices in I2C Sysfs
------------------------------------
Refer to the doc:
`How to instantiate I2C devices, Method 4: Instantiate from user-space
<instantiating-devices.rst#method-4-instantiate-from-user-space>`_
Refer to section "Method 4: Instantiate from user-space" of instantiating-devices.rst

16
Documentation/i2c/instantiating-devices.rst
View File

@ -31,7 +31,9 @@ Declare the I2C devices via devicetree
On platforms using devicetree, the declaration of I2C devices is done in
subnodes of the master controller.
Example::
Example:
.. code-block:: dts
i2c1: i2c@400a0000 {
/* ... master properties skipped ... */
@ -71,7 +73,9 @@ code. Instantiating I2C devices via board files is done with an array of
struct i2c_board_info which is registered by calling
i2c_register_board_info().
Example (from omap2 h4)::
Example (from omap2 h4):
.. code-block:: c
static struct i2c_board_info h4_i2c_board_info[] __initdata = {
{
@ -111,7 +115,9 @@ bus in advance, so the method 1 described above can't be used. Instead,
you can instantiate your I2C devices explicitly. This is done by filling
a struct i2c_board_info and calling i2c_new_client_device().
Example (from the sfe4001 network driver)::
Example (from the sfe4001 network driver):
.. code-block:: c
static struct i2c_board_info sfe4001_hwmon_info = {
I2C_BOARD_INFO("max6647", 0x4e),
@ -136,7 +142,9 @@ it may have different addresses from one board to the next (manufacturer
changing its design without notice). In this case, you can call
i2c_new_scanned_device() instead of i2c_new_client_device().
Example (from the nxp OHCI driver)::
Example (from the nxp OHCI driver):
.. code-block:: c
static const unsigned short normal_i2c[] = { 0x2c, 0x2d, I2C_CLIENT_END };

6
Documentation/i2c/smbus-protocol.rst
View File

@ -41,12 +41,12 @@ Sr Repeated start condition, used to switch from write to
P Stop condition
Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0.
A, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit
Addr (7 bits) I2C 7 bit address. Note that this can be expanded as usual to
Addr (7 bits) I2C 7 bit address. Note that this can be expanded to
get a 10 bit I2C address.
Comm (8 bits) Command byte, a data byte which often selects a register on
the device.
Data (8 bits) A plain data byte. Sometimes, I write DataLow, DataHigh
for 16 bit data.
Data (8 bits) A plain data byte. DataLow and DataHigh represent the low and
high byte of a 16 bit word.
Count (8 bits) A data byte containing the length of a block operation.
[..] Data sent by I2C device, as opposed to data sent by the host

2
Documentation/loongarch/introduction.rst
View File

@ -221,7 +221,7 @@ I26 Opcode + I26L + I26H
=========== ==========================
Rd is the destination register operand, while Rj, Rk and Ra ("a" stands for
"additional") are the source register operands. I8/I12/I16/I21/I26 are
"additional") are the source register operands. I8/I12/I14/I16/I21/I26 are
immediate operands of respective width. The longer I21 and I26 are stored
in separate higher and lower parts in the instruction word, denoted by the "L"
and "H" suffixes.

2
Documentation/tools/rtla/rtla-timerlat-hist.rst
View File

@ -33,7 +33,7 @@ EXAMPLE
=======
In the example below, **rtla timerlat hist** is set to run for *10* minutes,
in the cpus *0-4*, *skipping zero* only lines. Moreover, **rtla timerlat
hist** will change the priority of the *timelat* threads to run under
hist** will change the priority of the *timerlat* threads to run under
*SCHED_DEADLINE* priority, with a *10us* runtime every *1ms* period. The
*1ms* period is also passed to the *timerlat* tracer::

4
Documentation/translations/zh_CN/loongarch/introduction.rst
View File

@ -190,8 +190,8 @@ I26 Opcode + I26L + I26H
=========== ==========================
Opcode是指令操作码，Rj和Rk是源操作数（寄存器），Rd是目标操作数（寄存器），Ra是
4R-type格式特有的附加操作数（寄存器）。I8/I12/I16/I21/I26分别是8位/12位/16位/
21位/26位的立即数。其中较长的21位和26位立即数在指令字中被分割为高位部分与低位
4R-type格式特有的附加操作数（寄存器）。I8/I12/I14/I16/I21/I26分别是8位/12位/14位/
16位/21位/26位的立即数。其中较长的21位和26位立即数在指令字中被分割为高位部分与低位
部分，所以你们在这里的格式描述中能够看到I21L/I21H和I26L/I26H这样带后缀的表述。
指令列表

15
MAINTAINERS
View File

@ -264,6 +264,11 @@ W: http://www.adaptec.com/
F: Documentation/scsi/aacraid.rst
F: drivers/scsi/aacraid/
AB8500 BATTERY AND CHARGER DRIVERS
M: Linus Walleij <linus.walleij@linaro.org>
F: Documentation/devicetree/bindings/power/supply/*ab8500*
F: drivers/power/supply/*ab8500*
ABI/API
L: linux-api@vger.kernel.org
F: include/linux/syscalls.h
@ -2173,7 +2178,7 @@ M: Jean-Marie Verdun <verdun@hpe.com>
M: Nick Hawkins <nick.hawkins@hpe.com>
S: Maintained
F: Documentation/devicetree/bindings/arm/hpe,gxp.yaml
F: Documentation/devicetree/bindings/spi/hpe,gxp-spi.yaml
F: Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml
F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
F: arch/arm/boot/dts/hpe-bmc*
F: arch/arm/boot/dts/hpe-gxp*
@ -2481,11 +2486,13 @@ S: Supported
F: Documentation/devicetree/bindings/*/*/*npcm*
F: Documentation/devicetree/bindings/*/*npcm*
F: Documentation/devicetree/bindings/arm/npcm/*
F: Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml
F: arch/arm/boot/dts/nuvoton-npcm*
F: arch/arm/mach-npcm/
F: arch/arm64/boot/dts/nuvoton/
F: drivers/*/*npcm*
F: drivers/*/*/*npcm*
F: drivers/rtc/rtc-nct3018y.c
F: include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
F: include/dt-bindings/clock/nuvoton,npcm845-clk.h
@ -14461,6 +14468,7 @@ W: https://github.com/jonmason/ntb/wiki
T: git git://github.com/jonmason/ntb.git
F: drivers/net/ntb_netdev.c
F: drivers/ntb/
F: drivers/pci/endpoint/functions/pci-epf-*ntb.c
F: include/linux/ntb.h
F: include/linux/ntb_transport.h
F: tools/testing/selftests/ntb/
@ -16879,7 +16887,7 @@ M: Robert Foss <robert.foss@linaro.org>
L: linux-i2c@vger.kernel.org
L: linux-arm-msm@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt
F: Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
F: drivers/i2c/busses/i2c-qcom-cci.c
QUALCOMM INTERCONNECT BWMON DRIVER
@ -17524,6 +17532,7 @@ F: drivers/char/hw_random/mpfs-rng.c
F: drivers/clk/microchip/clk-mpfs.c
F: drivers/mailbox/mailbox-mpfs.c
F: drivers/pci/controller/pcie-microchip-host.c
F: drivers/rtc/rtc-mpfs.c
F: drivers/soc/microchip/
F: drivers/spi/spi-microchip-core.c
F: drivers/usb/musb/mpfs.c
@ -22191,12 +22200,14 @@ F: drivers/*/xen-*front.c
F: drivers/xen/
F: include/uapi/xen/
F: include/xen/
F: kernel/configs/xen.config
XEN HYPERVISOR X86
M: Juergen Gross <jgross@suse.com>
R: Boris Ostrovsky <boris.ostrovsky@oracle.com>
L: xen-devel@lists.xenproject.org (moderated for non-subscribers)
S: Supported
F: arch/x86/configs/xen.config
F: arch/x86/include/asm/pvclock-abi.h
F: arch/x86/include/asm/xen/
F: arch/x86/platform/pvh/

8
Makefile
View File

@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 5
PATCHLEVEL = 19
VERSION = 6
PATCHLEVEL = 0
SUBLEVEL = 0
EXTRAVERSION =
NAME = Superb Owl
EXTRAVERSION = -rc1
NAME = Hurr durr I'ma ninja sloth
# *DOCUMENTATION*
# To see a list of typical targets execute "make help"

18
arch/loongarch/Kconfig
View File

@ -2,7 +2,9 @@
config LOONGARCH
bool
default y
select ACPI
select ACPI_GENERIC_GSI if ACPI
select ACPI_MCFG if ACPI
select ACPI_SYSTEM_POWER_STATES_SUPPORT if ACPI
select ARCH_BINFMT_ELF_STATE
select ARCH_ENABLE_MEMORY_HOTPLUG
@ -40,6 +42,7 @@ config LOONGARCH
select ARCH_MIGHT_HAVE_PC_PARPORT
select ARCH_MIGHT_HAVE_PC_SERIO
select ARCH_SPARSEMEM_ENABLE
select ARCH_STACKWALK
select ARCH_SUPPORTS_ACPI
select ARCH_SUPPORTS_ATOMIC_RMW
select ARCH_SUPPORTS_HUGETLBFS
@ -51,6 +54,7 @@ config LOONGARCH
select ARCH_WANTS_NO_INSTR
select BUILDTIME_TABLE_SORT
select COMMON_CLK
select EFI
select GENERIC_CLOCKEVENTS
select GENERIC_CMOS_UPDATE
select GENERIC_CPU_AUTOPROBE
@ -86,6 +90,7 @@ config LOONGARCH
select HAVE_IRQ_TIME_ACCOUNTING
select HAVE_MOD_ARCH_SPECIFIC
select HAVE_NMI
select HAVE_PCI
select HAVE_PERF_EVENTS
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_RSEQ
@ -95,20 +100,27 @@ config LOONGARCH
select HAVE_VIRT_CPU_ACCOUNTING_GEN if !SMP
select IRQ_FORCED_THREADING
select IRQ_LOONGARCH_CPU
select MMU_GATHER_MERGE_VMAS if MMU
select MODULES_USE_ELF_RELA if MODULES
select NEED_PER_CPU_EMBED_FIRST_CHUNK
select NEED_PER_CPU_PAGE_FIRST_CHUNK
select OF
select OF_EARLY_FLATTREE
select PCI
select PCI_DOMAINS_GENERIC
select PCI_ECAM if ACPI
select PCI_LOONGSON
select PCI_MSI_ARCH_FALLBACKS
select PERF_USE_VMALLOC
select RTC_LIB
select SMP
select SPARSE_IRQ
select SYSCTL_EXCEPTION_TRACE
select SWIOTLB
select TRACE_IRQFLAGS_SUPPORT
select USE_PERCPU_NUMA_NODE_ID
select USER_STACKTRACE_SUPPORT
select ZONE_DMA32
select MMU_GATHER_MERGE_VMAS if MMU
config 32BIT
bool
@ -141,6 +153,10 @@ config LOCKDEP_SUPPORT
bool
default y
config STACKTRACE_SUPPORT
bool
default y
# MACH_LOONGSON32 and MACH_LOONGSON64 are delibrately carried over from the
# MIPS Loongson code, to preserve Loongson-specific code paths in drivers that
# are shared between architectures, and specifically expecting the symbols.

29
arch/loongarch/Kconfig.debug
View File

@ -0,0 +1,29 @@
choice
prompt "Choose kernel unwinder"
default UNWINDER_PROLOGUE if KALLSYMS
help
This determines which method will be used for unwinding kernel stack
traces for panics, oopses, bugs, warnings, perf, /proc/<pid>/stack,
lockdep, and more.
config UNWINDER_GUESS
bool "Guess unwinder"
help
This option enables the "guess" unwinder for unwinding kernel stack
traces. It scans the stack and reports every kernel text address it
finds. Some of the addresses it reports may be incorrect.
While this option often produces false positives, it can still be
useful in many cases.
config UNWINDER_PROLOGUE
bool "Prologue unwinder"
depends on KALLSYMS
help
This option enables the "prologue" unwinder for unwinding kernel stack
traces. It unwind the stack frame based on prologue code analyze. Symbol
information is needed, at least the address and length of each function.
Some of the addresses it reports may be incorrect (but better than the
Guess unwinder).
endchoice

2
arch/loongarch/Makefile
View File

@ -47,6 +47,8 @@ cflags-y += $(call cc-option, -mno-check-zero-division)
load-y = 0x9000000000200000
bootvars-y = VMLINUX_LOAD_ADDRESS=$(load-y)
drivers-$(CONFIG_PCI) += arch/loongarch/pci/
KBUILD_AFLAGS += $(cflags-y)
KBUILD_CFLAGS += $(cflags-y)
KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y)

34
arch/loongarch/configs/loongson3_defconfig
View File

@ -278,6 +278,8 @@ CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_BPF=m
CONFIG_OPENVSWITCH=m
CONFIG_VSOCKETS=m
CONFIG_VIRTIO_VSOCKETS=m
CONFIG_NETLINK_DIAG=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_BT=m
@ -289,6 +291,7 @@ CONFIG_MAC80211=m
CONFIG_RFKILL=m
CONFIG_RFKILL_INPUT=y
CONFIG_NET_9P=y
CONFIG_NET_9P_VIRTIO=y
CONFIG_CEPH_LIB=m
CONFIG_PCIEPORTBUS=y
CONFIG_HOTPLUG_PCI_PCIE=y
@ -308,6 +311,8 @@ CONFIG_RAPIDIO_MPORT_CDEV=m
CONFIG_UEVENT_HELPER=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_FW_LOADER_COMPRESS=y
CONFIG_FW_LOADER_COMPRESS_ZSTD=y
CONFIG_MTD=m
CONFIG_MTD_BLOCK=m
CONFIG_MTD_CFI=m
@ -328,8 +333,19 @@ CONFIG_BLK_DEV_CRYPTOLOOP=y
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_VIRTIO_BLK=y
CONFIG_BLK_DEV_RBD=m
CONFIG_BLK_DEV_NVME=y
CONFIG_NVME_MULTIPATH=y
CONFIG_NVME_RDMA=m
CONFIG_NVME_FC=m
CONFIG_NVME_TCP=m
CONFIG_NVME_TARGET=m
CONFIG_NVME_TARGET_PASSTHRU=y
CONFIG_NVME_TARGET_LOOP=m
CONFIG_NVME_TARGET_RDMA=m
CONFIG_NVME_TARGET_FC=m
CONFIG_NVME_TARGET_TCP=m
CONFIG_EEPROM_AT24=m
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=y
@ -359,6 +375,7 @@ CONFIG_SCSI_QLA_FC=m
CONFIG_TCM_QLA2XXX=m
CONFIG_SCSI_QLA_ISCSI=m
CONFIG_SCSI_LPFC=m
CONFIG_SCSI_VIRTIO=m
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_SATA_AHCI_PLATFORM=y
@ -403,6 +420,7 @@ CONFIG_VXLAN=y
CONFIG_RIONET=m
CONFIG_TUN=m
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
@ -527,10 +545,12 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_NONSTANDARD=y
CONFIG_PRINTER=m
CONFIG_VIRTIO_CONSOLE=y
CONFIG_IPMI_HANDLER=m
CONFIG_IPMI_DEVICE_INTERFACE=m
CONFIG_IPMI_SI=m
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_PIIX4=y
CONFIG_I2C_GPIO=y
@ -568,6 +588,8 @@ CONFIG_DRM_AMDGPU_SI=y
CONFIG_DRM_AMDGPU_CIK=y
CONFIG_DRM_AMDGPU_USERPTR=y
CONFIG_DRM_AST=y
CONFIG_DRM_QXL=m
CONFIG_DRM_VIRTIO_GPU=m
CONFIG_FB=y
CONFIG_FB_EFI=y
CONFIG_FB_RADEON=y
@ -637,7 +659,16 @@ CONFIG_UIO=m
CONFIG_UIO_PDRV_GENIRQ=m
CONFIG_UIO_DMEM_GENIRQ=m
CONFIG_UIO_PCI_GENERIC=m
# CONFIG_VIRTIO_MENU is not set
CONFIG_VFIO=m
CONFIG_VFIO_PCI=m
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_SCSI=m
CONFIG_VHOST_VSOCK=m
CONFIG_COMEDI=m
CONFIG_COMEDI_PCI_DRIVERS=m
CONFIG_COMEDI_8255_PCI=m
@ -762,6 +793,7 @@ CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
CONFIG_CRYPTO_USER_API_RNG=m
CONFIG_CRYPTO_USER_API_AEAD=m
CONFIG_CRYPTO_DEV_VIRTIO=m
CONFIG_PRINTK_TIME=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_MAGIC_SYSRQ=y

2
arch/loongarch/include/asm/bootinfo.h
View File

@ -28,10 +28,10 @@ struct loongson_board_info {
struct loongson_system_configuration {
int nr_cpus;
int nr_nodes;
int nr_io_pics;
int boot_cpu_id;
int cores_per_node;
int cores_per_package;
unsigned long cores_io_master;
const char *cpuname;
};

11
arch/loongarch/include/asm/dma.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
*/
#ifndef __ASM_DMA_H
#define __ASM_DMA_H
#define MAX_DMA_ADDRESS PAGE_OFFSET
#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
#endif

52
arch/loongarch/include/asm/inst.h
View File

@ -23,12 +23,33 @@ enum reg1i20_op {
lu32id_op = 0x0b,
};
enum reg1i21_op {
beqz_op = 0x10,
bnez_op = 0x11,
};
enum reg2i12_op {
addiw_op = 0x0a,
addid_op = 0x0b,
lu52id_op = 0x0c,
ldb_op = 0xa0,
ldh_op = 0xa1,
ldw_op = 0xa2,
ldd_op = 0xa3,
stb_op = 0xa4,
sth_op = 0xa5,
stw_op = 0xa6,
std_op = 0xa7,
};
enum reg2i16_op {
jirl_op = 0x13,
beq_op = 0x16,
bne_op = 0x17,
blt_op = 0x18,
bge_op = 0x19,
bltu_op = 0x1a,
bgeu_op = 0x1b,
};
struct reg0i26_format {
@ -110,6 +131,37 @@ enum loongarch_gpr {
LOONGARCH_GPR_MAX
};
#define is_imm12_negative(val) is_imm_negative(val, 12)
static inline bool is_imm_negative(unsigned long val, unsigned int bit)
{
return val & (1UL << (bit - 1));
}
static inline bool is_branch_ins(union loongarch_instruction *ip)
{
return ip->reg1i21_format.opcode >= beqz_op &&
ip->reg1i21_format.opcode <= bgeu_op;
}
static inline bool is_ra_save_ins(union loongarch_instruction *ip)
{
/* st.d $ra, $sp, offset */
return ip->reg2i12_format.opcode == std_op &&
ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
ip->reg2i12_format.rd == LOONGARCH_GPR_RA &&
!is_imm12_negative(ip->reg2i12_format.immediate);
}
static inline bool is_stack_alloc_ins(union loongarch_instruction *ip)
{
/* addi.d $sp, $sp, -imm */
return ip->reg2i12_format.opcode == addid_op &&
ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
ip->reg2i12_format.rd == LOONGARCH_GPR_SP &&
is_imm12_negative(ip->reg2i12_format.immediate);
}
u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, unsigned long pc, unsigned long dest);

10
arch/loongarch/include/asm/irq.h
View File

@ -82,8 +82,6 @@ extern struct acpi_vector_group msi_group[MAX_IO_PICS];
#define GSI_MAX_PCH_IRQ (LOONGSON_PCH_IRQ_BASE + 256 - 1)
extern int find_pch_pic(u32 gsi);
extern int eiointc_get_node(int id);
struct acpi_madt_lio_pic;
struct acpi_madt_eio_pic;
struct acpi_madt_ht_pic;
@ -100,16 +98,8 @@ struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
struct acpi_madt_ht_pic *acpi_htvec);
int pch_lpc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lpc_pic *acpi_pchlpc);
#if IS_ENABLED(CONFIG_LOONGSON_PCH_MSI)
int pch_msi_acpi_init(struct irq_domain *parent,
struct acpi_madt_msi_pic *acpi_pchmsi);
#else
static inline int pch_msi_acpi_init(struct irq_domain *parent,
struct acpi_madt_msi_pic *acpi_pchmsi)
{
return 0;
}
#endif
int pch_pic_acpi_init(struct irq_domain *parent,
struct acpi_madt_bio_pic *acpi_pchpic);
int find_pch_pic(u32 gsi);

2
arch/loongarch/include/asm/page.h
View File

@ -33,8 +33,6 @@
#include <linux/kernel.h>
#include <linux/pfn.h>
#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
/*
* It's normally defined only for FLATMEM config but it's
* used in our early mem init code for all memory models.

25
arch/loongarch/include/asm/pci.h Normal file
View File

@ -0,0 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
*/
#ifndef _ASM_PCI_H
#define _ASM_PCI_H
#include <linux/ioport.h>
#include <linux/list.h>
#include <linux/types.h>
#include <asm/io.h>
#define PCIBIOS_MIN_IO 0x4000
#define PCIBIOS_MIN_MEM 0x20000000
#define PCIBIOS_MIN_CARDBUS_IO 0x4000
#define HAVE_PCI_MMAP
#define pcibios_assign_all_busses() 0
extern phys_addr_t mcfg_addr_init(int node);
/* generic pci stuff */
#include <asm-generic/pci.h>
#endif /* _ASM_PCI_H */

9
arch/loongarch/include/asm/processor.h
View File

@ -101,6 +101,10 @@ struct thread_struct {
unsigned long reg23, reg24, reg25, reg26; /* s0-s3 */
unsigned long reg27, reg28, reg29, reg30, reg31; /* s4-s8 */
/* __schedule() return address / call frame address */
unsigned long sched_ra;
unsigned long sched_cfa;
/* CSR registers */
unsigned long csr_prmd;
unsigned long csr_crmd;
@ -129,6 +133,9 @@ struct thread_struct {
struct loongarch_fpu fpu FPU_ALIGN;
};
#define thread_saved_ra(tsk) (tsk->thread.sched_ra)
#define thread_saved_fp(tsk) (tsk->thread.sched_cfa)
#define INIT_THREAD { \
/* \
* Main processor registers \
@ -145,6 +152,8 @@ struct thread_struct {
.reg29 = 0, \
.reg30 = 0, \
.reg31 = 0, \
.sched_ra = 0, \
.sched_cfa = 0, \
.csr_crmd = 0, \
.csr_prmd = 0, \
.csr_euen = 0, \

20
arch/loongarch/include/asm/stacktrace.h
View File

@ -10,6 +10,26 @@
#include <asm/loongarch.h>
#include <linux/stringify.h>
enum stack_type {
STACK_TYPE_UNKNOWN,
STACK_TYPE_IRQ,
STACK_TYPE_TASK,
};
struct stack_info {
enum stack_type type;
unsigned long begin, end, next_sp;
};
struct stack_frame {
unsigned long fp;
unsigned long ra;
};
bool in_irq_stack(unsigned long stack, struct stack_info *info);
bool in_task_stack(unsigned long stack, struct task_struct *task, struct stack_info *info);
int get_stack_info(unsigned long stack, struct task_struct *task, struct stack_info *info);
#define STR_LONG_L __stringify(LONG_L)
#define STR_LONG_S __stringify(LONG_S)
#define STR_LONGSIZE __stringify(LONGSIZE)

14
arch/loongarch/include/asm/switch_to.h
View File

@ -15,12 +15,15 @@ struct task_struct;
* @prev: The task previously executed.
* @next: The task to begin executing.
* @next_ti: task_thread_info(next).
* @sched_ra: __schedule return address.
* @sched_cfa: __schedule call frame address.
*
* This function is used whilst scheduling to save the context of prev & load
* the context of next. Returns prev.
*/
extern asmlinkage struct task_struct *__switch_to(struct task_struct *prev,
struct task_struct *next, struct thread_info *next_ti);
struct task_struct *next, struct thread_info *next_ti,
void *sched_ra, void *sched_cfa);
/*
* For newly created kernel threads switch_to() will return to
@ -28,10 +31,11 @@ extern asmlinkage struct task_struct *__switch_to(struct task_struct *prev,
* That is, everything following __switch_to() will be skipped for new threads.
* So everything that matters to new threads should be placed before __switch_to().
*/
#define switch_to(prev, next, last) \
do { \
lose_fpu_inatomic(1, prev); \
(last) = __switch_to(prev, next, task_thread_info(next)); \
#define switch_to(prev, next, last) \
do { \
lose_fpu_inatomic(1, prev); \
(last) = __switch_to(prev, next, task_thread_info(next), \
__builtin_return_address(0), __builtin_frame_address(0)); \
} while (0)
#endif /* _ASM_SWITCH_TO_H */

4
arch/loongarch/include/asm/uaccess.h
View File

@ -229,13 +229,13 @@ extern unsigned long __copy_user(void *to, const void *from, __kernel_size_t n);
static inline unsigned long __must_check
raw_copy_from_user(void *to, const void __user *from, unsigned long n)
{
return __copy_user(to, from, n);
return __copy_user(to, (__force const void *)from, n);
}
static inline unsigned long __must_check
raw_copy_to_user(void __user *to, const void *from, unsigned long n)
{
return __copy_user(to, from, n);
return __copy_user((__force void *)to, from, n);
}
#define INLINE_COPY_FROM_USER

42
arch/loongarch/include/asm/unwind.h Normal file
View File

@ -0,0 +1,42 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Most of this ideas comes from x86.
*
* Copyright (C) 2022 Loongson Technology Corporation Limited
*/
#ifndef _ASM_UNWIND_H
#define _ASM_UNWIND_H
#include <linux/sched.h>
#include <asm/stacktrace.h>
enum unwinder_type {
UNWINDER_GUESS,
UNWINDER_PROLOGUE,
};
struct unwind_state {
char type; /* UNWINDER_XXX */
struct stack_info stack_info;
struct task_struct *task;
bool first, error;
unsigned long sp, pc, ra;
};
void unwind_start(struct unwind_state *state,
struct task_struct *task, struct pt_regs *regs);
bool unwind_next_frame(struct unwind_state *state);
unsigned long unwind_get_return_address(struct unwind_state *state);
static inline bool unwind_done(struct unwind_state *state)
{
return state->stack_info.type == STACK_TYPE_UNKNOWN;
}
static inline bool unwind_error(struct unwind_state *state)
{
return state->error;
}
#endif /* _ASM_UNWIND_H */

1
arch/loongarch/include/asm/vdso.h
View File

@ -7,6 +7,7 @@
#ifndef __ASM_VDSO_H
#define __ASM_VDSO_H
#include <linux/mm.h>
#include <linux/mm_types.h>
#include <vdso/datapage.h>

15
arch/loongarch/include/asm/vdso/vdso.h
View File

@ -8,6 +8,18 @@
#include <asm/asm.h>
#include <asm/page.h>
#include <asm/vdso.h>
struct vdso_pcpu_data {
u32 node;
} ____cacheline_aligned_in_smp;
struct loongarch_vdso_data {
struct vdso_pcpu_data pdata[NR_CPUS];
struct vdso_data data[CS_BASES]; /* Arch-independent data */
};
#define VDSO_DATA_SIZE PAGE_ALIGN(sizeof(struct loongarch_vdso_data))
static inline unsigned long get_vdso_base(void)
{
@ -24,7 +36,8 @@ static inline unsigned long get_vdso_base(void)
static inline const struct vdso_data *get_vdso_data(void)
{
return (const struct vdso_data *)(get_vdso_base() - PAGE_SIZE);
return (const struct vdso_data *)(get_vdso_base()
- VDSO_DATA_SIZE + SMP_CACHE_BYTES * NR_CPUS);
}
#endif /* __ASSEMBLY__ */

4
arch/loongarch/kernel/Makefile
View File

@ -15,6 +15,7 @@ obj-$(CONFIG_EFI) += efi.o
obj-$(CONFIG_CPU_HAS_FPU) += fpu.o
obj-$(CONFIG_MODULES) += module.o module-sections.o
obj-$(CONFIG_STACKTRACE) += stacktrace.o
obj-$(CONFIG_PROC_FS) += proc.o
@ -22,4 +23,7 @@ obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_NUMA) += numa.o
obj-$(CONFIG_UNWINDER_GUESS) += unwind_guess.o
obj-$(CONFIG_UNWINDER_PROLOGUE) += unwind_prologue.o
CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)

38
arch/loongarch/kernel/acpi.c
View File

@ -104,6 +104,39 @@ static int set_processor_mask(u32 id, u32 flags)
}
#endif
static int __init
acpi_parse_processor(union acpi_subtable_headers *header, const unsigned long end)
{
struct acpi_madt_core_pic *processor = NULL;
processor = (struct acpi_madt_core_pic *)header;
if (BAD_MADT_ENTRY(processor, end))
return -EINVAL;
acpi_table_print_madt_entry(&header->common);
#ifdef CONFIG_SMP
set_processor_mask(processor->core_id, processor->flags);
#endif
return 0;
}
static int __init
acpi_parse_eio_master(union acpi_subtable_headers *header, const unsigned long end)
{
static int core = 0;
struct acpi_madt_eio_pic *eiointc = NULL;
eiointc = (struct acpi_madt_eio_pic *)header;
if (BAD_MADT_ENTRY(eiointc, end))
return -EINVAL;
core = eiointc->node * CORES_PER_EIO_NODE;
set_bit(core, &(loongson_sysconf.cores_io_master));
return 0;
}
static void __init acpi_process_madt(void)
{
#ifdef CONFIG_SMP
@ -114,6 +147,11 @@ static void __init acpi_process_madt(void)
__cpu_logical_map[i] = -1;
}
#endif
acpi_table_parse_madt(ACPI_MADT_TYPE_CORE_PIC,
acpi_parse_processor, MAX_CORE_PIC);
acpi_table_parse_madt(ACPI_MADT_TYPE_EIO_PIC,
acpi_parse_eio_master, MAX_IO_PICS);
loongson_sysconf.nr_cpus = num_processors;
}

2
arch/loongarch/kernel/asm-offsets.c
View File

@ -103,6 +103,8 @@ void output_thread_defines(void)
OFFSET(THREAD_REG29, task_struct, thread.reg29);
OFFSET(THREAD_REG30, task_struct, thread.reg30);
OFFSET(THREAD_REG31, task_struct, thread.reg31);
OFFSET(THREAD_SCHED_RA, task_struct, thread.sched_ra);
OFFSET(THREAD_SCHED_CFA, task_struct, thread.sched_cfa);
OFFSET(THREAD_CSRCRMD, task_struct,
thread.csr_crmd);
OFFSET(THREAD_CSRPRMD, task_struct,

19
arch/loongarch/kernel/head.S
View File

@ -21,6 +21,12 @@ SYM_CODE_START(kernel_entry) # kernel entry point
csrwr t0, LOONGARCH_CSR_DMWIN0
li.d t0, CSR_DMW1_INIT # CA, PLV0, 0x9000 xxxx xxxx xxxx
csrwr t0, LOONGARCH_CSR_DMWIN1
/* We might not get launched at the address the kernel is linked to,
so we jump there. */
la.abs t0, 0f
jr t0
0:
/* Enable PG */
li.w t0, 0xb0 # PLV=0, IE=0, PG=1
csrwr t0, LOONGARCH_CSR_CRMD
@ -29,11 +35,6 @@ SYM_CODE_START(kernel_entry) # kernel entry point
li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0
csrwr t0, LOONGARCH_CSR_EUEN
/* We might not get launched at the address the kernel is linked to,
so we jump there. */
la.abs t0, 0f
jr t0
0:
la t0, __bss_start # clear .bss
st.d zero, t0, 0
la t1, __bss_stop - LONGSIZE
@ -74,6 +75,11 @@ SYM_CODE_START(smpboot_entry)
csrwr t0, LOONGARCH_CSR_DMWIN0
li.d t0, CSR_DMW1_INIT # CA, PLV0
csrwr t0, LOONGARCH_CSR_DMWIN1
la.abs t0, 0f
jr t0
0:
/* Enable PG */
li.w t0, 0xb0 # PLV=0, IE=0, PG=1
csrwr t0, LOONGARCH_CSR_CRMD
li.w t0, 0x04 # PLV=0, PIE=1, PWE=0
@ -85,9 +91,6 @@ SYM_CODE_START(smpboot_entry)
ld.d sp, t0, CPU_BOOT_STACK
ld.d tp, t0, CPU_BOOT_TINFO
la.abs t0, 0f
jr t0
0:
bl start_secondary
SYM_CODE_END(smpboot_entry)

2
arch/loongarch/kernel/proc.c
View File

@ -106,7 +106,7 @@ static void *c_start(struct seq_file *m, loff_t *pos)
{
unsigned long i = *pos;
return i < NR_CPUS ? (void *)(i + 1) : NULL;
return i < nr_cpu_ids ? (void *)(i + 1) : NULL;
}
static void *c_next(struct seq_file *m, void *v, loff_t *pos)

90
arch/loongarch/kernel/process.c
View File

@ -44,6 +44,7 @@
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/reg.h>
#include <asm/unwind.h>
#include <asm/vdso.h>
/*
@ -134,6 +135,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
childregs = (struct pt_regs *) childksp - 1;
/* Put the stack after the struct pt_regs. */
childksp = (unsigned long) childregs;
p->thread.sched_cfa = 0;
p->thread.csr_euen = 0;
p->thread.csr_crmd = csr_read32(LOONGARCH_CSR_CRMD);
p->thread.csr_prmd = csr_read32(LOONGARCH_CSR_PRMD);
@ -144,6 +146,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
p->thread.reg23 = (unsigned long)args->fn;
p->thread.reg24 = (unsigned long)args->fn_arg;
p->thread.reg01 = (unsigned long)ret_from_kernel_thread;
p->thread.sched_ra = (unsigned long)ret_from_kernel_thread;
memset(childregs, 0, sizeof(struct pt_regs));
childregs->csr_euen = p->thread.csr_euen;
childregs->csr_crmd = p->thread.csr_crmd;
@ -160,6 +163,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
p->thread.reg03 = (unsigned long) childregs;
p->thread.reg01 = (unsigned long) ret_from_fork;
p->thread.sched_ra = (unsigned long) ret_from_fork;
/*
* New tasks lose permission to use the fpu. This accelerates context
@ -180,7 +184,91 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
unsigned long __get_wchan(struct task_struct *task)
{
return 0;
unsigned long pc;
struct unwind_state state;
if (!try_get_task_stack(task))
return 0;
unwind_start(&state, task, NULL);
state.sp = thread_saved_fp(task);
get_stack_info(state.sp, state.task, &state.stack_info);
state.pc = thread_saved_ra(task);
#ifdef CONFIG_UNWINDER_PROLOGUE
state.type = UNWINDER_PROLOGUE;
#endif
for (; !unwind_done(&state); unwind_next_frame(&state)) {
pc = unwind_get_return_address(&state);
if (!pc)
break;
if (in_sched_functions(pc))
continue;
break;
}
put_task_stack(task);
return pc;
}
bool in_irq_stack(unsigned long stack, struct stack_info *info)
{
unsigned long nextsp;
unsigned long begin = (unsigned long)this_cpu_read(irq_stack);
unsigned long end = begin + IRQ_STACK_START;
if (stack < begin || stack >= end)
return false;
nextsp = *(unsigned long *)end;
if (nextsp & (SZREG - 1))
return false;
info->begin = begin;
info->end = end;
info->next_sp = nextsp;
info->type = STACK_TYPE_IRQ;
return true;
}
bool in_task_stack(unsigned long stack, struct task_struct *task,
struct stack_info *info)
{
unsigned long begin = (unsigned long)task_stack_page(task);
unsigned long end = begin + THREAD_SIZE - 32;
if (stack < begin || stack >= end)
return false;
info->begin = begin;
info->end = end;
info->next_sp = 0;
info->type = STACK_TYPE_TASK;
return true;
}
int get_stack_info(unsigned long stack, struct task_struct *task,
struct stack_info *info)
{
task = task ? : current;
if (!stack || stack & (SZREG - 1))
goto unknown;
if (in_task_stack(stack, task, info))
return 0;
if (task != current)
goto unknown;
if (in_irq_stack(stack, info))
return 0;
unknown:
info->type = STACK_TYPE_UNKNOWN;
return -EINVAL;
}
unsigned long stack_top(void)

5
arch/loongarch/kernel/smp.c
View File

@ -242,10 +242,7 @@ void loongson3_smp_finish(void)
static bool io_master(int cpu)
{
if (cpu == 0)
return true;
return false;
return test_bit(cpu, &loongson_sysconf.cores_io_master);
}
int loongson3_cpu_disable(void)

78
arch/loongarch/kernel/stacktrace.c Normal file
View File

@ -0,0 +1,78 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Stack trace management functions
*
* Copyright (C) 2022 Loongson Technology Corporation Limited
*/
#include <linux/sched.h>
#include <linux/stacktrace.h>
#include <linux/uaccess.h>
#include <asm/stacktrace.h>
#include <asm/unwind.h>
void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie,
struct task_struct *task, struct pt_regs *regs)
{
unsigned long addr;
struct pt_regs dummyregs;
struct unwind_state state;
regs = &dummyregs;
if (task == current) {
regs->regs[3] = (unsigned long)__builtin_frame_address(0);
regs->csr_era = (unsigned long)__builtin_return_address(0);
} else {
regs->regs[3] = thread_saved_fp(task);
regs->csr_era = thread_saved_ra(task);
}
regs->regs[1] = 0;
for (unwind_start(&state, task, regs);
!unwind_done(&state); unwind_next_frame(&state)) {
addr = unwind_get_return_address(&state);
if (!addr || !consume_entry(cookie, addr))
break;
}
}
static int
copy_stack_frame(unsigned long fp, struct stack_frame *frame)
{
int ret = 1;
unsigned long err;
unsigned long __user *user_frame_tail;
user_frame_tail = (unsigned long *)(fp - sizeof(struct stack_frame));
if (!access_ok(user_frame_tail, sizeof(*frame)))
return 0;
pagefault_disable();
err = (__copy_from_user_inatomic(frame, user_frame_tail, sizeof(*frame)));
if (err || (unsigned long)user_frame_tail >= frame->fp)
ret = 0;
pagefault_enable();
return ret;
}
void arch_stack_walk_user(stack_trace_consume_fn consume_entry, void *cookie,
const struct pt_regs *regs)
{
unsigned long fp = regs->regs[22];
while (fp && !((unsigned long)fp & 0xf)) {
struct stack_frame frame;
frame.fp = 0;
frame.ra = 0;
if (!copy_stack_frame(fp, &frame))
break;
if (!frame.ra)
break;
if (!consume_entry(cookie, frame.ra))
break;
fp = frame.fp;
}
}

Some files were not shown because too many files have changed in this diff Show More