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clk: sifive: Fix the wrong bit field shift

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The clk enable bit should be 31 instead of 24.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reported-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Link: https://lore.kernel.org/r/20201209094916.17383-5-zong.li@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Zong Li 2020-12-09 17:49:15 +08:00 committed by Stephen Boyd
parent efc91ae43c
commit 263ac39085
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/sifive/sifive-prci.h
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@ -59,7 +59,7 @@
/* DDRPLLCFG1 */ /* DDRPLLCFG1 */
#define PRCI_DDRPLLCFG1_OFFSET 0x10 #define PRCI_DDRPLLCFG1_OFFSET 0x10
#define PRCI_DDRPLLCFG1_CKE_SHIFT 24 #define PRCI_DDRPLLCFG1_CKE_SHIFT 31
#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
/* GEMGXLPLLCFG0 */ /* GEMGXLPLLCFG0 */
@ -81,7 +81,7 @@
/* GEMGXLPLLCFG1 */ /* GEMGXLPLLCFG1 */
#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24 #define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
/* CORECLKSEL */ /* CORECLKSEL */