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serial/mpc52xx_uart: prepare for adding MPC5125 PSC UART support
MPC5125 PSC controller has different register layout than MPC5121. To support MPC5125 PSC in this driver we have to provide further psc_ops functions for SoC specific register accesses. Add new register access functions to the psc_ops structure and provide MPC52xx and MPC512x specific implementation for them. Then replace remaining direct register accesses in the driver by appropriate psc_ops function calls. The subsequent patch can now add MPC5125 specific set of psc_ops functions. Signed-off-by: Vladimir Ermakov <vooon341@gmail.com> Signed-off-by: Matteo Facchinetti <matteo.facchinetti@sirius-es.it> Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Matteo Facchinetti
Greg Kroah-Hartman
parent
696faedd61
commit
2574b27eee
@ -112,6 +112,15 @@ struct psc_ops {
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void (*fifoc_uninit)(void);
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void (*get_irq)(struct uart_port *, struct device_node *);
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irqreturn_t (*handle_irq)(struct uart_port *port);
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u16 (*get_status)(struct uart_port *port);
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u8 (*get_ipcr)(struct uart_port *port);
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void (*command)(struct uart_port *port, u8 cmd);
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void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2);
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void (*set_rts)(struct uart_port *port, int state);
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void (*enable_ms)(struct uart_port *port);
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void (*set_sicr)(struct uart_port *port, u32 val);
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void (*set_imr)(struct uart_port *port, u16 val);
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u8 (*get_mr1)(struct uart_port *port);
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};
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/* setting the prescaler and divisor reg is common for all chips */
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@ -124,6 +133,65 @@ static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
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out_8(&psc->ctlr, divisor & 0xff);
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}
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static u16 mpc52xx_psc_get_status(struct uart_port *port)
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{
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return in_be16(&PSC(port)->mpc52xx_psc_status);
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}
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static u8 mpc52xx_psc_get_ipcr(struct uart_port *port)
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{
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return in_8(&PSC(port)->mpc52xx_psc_ipcr);
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}
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static void mpc52xx_psc_command(struct uart_port *port, u8 cmd)
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{
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out_8(&PSC(port)->command, cmd);
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}
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static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
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{
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out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
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out_8(&PSC(port)->mode, mr1);
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out_8(&PSC(port)->mode, mr2);
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}
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static void mpc52xx_psc_set_rts(struct uart_port *port, int state)
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{
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if (state)
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out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
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else
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out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
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}
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static void mpc52xx_psc_enable_ms(struct uart_port *port)
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{
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struct mpc52xx_psc __iomem *psc = PSC(port);
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/* clear D_*-bits by reading them */
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in_8(&psc->mpc52xx_psc_ipcr);
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/* enable CTS and DCD as IPC interrupts */
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out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
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port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
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out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
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}
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static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val)
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{
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out_be32(&PSC(port)->sicr, val);
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}
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static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val)
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{
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out_be16(&PSC(port)->mpc52xx_psc_imr, val);
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}
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static u8 mpc52xx_psc_get_mr1(struct uart_port *port)
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{
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out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
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return in_8(&PSC(port)->mode);
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}
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#ifdef CONFIG_PPC_MPC52xx
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#define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
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static void mpc52xx_psc_fifo_init(struct uart_port *port)
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@ -294,6 +362,15 @@ static struct psc_ops mpc52xx_psc_ops = {
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.set_baudrate = mpc5200_psc_set_baudrate,
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.get_irq = mpc52xx_psc_get_irq,
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.handle_irq = mpc52xx_psc_handle_irq,
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.get_status = mpc52xx_psc_get_status,
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.get_ipcr = mpc52xx_psc_get_ipcr,
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.command = mpc52xx_psc_command,
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.set_mode = mpc52xx_psc_set_mode,
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.set_rts = mpc52xx_psc_set_rts,
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.enable_ms = mpc52xx_psc_enable_ms,
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.set_sicr = mpc52xx_psc_set_sicr,
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.set_imr = mpc52xx_psc_set_imr,
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.get_mr1 = mpc52xx_psc_get_mr1,
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};
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static struct psc_ops mpc5200b_psc_ops = {
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@ -315,6 +392,15 @@ static struct psc_ops mpc5200b_psc_ops = {
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.set_baudrate = mpc5200b_psc_set_baudrate,
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.get_irq = mpc52xx_psc_get_irq,
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.handle_irq = mpc52xx_psc_handle_irq,
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.get_status = mpc52xx_psc_get_status,
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.get_ipcr = mpc52xx_psc_get_ipcr,
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.command = mpc52xx_psc_command,
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.set_mode = mpc52xx_psc_set_mode,
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.set_rts = mpc52xx_psc_set_rts,
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.enable_ms = mpc52xx_psc_enable_ms,
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.set_sicr = mpc52xx_psc_set_sicr,
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.set_imr = mpc52xx_psc_set_imr,
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.get_mr1 = mpc52xx_psc_get_mr1,
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};
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#endif /* CONFIG_MPC52xx */
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@ -585,8 +671,18 @@ static struct psc_ops mpc512x_psc_ops = {
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.fifoc_uninit = mpc512x_psc_fifoc_uninit,
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.get_irq = mpc512x_psc_get_irq,
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.handle_irq = mpc512x_psc_handle_irq,
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.get_status = mpc52xx_psc_get_status,
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.get_ipcr = mpc52xx_psc_get_ipcr,
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.command = mpc52xx_psc_command,
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.set_mode = mpc52xx_psc_set_mode,
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.set_rts = mpc52xx_psc_set_rts,
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.enable_ms = mpc52xx_psc_enable_ms,
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.set_sicr = mpc52xx_psc_set_sicr,
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.set_imr = mpc52xx_psc_set_imr,
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.get_mr1 = mpc52xx_psc_get_mr1,
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};
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#endif
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#endif /* CONFIG_PPC_MPC512x */
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static const struct psc_ops *psc_ops;
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@ -603,17 +699,14 @@ mpc52xx_uart_tx_empty(struct uart_port *port)
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static void
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mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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if (mctrl & TIOCM_RTS)
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out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
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else
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out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
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psc_ops->set_rts(port, mctrl & TIOCM_RTS);
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}
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static unsigned int
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mpc52xx_uart_get_mctrl(struct uart_port *port)
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{
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unsigned int ret = TIOCM_DSR;
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u8 status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
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u8 status = psc_ops->get_ipcr(port);
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if (!(status & MPC52xx_PSC_CTS))
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ret |= TIOCM_CTS;
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@ -663,15 +756,7 @@ mpc52xx_uart_stop_rx(struct uart_port *port)
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static void
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mpc52xx_uart_enable_ms(struct uart_port *port)
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{
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struct mpc52xx_psc __iomem *psc = PSC(port);
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/* clear D_*-bits by reading them */
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in_8(&psc->mpc52xx_psc_ipcr);
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/* enable CTS and DCD as IPC interrupts */
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out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
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port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
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out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
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psc_ops->enable_ms(port);
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}
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static void
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@ -681,9 +766,9 @@ mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
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spin_lock_irqsave(&port->lock, flags);
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if (ctl == -1)
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out_8(&PSC(port)->command, MPC52xx_PSC_START_BRK);
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psc_ops->command(port, MPC52xx_PSC_START_BRK);
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else
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out_8(&PSC(port)->command, MPC52xx_PSC_STOP_BRK);
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psc_ops->command(port, MPC52xx_PSC_STOP_BRK);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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@ -691,7 +776,6 @@ mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
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static int
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mpc52xx_uart_startup(struct uart_port *port)
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{
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struct mpc52xx_psc __iomem *psc = PSC(port);
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int ret;
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if (psc_ops->clock) {
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@ -707,15 +791,15 @@ mpc52xx_uart_startup(struct uart_port *port)
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return ret;
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/* Reset/activate the port, clear and enable interrupts */
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out_8(&psc->command, MPC52xx_PSC_RST_RX);
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out_8(&psc->command, MPC52xx_PSC_RST_TX);
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psc_ops->command(port, MPC52xx_PSC_RST_RX);
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psc_ops->command(port, MPC52xx_PSC_RST_TX);
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out_be32(&psc->sicr, 0); /* UART mode DCD ignored */
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psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */
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psc_ops->fifo_init(port);
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out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
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out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
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psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
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psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
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return 0;
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}
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@ -723,15 +807,13 @@ mpc52xx_uart_startup(struct uart_port *port)
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static void
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mpc52xx_uart_shutdown(struct uart_port *port)
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{
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struct mpc52xx_psc __iomem *psc = PSC(port);
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/* Shut down the port. Leave TX active if on a console port */
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out_8(&psc->command, MPC52xx_PSC_RST_RX);
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psc_ops->command(port, MPC52xx_PSC_RST_RX);
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if (!uart_console(port))
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out_8(&psc->command, MPC52xx_PSC_RST_TX);
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psc_ops->command(port, MPC52xx_PSC_RST_TX);
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port->read_status_mask = 0;
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out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
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psc_ops->set_imr(port, port->read_status_mask);
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if (psc_ops->clock)
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psc_ops->clock(port, 0);
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@ -744,7 +826,6 @@ static void
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mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
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struct ktermios *old)
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{
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struct mpc52xx_psc __iomem *psc = PSC(port);
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unsigned long flags;
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unsigned char mr1, mr2;
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unsigned int j;
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@ -808,13 +889,11 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
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"Some chars may have been lost.\n");
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/* Reset the TX & RX */
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out_8(&psc->command, MPC52xx_PSC_RST_RX);
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out_8(&psc->command, MPC52xx_PSC_RST_TX);
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psc_ops->command(port, MPC52xx_PSC_RST_RX);
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psc_ops->command(port, MPC52xx_PSC_RST_TX);
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/* Send new mode settings */
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out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
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out_8(&psc->mode, mr1);
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out_8(&psc->mode, mr2);
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psc_ops->set_mode(port, mr1, mr2);
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baud = psc_ops->set_baudrate(port, new, old);
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/* Update the per-port timeout */
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@ -824,8 +903,8 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
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mpc52xx_uart_enable_ms(port);
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/* Reenable TX & RX */
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out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
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out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
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psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
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psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
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/* We're all set, release the lock */
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spin_unlock_irqrestore(&port->lock, flags);
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@ -953,7 +1032,7 @@ mpc52xx_uart_int_rx_chars(struct uart_port *port)
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flag = TTY_NORMAL;
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port->icount.rx++;
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status = in_be16(&PSC(port)->mpc52xx_psc_status);
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status = psc_ops->get_status(port);
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if (status & (MPC52xx_PSC_SR_PE |
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MPC52xx_PSC_SR_FE |
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@ -973,7 +1052,7 @@ mpc52xx_uart_int_rx_chars(struct uart_port *port)
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}
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/* Clear error condition */
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out_8(&PSC(port)->command, MPC52xx_PSC_RST_ERR_STAT);
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psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT);
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}
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tty_insert_flip_char(tport, ch, flag);
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@ -1056,7 +1135,7 @@ mpc5xxx_uart_process_int(struct uart_port *port)
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if (psc_ops->tx_rdy(port))
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keepgoing |= mpc52xx_uart_int_tx_chars(port);
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status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
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status = psc_ops->get_ipcr(port);
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if (status & MPC52xx_PSC_D_DCD)
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uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
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@ -1097,14 +1176,12 @@ static void __init
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mpc52xx_console_get_options(struct uart_port *port,
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int *baud, int *parity, int *bits, int *flow)
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{
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struct mpc52xx_psc __iomem *psc = PSC(port);
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unsigned char mr1;
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pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
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/* Read the mode registers */
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out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
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mr1 = in_8(&psc->mode);
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mr1 = psc_ops->get_mr1(port);
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/* CT{U,L}R are write-only ! */
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*baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
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