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clk: tegra: Reimplement SOR clock on Tegra124

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In order to allow the display driver to deal uniformly with all SOR
generations, implement the SOR clocks in a way that is compatible with
Tegra186 and later.

Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding 2019-07-25 18:19:00 +02:00
parent da8d1a3555
commit 25175c806a
1 changed files with 13 additions and 9 deletions
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22
drivers/clk/tegra/clk-tegra124.c
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@ -1005,20 +1005,24 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI },
};
static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
"pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
"pll_d2_out0", "clk_m"
static const char * const sor0_parents[] = {
"pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0",
"pll_d2_out0", "clk_m",
};
#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
static const char *mux_clkm_plldp_sor0out[] = {
"clk_m", "pll_dp", "sor0_out",
static const char * const sor0_out_parents[] = {
"clk_m", "sor0_pad_clkout",
};
#define mux_clkm_plldp_sor0out_idx NULL
static struct tegra_periph_init_data tegra124_periph[] = {
MUX8_NOGATE_LOCK("sor0_out", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_out, &sor0_lock),
NODIV("sor0", mux_clkm_plldp_sor0out, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
TEGRA_INIT_DATA_TABLE("sor0", NULL, NULL, sor0_parents,
CLK_SOURCE_SOR0, 29, 0x7, 0, 0, 0, 0,
0, 182, 0, tegra_clk_sor0, NULL, 0,
&sor0_lock),
TEGRA_INIT_DATA_TABLE("sor0_out", NULL, NULL, sor0_out_parents,
CLK_SOURCE_SOR0, 14, 0x1, 0, 0, 0, 0,
0, 0, TEGRA_PERIPH_NO_GATE, tegra_clk_sor0_out,
NULL, 0, &sor0_lock),
};
static struct clk **clks;