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slc90e66: carry over fixes from piix driver
Synchronize with version 0.46 of the Intel PIIX/ICH driver: - carry over Alan's and my own fixes in the tuneproc() method and my cleanups both there and in the ratemask() method; - SLC90E66 only supports MW DMA modes 1/2 and SW DMA mode 2 (just like Intel chips), so don't claim support for other MW/SW DMA modes; - don't check dor non-NULL drive->id in the ide_dma_check() method -- this is assumed to be true in all other drivers; - do some coding/formatting cleanups while at it... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
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@ -1,5 +1,5 @@
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/*
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* linux/drivers/ide/pci/slc90e66.c Version 0.12 May 12, 2006
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* linux/drivers/ide/pci/slc90e66.c Version 0.13 December 30, 2006
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*
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* Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2006 MontaVista Software, Inc. <source@mvista.com>
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@ -26,7 +26,7 @@ static u8 slc90e66_ratemask (ide_drive_t *drive)
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u8 mode = 2;
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if (!eighty_ninty_three(drive))
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mode = min(mode, (u8)1);
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mode = min_t(u8, mode, 1);
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return mode;
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}
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@ -65,36 +65,47 @@ static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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int is_slave = (&hwif->drives[1] == drive);
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int is_slave = drive->dn & 1;
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int master_port = hwif->channel ? 0x42 : 0x40;
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int slave_port = 0x44;
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unsigned long flags;
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u16 master_data;
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u8 slave_data;
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/* ISP RTC */
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int control = 0;
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/* ISP RTC */
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static const u8 timings[][2]= {
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{ 0, 0 },
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{ 0, 0 },
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{ 1, 0 },
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{ 2, 1 },
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{ 2, 3 }, };
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{ 0, 0 },
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{ 0, 0 },
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{ 1, 0 },
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{ 2, 1 },
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{ 2, 3 }, };
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pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
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pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
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spin_lock_irqsave(&ide_lock, flags);
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pci_read_config_word(dev, master_port, &master_data);
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if (pio > 1)
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control |= 1; /* Programmable timing on */
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if (drive->media == ide_disk)
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control |= 4; /* Prefetch, post write */
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if (pio > 2)
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control |= 2; /* IORDY */
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if (is_slave) {
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master_data = master_data | 0x4000;
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if (pio > 1)
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master_data |= 0x4000;
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master_data &= ~0x0070;
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if (pio > 1) {
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/* enable PPE, IE and TIME */
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master_data = master_data | 0x0070;
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master_data = master_data | (control << 4);
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}
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pci_read_config_byte(dev, slave_port, &slave_data);
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slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
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slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
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} else {
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master_data = master_data & 0xccf8;
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if (pio > 1)
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master_data &= ~0x3307;
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if (pio > 1) {
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/* enable PPE, IE and TIME */
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master_data = master_data | 0x0007;
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master_data = master_data | control;
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}
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master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
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}
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pci_write_config_word(dev, master_port, master_data);
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@ -173,7 +184,7 @@ static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
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drive->init_speed = 0;
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if (id && (id->capability & 1) && drive->autodma) {
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if ((id->capability & 1) && drive->autodma) {
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if (ide_use_dma(drive) && slc90e66_config_drive_for_dma(drive))
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return hwif->ide_dma_on(drive);
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@ -201,7 +212,7 @@ static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
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hwif->irq = hwif->channel ? 15 : 14;
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hwif->speedproc = &slc90e66_tune_chipset;
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hwif->tuneproc = &slc90e66_tune_drive;
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hwif->tuneproc = &slc90e66_tune_drive;
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pci_read_config_byte(hwif->pci_dev, 0x47, ®47);
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@ -213,14 +224,16 @@ static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
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hwif->atapi_dma = 1;
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hwif->ultra_mask = 0x1f;
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hwif->mwdma_mask = 0x07;
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hwif->swdma_mask = 0x07;
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hwif->mwdma_mask = 0x06;
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hwif->swdma_mask = 0x04;
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if (!(hwif->udma_four))
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if (!hwif->udma_four) {
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/* bit[0(1)]: 0:80, 1:40 */
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hwif->udma_four = (reg47 & mask) ? 0 : 1;
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}
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hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;
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if (!noautodma)
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hwif->autodma = 1;
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hwif->drives[0].autodma = hwif->autodma;
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