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bpf, x32: remove ld_abs/ld_ind
Since LD_ABS/LD_IND instructions are now removed from the core and reimplemented through a combination of inlined BPF instructions and a slow-path helper, we can get rid of the complexity from x32 JIT. Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Acked-by: Alexei Starovoitov <ast@kernel.org> Signed-off-by: Alexei Starovoitov <ast@kernel.org>
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@ -175,19 +175,13 @@ static const u8 bpf2ia32[][2] = {
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#define SCRATCH_SIZE 96
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/* Total stack size used in JITed code */
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#define _STACK_SIZE \
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(stack_depth + \
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+ SCRATCH_SIZE + \
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+ 4 /* Extra space for skb_copy_bits buffer */)
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#define _STACK_SIZE (stack_depth + SCRATCH_SIZE)
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#define STACK_SIZE ALIGN(_STACK_SIZE, STACK_ALIGNMENT)
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/* Get the offset of eBPF REGISTERs stored on scratch space. */
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#define STACK_VAR(off) (off)
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/* Offset of skb_copy_bits buffer */
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#define SKB_BUFFER STACK_VAR(SCRATCH_SIZE)
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/* Encode 'dst_reg' register into IA32 opcode 'byte' */
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static u8 add_1reg(u8 byte, u32 dst_reg)
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{
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@ -2276,134 +2270,6 @@ emit_jmp:
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return -EFAULT;
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}
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break;
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case BPF_LD | BPF_ABS | BPF_W:
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case BPF_LD | BPF_ABS | BPF_H:
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case BPF_LD | BPF_ABS | BPF_B:
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case BPF_LD | BPF_IND | BPF_W:
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case BPF_LD | BPF_IND | BPF_H:
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case BPF_LD | BPF_IND | BPF_B:
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{
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int size;
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const u8 *r6 = bpf2ia32[BPF_REG_6];
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/* Setting up first argument */
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/* mov eax,dword ptr [ebp+off] */
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EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
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STACK_VAR(r6[0]));
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/* Setting up second argument */
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if (BPF_MODE(code) == BPF_ABS) {
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/* mov %edx, imm32 */
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EMIT1_off32(0xBA, imm32);
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} else {
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if (sstk)
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/* mov edx,dword ptr [ebp+off] */
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EMIT3(0x8B, add_2reg(0x40, IA32_EBP,
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IA32_EDX),
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STACK_VAR(src_lo));
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else
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/* mov edx,src_lo */
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EMIT2(0x8B, add_2reg(0xC0, src_lo,
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IA32_EDX));
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if (imm32) {
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if (is_imm8(imm32))
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/* add %edx,imm8 */
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EMIT3(0x83, 0xC2, imm32);
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else
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/* add %edx,imm32 */
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EMIT2_off32(0x81, 0xC2, imm32);
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}
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}
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/* Setting up third argument */
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switch (BPF_SIZE(code)) {
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case BPF_W:
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size = 4;
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break;
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case BPF_H:
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size = 2;
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break;
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case BPF_B:
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size = 1;
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break;
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default:
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return -EINVAL;
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}
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/* mov ecx,val */
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EMIT2(0xB1, size);
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/* movzx ecx,ecx */
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EMIT3(0x0F, 0xB6, add_2reg(0xC0, IA32_ECX, IA32_ECX));
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/* mov ebx,ebp */
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EMIT2(0x8B, add_2reg(0xC0, IA32_EBP, IA32_EBX));
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/* add %ebx,imm8 */
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EMIT3(0x83, add_1reg(0xC0, IA32_EBX), SKB_BUFFER);
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/* push ebx */
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EMIT1(0x53);
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/* Setting up function pointer to call */
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/* mov ebx,imm32*/
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EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EBX),
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(unsigned int)bpf_load_pointer);
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EMIT2(0xFF, add_1reg(0xD0, IA32_EBX));
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/* add %esp,4 */
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EMIT3(0x83, add_1reg(0xC0, IA32_ESP), 4);
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/* xor edx,edx */
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EMIT2(0x33, add_2reg(0xC0, IA32_EDX, IA32_EDX));
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/* mov dword ptr [ebp+off],eax */
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EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
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STACK_VAR(r0[0]));
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/* mov dword ptr [ebp+off],edx */
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EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
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STACK_VAR(r0[1]));
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/*
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* Check if return address is NULL or not.
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* If NULL then jump to epilogue else continue
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* to load the value from retn address
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*/
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EMIT3(0x83, add_1reg(0xF8, IA32_EAX), 0);
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jmp_offset = ctx->cleanup_addr - addrs[i];
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switch (BPF_SIZE(code)) {
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case BPF_W:
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jmp_offset += 7;
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break;
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case BPF_H:
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jmp_offset += 10;
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break;
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case BPF_B:
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jmp_offset += 6;
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break;
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}
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EMIT2_off32(0x0F, IA32_JE + 0x10, jmp_offset);
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/* Load value from the address */
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switch (BPF_SIZE(code)) {
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case BPF_W:
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/* mov eax,[eax] */
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EMIT2(0x8B, 0x0);
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/* Emit 'bswap eax' */
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EMIT2(0x0F, add_1reg(0xC8, IA32_EAX));
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break;
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case BPF_H:
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EMIT3(0x0F, 0xB7, 0x0);
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EMIT1(0x66);
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EMIT3(0xC1, add_1reg(0xC8, IA32_EAX), 8);
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break;
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case BPF_B:
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EMIT3(0x0F, 0xB6, 0x0);
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break;
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}
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/* mov dword ptr [ebp+off],eax */
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EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
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STACK_VAR(r0[0]));
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break;
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}
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/* STX XADD: lock *(u32 *)(dst + off) += src */
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case BPF_STX | BPF_XADD | BPF_W:
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/* STX XADD: lock *(u64 *)(dst + off) += src */
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