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perf/x86/intel/uncore: Add BW counters for GT, IA and IO breakdown
Linux only has support to read total DDR reads and writes. Here we add support to enable bandwidth breakdown-GT, IA and IO. Breakdown of BW is important to debug and optimize memory access. This can also be used for telemetry and improving the system software.The offsets for GT, IA and IO are added and these free running counters can be accessed via MMIO space. The BW breakdown can be measured using the following cmd: perf stat -e uncore_imc/gt_requests/,uncore_imc/ia_requests/,uncore_imc/io_requests/ 30.57 MiB uncore_imc/gt_requests/ 1346.13 MiB uncore_imc/ia_requests/ 190.97 MiB uncore_imc/io_requests/ 5.984572733 seconds time elapsed BW/s = <gt,ia,io>_requests/time elapsed Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20200814022234.23605-1-vaibhav.shankar@intel.com
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@ -390,6 +390,18 @@ static struct uncore_event_desc snb_uncore_imc_events[] = {
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INTEL_UNCORE_EVENT_DESC(data_writes.scale, "6.103515625e-5"),
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INTEL_UNCORE_EVENT_DESC(data_writes.unit, "MiB"),
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INTEL_UNCORE_EVENT_DESC(gt_requests, "event=0x03"),
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INTEL_UNCORE_EVENT_DESC(gt_requests.scale, "6.103515625e-5"),
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INTEL_UNCORE_EVENT_DESC(gt_requests.unit, "MiB"),
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INTEL_UNCORE_EVENT_DESC(ia_requests, "event=0x04"),
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INTEL_UNCORE_EVENT_DESC(ia_requests.scale, "6.103515625e-5"),
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INTEL_UNCORE_EVENT_DESC(ia_requests.unit, "MiB"),
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INTEL_UNCORE_EVENT_DESC(io_requests, "event=0x05"),
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INTEL_UNCORE_EVENT_DESC(io_requests.scale, "6.103515625e-5"),
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INTEL_UNCORE_EVENT_DESC(io_requests.unit, "MiB"),
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{ /* end: all zeroes */ },
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};
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@ -405,13 +417,35 @@ static struct uncore_event_desc snb_uncore_imc_events[] = {
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#define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE 0x5054
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#define SNB_UNCORE_PCI_IMC_CTR_BASE SNB_UNCORE_PCI_IMC_DATA_READS_BASE
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/* BW break down- legacy counters */
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#define SNB_UNCORE_PCI_IMC_GT_REQUESTS 0x3
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#define SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE 0x5040
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#define SNB_UNCORE_PCI_IMC_IA_REQUESTS 0x4
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#define SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE 0x5044
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#define SNB_UNCORE_PCI_IMC_IO_REQUESTS 0x5
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#define SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE 0x5048
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enum perf_snb_uncore_imc_freerunning_types {
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SNB_PCI_UNCORE_IMC_DATA = 0,
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SNB_PCI_UNCORE_IMC_DATA_READS = 0,
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SNB_PCI_UNCORE_IMC_DATA_WRITES,
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SNB_PCI_UNCORE_IMC_GT_REQUESTS,
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SNB_PCI_UNCORE_IMC_IA_REQUESTS,
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SNB_PCI_UNCORE_IMC_IO_REQUESTS,
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SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
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};
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static struct freerunning_counters snb_uncore_imc_freerunning[] = {
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[SNB_PCI_UNCORE_IMC_DATA] = { SNB_UNCORE_PCI_IMC_DATA_READS_BASE, 0x4, 0x0, 2, 32 },
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[SNB_PCI_UNCORE_IMC_DATA_READS] = { SNB_UNCORE_PCI_IMC_DATA_READS_BASE,
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0x0, 0x0, 1, 32 },
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[SNB_PCI_UNCORE_IMC_DATA_READS] = { SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE,
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0x0, 0x0, 1, 32 },
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[SNB_PCI_UNCORE_IMC_GT_REQUESTS] = { SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE,
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0x0, 0x0, 1, 32 },
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[SNB_PCI_UNCORE_IMC_IA_REQUESTS] = { SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE,
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0x0, 0x0, 1, 32 },
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[SNB_PCI_UNCORE_IMC_IO_REQUESTS] = { SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE,
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0x0, 0x0, 1, 32 },
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};
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static struct attribute *snb_uncore_imc_formats_attr[] = {
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@ -525,6 +559,18 @@ static int snb_uncore_imc_event_init(struct perf_event *event)
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base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE;
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idx = UNCORE_PMC_IDX_FREERUNNING;
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break;
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case SNB_UNCORE_PCI_IMC_GT_REQUESTS:
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base = SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE;
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idx = UNCORE_PMC_IDX_FREERUNNING;
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break;
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case SNB_UNCORE_PCI_IMC_IA_REQUESTS:
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base = SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE;
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idx = UNCORE_PMC_IDX_FREERUNNING;
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break;
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case SNB_UNCORE_PCI_IMC_IO_REQUESTS:
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base = SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE;
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idx = UNCORE_PMC_IDX_FREERUNNING;
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break;
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default:
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return -EINVAL;
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}
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@ -598,7 +644,7 @@ static struct intel_uncore_ops snb_uncore_imc_ops = {
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static struct intel_uncore_type snb_uncore_imc = {
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.name = "imc",
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.num_counters = 2,
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.num_counters = 5,
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.num_boxes = 1,
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.num_freerunning_types = SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
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.mmio_map_size = SNB_UNCORE_PCI_IMC_MAP_SIZE,
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