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arm64: dts: hisilicon: separate each group of data in the property "reg"

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Do not write the "reg" of multiple groups of data into a uint32 array,
use <> to separate them. Otherwise, the errors similar to the following
will be reported by reg.yaml.

soc: dsa@c7000000:reg:0: [0, 3305111552, 0, 8978432, 0, 3338665984, 0, \
6291456] is too long

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This commit is contained in:
Zhen Lei 2020-10-12 21:17:30 +08:00 committed by Wei Xu
parent c25b846425
commit 24402ce1e2
2 changed files with 76 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/hisilicon/hip06.dtsi
View File

@ -434,8 +434,8 @@
#size-cells = <0>;
compatible = "hisilicon,hns-dsaf-v2";
mode = "6port-16rss";
reg = <0x0 0xc5000000 0x0 0x890000
0x0 0xc7000000 0x0 0x600000>;
reg = <0x0 0xc5000000 0x0 0x890000>,
<0x0 0xc7000000 0x0 0x600000>;
reg-names = "ppe-base", "dsaf-base";
interrupt-parent = <&mbigen_dsaf0>;
subctrl-syscon = <&dsa_subctrl>;

148
arch/arm64/boot/dts/hisilicon/hip07.dtsi
View File

@ -1321,8 +1321,8 @@
#size-cells = <0>;
compatible = "hisilicon,hns-dsaf-v2";
mode = "6port-16rss";
reg = <0x0 0xc5000000 0x0 0x890000
0x0 0xc7000000 0x0 0x600000>;
reg = <0x0 0xc5000000 0x0 0x890000>,
<0x0 0xc7000000 0x0 0x600000>;
reg-names = "ppe-base", "dsaf-base";
interrupt-parent = <&mbigen_dsaf0>;
subctrl-syscon = <&dsa_subctrl>;
@ -1720,24 +1720,24 @@
};
p0_sec_a: crypto@d2000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x0 0xd0000000 0x0 0x10000
0x0 0xd2000000 0x0 0x10000
0x0 0xd2010000 0x0 0x10000
0x0 0xd2020000 0x0 0x10000
0x0 0xd2030000 0x0 0x10000
0x0 0xd2040000 0x0 0x10000
0x0 0xd2050000 0x0 0x10000
0x0 0xd2060000 0x0 0x10000
0x0 0xd2070000 0x0 0x10000
0x0 0xd2080000 0x0 0x10000
0x0 0xd2090000 0x0 0x10000
0x0 0xd20a0000 0x0 0x10000
0x0 0xd20b0000 0x0 0x10000
0x0 0xd20c0000 0x0 0x10000
0x0 0xd20d0000 0x0 0x10000
0x0 0xd20e0000 0x0 0x10000
0x0 0xd20f0000 0x0 0x10000
0x0 0xd2100000 0x0 0x10000>;
reg = <0x0 0xd0000000 0x0 0x10000>,
<0x0 0xd2000000 0x0 0x10000>,
<0x0 0xd2010000 0x0 0x10000>,
<0x0 0xd2020000 0x0 0x10000>,
<0x0 0xd2030000 0x0 0x10000>,
<0x0 0xd2040000 0x0 0x10000>,
<0x0 0xd2050000 0x0 0x10000>,
<0x0 0xd2060000 0x0 0x10000>,
<0x0 0xd2070000 0x0 0x10000>,
<0x0 0xd2080000 0x0 0x10000>,
<0x0 0xd2090000 0x0 0x10000>,
<0x0 0xd20a0000 0x0 0x10000>,
<0x0 0xd20b0000 0x0 0x10000>,
<0x0 0xd20c0000 0x0 0x10000>,
<0x0 0xd20d0000 0x0 0x10000>,
<0x0 0xd20e0000 0x0 0x10000>,
<0x0 0xd20f0000 0x0 0x10000>,
<0x0 0xd2100000 0x0 0x10000>;
interrupt-parent = <&p0_mbigen_sec_a>;
iommus = <&p0_smmu_alg_a 0x600>;
dma-coherent;
@ -1761,24 +1761,24 @@
};
p0_sec_b: crypto@8,d2000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x8 0xd0000000 0x0 0x10000
0x8 0xd2000000 0x0 0x10000
0x8 0xd2010000 0x0 0x10000
0x8 0xd2020000 0x0 0x10000
0x8 0xd2030000 0x0 0x10000
0x8 0xd2040000 0x0 0x10000
0x8 0xd2050000 0x0 0x10000
0x8 0xd2060000 0x0 0x10000
0x8 0xd2070000 0x0 0x10000
0x8 0xd2080000 0x0 0x10000
0x8 0xd2090000 0x0 0x10000
0x8 0xd20a0000 0x0 0x10000
0x8 0xd20b0000 0x0 0x10000
0x8 0xd20c0000 0x0 0x10000
0x8 0xd20d0000 0x0 0x10000
0x8 0xd20e0000 0x0 0x10000
0x8 0xd20f0000 0x0 0x10000
0x8 0xd2100000 0x0 0x10000>;
reg = <0x8 0xd0000000 0x0 0x10000>,
<0x8 0xd2000000 0x0 0x10000>,
<0x8 0xd2010000 0x0 0x10000>,
<0x8 0xd2020000 0x0 0x10000>,
<0x8 0xd2030000 0x0 0x10000>,
<0x8 0xd2040000 0x0 0x10000>,
<0x8 0xd2050000 0x0 0x10000>,
<0x8 0xd2060000 0x0 0x10000>,
<0x8 0xd2070000 0x0 0x10000>,
<0x8 0xd2080000 0x0 0x10000>,
<0x8 0xd2090000 0x0 0x10000>,
<0x8 0xd20a0000 0x0 0x10000>,
<0x8 0xd20b0000 0x0 0x10000>,
<0x8 0xd20c0000 0x0 0x10000>,
<0x8 0xd20d0000 0x0 0x10000>,
<0x8 0xd20e0000 0x0 0x10000>,
<0x8 0xd20f0000 0x0 0x10000>,
<0x8 0xd2100000 0x0 0x10000>;
interrupt-parent = <&p0_mbigen_sec_b>;
iommus = <&p0_smmu_alg_b 0x600>;
dma-coherent;
@ -1802,24 +1802,24 @@
};
p1_sec_a: crypto@400,d2000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x400 0xd0000000 0x0 0x10000
0x400 0xd2000000 0x0 0x10000
0x400 0xd2010000 0x0 0x10000
0x400 0xd2020000 0x0 0x10000
0x400 0xd2030000 0x0 0x10000
0x400 0xd2040000 0x0 0x10000
0x400 0xd2050000 0x0 0x10000
0x400 0xd2060000 0x0 0x10000
0x400 0xd2070000 0x0 0x10000
0x400 0xd2080000 0x0 0x10000
0x400 0xd2090000 0x0 0x10000
0x400 0xd20a0000 0x0 0x10000
0x400 0xd20b0000 0x0 0x10000
0x400 0xd20c0000 0x0 0x10000
0x400 0xd20d0000 0x0 0x10000
0x400 0xd20e0000 0x0 0x10000
0x400 0xd20f0000 0x0 0x10000
0x400 0xd2100000 0x0 0x10000>;
reg = <0x400 0xd0000000 0x0 0x10000>,
<0x400 0xd2000000 0x0 0x10000>,
<0x400 0xd2010000 0x0 0x10000>,
<0x400 0xd2020000 0x0 0x10000>,
<0x400 0xd2030000 0x0 0x10000>,
<0x400 0xd2040000 0x0 0x10000>,
<0x400 0xd2050000 0x0 0x10000>,
<0x400 0xd2060000 0x0 0x10000>,
<0x400 0xd2070000 0x0 0x10000>,
<0x400 0xd2080000 0x0 0x10000>,
<0x400 0xd2090000 0x0 0x10000>,
<0x400 0xd20a0000 0x0 0x10000>,
<0x400 0xd20b0000 0x0 0x10000>,
<0x400 0xd20c0000 0x0 0x10000>,
<0x400 0xd20d0000 0x0 0x10000>,
<0x400 0xd20e0000 0x0 0x10000>,
<0x400 0xd20f0000 0x0 0x10000>,
<0x400 0xd2100000 0x0 0x10000>;
interrupt-parent = <&p1_mbigen_sec_a>;
iommus = <&p1_smmu_alg_a 0x600>;
dma-coherent;
@ -1843,24 +1843,24 @@
};
p1_sec_b: crypto@408,d2000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x408 0xd0000000 0x0 0x10000
0x408 0xd2000000 0x0 0x10000
0x408 0xd2010000 0x0 0x10000
0x408 0xd2020000 0x0 0x10000
0x408 0xd2030000 0x0 0x10000
0x408 0xd2040000 0x0 0x10000
0x408 0xd2050000 0x0 0x10000
0x408 0xd2060000 0x0 0x10000
0x408 0xd2070000 0x0 0x10000
0x408 0xd2080000 0x0 0x10000
0x408 0xd2090000 0x0 0x10000
0x408 0xd20a0000 0x0 0x10000
0x408 0xd20b0000 0x0 0x10000
0x408 0xd20c0000 0x0 0x10000
0x408 0xd20d0000 0x0 0x10000
0x408 0xd20e0000 0x0 0x10000
0x408 0xd20f0000 0x0 0x10000
0x408 0xd2100000 0x0 0x10000>;
reg = <0x408 0xd0000000 0x0 0x10000>,
<0x408 0xd2000000 0x0 0x10000>,
<0x408 0xd2010000 0x0 0x10000>,
<0x408 0xd2020000 0x0 0x10000>,
<0x408 0xd2030000 0x0 0x10000>,
<0x408 0xd2040000 0x0 0x10000>,
<0x408 0xd2050000 0x0 0x10000>,
<0x408 0xd2060000 0x0 0x10000>,
<0x408 0xd2070000 0x0 0x10000>,
<0x408 0xd2080000 0x0 0x10000>,
<0x408 0xd2090000 0x0 0x10000>,
<0x408 0xd20a0000 0x0 0x10000>,
<0x408 0xd20b0000 0x0 0x10000>,
<0x408 0xd20c0000 0x0 0x10000>,
<0x408 0xd20d0000 0x0 0x10000>,
<0x408 0xd20e0000 0x0 0x10000>,
<0x408 0xd20f0000 0x0 0x10000>,
<0x408 0xd2100000 0x0 0x10000>;
interrupt-parent = <&p1_mbigen_sec_b>;
iommus = <&p1_smmu_alg_b 0x600>;
dma-coherent;