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scsi: hisi_sas: add phy_set_linkrate_v3_hw()
Add function to set linkrate for v3 hw. Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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@ -1680,6 +1680,44 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
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return 0;
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}
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static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
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struct sas_phy_linkrates *r)
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{
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u32 prog_phy_link_rate =
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hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
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struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
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struct asd_sas_phy *sas_phy = &phy->sas_phy;
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int i;
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enum sas_linkrate min, max;
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u32 rate_mask = 0;
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if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
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max = sas_phy->phy->maximum_linkrate;
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min = r->minimum_linkrate;
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} else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
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max = r->maximum_linkrate;
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min = sas_phy->phy->minimum_linkrate;
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} else
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return;
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sas_phy->phy->maximum_linkrate = max;
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sas_phy->phy->minimum_linkrate = min;
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min -= SAS_LINK_RATE_1_5_GBPS;
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max -= SAS_LINK_RATE_1_5_GBPS;
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for (i = 0; i <= max; i++)
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rate_mask |= 1 << (i * 2);
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prog_phy_link_rate &= ~0xff;
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prog_phy_link_rate |= rate_mask;
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hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
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prog_phy_link_rate);
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phy_hard_reset_v3_hw(hisi_hba, phy_no);
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}
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static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
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{
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struct pci_dev *pdev = hisi_hba->pci_dev;
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@ -1760,6 +1798,7 @@ static const struct hisi_sas_hw hisi_sas_v3_hw = {
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.phy_disable = disable_phy_v3_hw,
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.phy_hard_reset = phy_hard_reset_v3_hw,
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.phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
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.phy_set_linkrate = phy_set_linkrate_v3_hw,
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.dereg_device = dereg_device_v3_hw,
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.soft_reset = soft_reset_v3_hw,
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.get_phys_state = get_phys_state_v3_hw,
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