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ath9k: Clear TSF2 properly

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Chips in the AR9003 family have a second TSF, which
needs to be cleared when putting the card to
sleep.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
Sujith Manoharan 2015-02-02 18:21:12 +05:30 committed by Kalle Valo
parent b6f68b1ecb
commit 23ee7c33aa
2 changed files with 11 additions and 0 deletions
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9
drivers/net/wireless/ath/ath9k/ar9003_wow.c
View File

@ -35,6 +35,15 @@ static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
return; return;
} }
if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL))
REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE);
} else if (AR_SREV_9485(ah)){
if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) &
AR_GEN_TIMERS2_MODE_ENABLE_MASK))
REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE);
}
REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT); REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
} }

2
drivers/net/wireless/ath/ath9k/reg.h
View File

@ -1883,6 +1883,7 @@ enum {
#define AR_FIRST_NDP_TIMER 7 #define AR_FIRST_NDP_TIMER 7
#define AR_NDP2_PERIOD 0x81a0 #define AR_NDP2_PERIOD 0x81a0
#define AR_NDP2_TIMER_MODE 0x81c0 #define AR_NDP2_TIMER_MODE 0x81c0
#define AR_GEN_TIMERS2_MODE_ENABLE_MASK 0x000000FF
#define AR_GEN_TIMERS(_i) (0x8200 + ((_i) << 2)) #define AR_GEN_TIMERS(_i) (0x8200 + ((_i) << 2))
#define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0) #define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0)
@ -1978,6 +1979,7 @@ enum {
#define AR_DIRECT_CONNECT 0x83a0 #define AR_DIRECT_CONNECT 0x83a0
#define AR_DC_AP_STA_EN 0x00000001 #define AR_DC_AP_STA_EN 0x00000001
#define AR_DC_TSF2_ENABLE 0x00000001
#define AR_AES_MUTE_MASK0 0x805c #define AR_AES_MUTE_MASK0 0x805c
#define AR_AES_MUTE_MASK0_FC 0x0000FFFF #define AR_AES_MUTE_MASK0_FC 0x0000FFFF