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cpufreq: imx6q: switch to Use clk_bulk_get() to refine clk operations
Use clk_bulk_get() to simplify the driver's clocks handling. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Dong Aisheng
Rafael J. Wysocki
parent
3eff5f67a2
commit
2332bd0419
@ -25,15 +25,29 @@ static struct regulator *arm_reg;
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static struct regulator *pu_reg;
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static struct regulator *soc_reg;
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static struct clk *arm_clk;
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static struct clk *pll1_sys_clk;
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static struct clk *pll1_sw_clk;
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static struct clk *step_clk;
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static struct clk *pll2_pfd2_396m_clk;
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enum IMX6_CPUFREQ_CLKS {
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ARM,
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PLL1_SYS,
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STEP,
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PLL1_SW,
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PLL2_PFD2_396M,
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/* MX6UL requires two more clks */
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PLL2_BUS,
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SECONDARY_SEL,
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};
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#define IMX6Q_CPUFREQ_CLK_NUM 5
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#define IMX6UL_CPUFREQ_CLK_NUM 7
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/* clk used by i.MX6UL */
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static struct clk *pll2_bus_clk;
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static struct clk *secondary_sel_clk;
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static int num_clks;
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static struct clk_bulk_data clks[] = {
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{ .id = "arm" },
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{ .id = "pll1_sys" },
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{ .id = "step" },
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{ .id = "pll1_sw" },
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{ .id = "pll2_pfd2_396m" },
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{ .id = "pll2_bus" },
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{ .id = "secondary_sel" },
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};
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static struct device *cpu_dev;
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static bool free_opp;
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@ -53,7 +67,7 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
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new_freq = freq_table[index].frequency;
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freq_hz = new_freq * 1000;
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old_freq = clk_get_rate(arm_clk) / 1000;
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old_freq = clk_get_rate(clks[ARM].clk) / 1000;
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opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
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if (IS_ERR(opp)) {
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@ -112,29 +126,31 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
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* voltage of 528MHz, so lower the CPU frequency to one
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* half before changing CPU frequency.
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*/
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clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
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clk_set_parent(pll1_sw_clk, pll1_sys_clk);
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if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
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clk_set_parent(secondary_sel_clk, pll2_bus_clk);
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clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
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clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
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if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
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clk_set_parent(clks[SECONDARY_SEL].clk,
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clks[PLL2_BUS].clk);
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else
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clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
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clk_set_parent(step_clk, secondary_sel_clk);
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clk_set_parent(pll1_sw_clk, step_clk);
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clk_set_parent(clks[SECONDARY_SEL].clk,
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clks[PLL2_PFD2_396M].clk);
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clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
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clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
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} else {
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clk_set_parent(step_clk, pll2_pfd2_396m_clk);
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clk_set_parent(pll1_sw_clk, step_clk);
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if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
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clk_set_rate(pll1_sys_clk, new_freq * 1000);
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clk_set_parent(pll1_sw_clk, pll1_sys_clk);
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clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
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clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
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if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
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clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
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clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
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} else {
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/* pll1_sys needs to be enabled for divider rate change to work. */
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pll1_sys_temp_enabled = true;
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clk_prepare_enable(pll1_sys_clk);
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clk_prepare_enable(clks[PLL1_SYS].clk);
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}
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}
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/* Ensure the arm clock divider is what we expect */
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ret = clk_set_rate(arm_clk, new_freq * 1000);
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ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
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if (ret) {
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dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
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regulator_set_voltage_tol(arm_reg, volt_old, 0);
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@ -143,7 +159,7 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
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/* PLL1 is only needed until after ARM-PODF is set. */
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if (pll1_sys_temp_enabled)
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clk_disable_unprepare(pll1_sys_clk);
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clk_disable_unprepare(clks[PLL1_SYS].clk);
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/* scaling down? scale voltage after frequency */
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if (new_freq < old_freq) {
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@ -174,7 +190,7 @@ static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
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{
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int ret;
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policy->clk = arm_clk;
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policy->clk = clks[ARM].clk;
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ret = cpufreq_generic_init(policy, freq_table, transition_latency);
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policy->suspend_freq = policy->max;
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@ -266,28 +282,15 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
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return -ENOENT;
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}
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arm_clk = clk_get(cpu_dev, "arm");
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pll1_sys_clk = clk_get(cpu_dev, "pll1_sys");
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pll1_sw_clk = clk_get(cpu_dev, "pll1_sw");
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step_clk = clk_get(cpu_dev, "step");
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pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m");
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if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
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IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
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dev_err(cpu_dev, "failed to get clocks\n");
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ret = -ENOENT;
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goto put_clk;
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}
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if (of_machine_is_compatible("fsl,imx6ul") ||
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of_machine_is_compatible("fsl,imx6ull")) {
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pll2_bus_clk = clk_get(cpu_dev, "pll2_bus");
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secondary_sel_clk = clk_get(cpu_dev, "secondary_sel");
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if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) {
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dev_err(cpu_dev, "failed to get clocks specific to imx6ul\n");
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ret = -ENOENT;
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goto put_clk;
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}
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}
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of_machine_is_compatible("fsl,imx6ull"))
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num_clks = IMX6UL_CPUFREQ_CLK_NUM;
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else
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num_clks = IMX6Q_CPUFREQ_CLK_NUM;
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ret = clk_bulk_get(cpu_dev, num_clks, clks);
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if (ret)
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goto put_node;
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arm_reg = regulator_get(cpu_dev, "arm");
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pu_reg = regulator_get_optional(cpu_dev, "pu");
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@ -424,22 +427,11 @@ put_reg:
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regulator_put(pu_reg);
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if (!IS_ERR(soc_reg))
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regulator_put(soc_reg);
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put_clk:
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if (!IS_ERR(arm_clk))
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clk_put(arm_clk);
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if (!IS_ERR(pll1_sys_clk))
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clk_put(pll1_sys_clk);
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if (!IS_ERR(pll1_sw_clk))
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clk_put(pll1_sw_clk);
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if (!IS_ERR(step_clk))
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clk_put(step_clk);
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if (!IS_ERR(pll2_pfd2_396m_clk))
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clk_put(pll2_pfd2_396m_clk);
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if (!IS_ERR(pll2_bus_clk))
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clk_put(pll2_bus_clk);
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if (!IS_ERR(secondary_sel_clk))
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clk_put(secondary_sel_clk);
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clk_bulk_put(num_clks, clks);
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put_node:
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of_node_put(np);
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return ret;
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}
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@ -453,13 +445,8 @@ static int imx6q_cpufreq_remove(struct platform_device *pdev)
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if (!IS_ERR(pu_reg))
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regulator_put(pu_reg);
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regulator_put(soc_reg);
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clk_put(arm_clk);
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clk_put(pll1_sys_clk);
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clk_put(pll1_sw_clk);
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clk_put(step_clk);
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clk_put(pll2_pfd2_396m_clk);
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clk_put(pll2_bus_clk);
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clk_put(secondary_sel_clk);
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clk_bulk_put(num_clks, clks);
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return 0;
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}
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