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PCI: keystone: Add support for PCIe EP in AM654x Platforms
Add PCIe EP support for AM654x Platforms in pci-keystone.c Link: https://lore.kernel.org/linux-pci/20190325093947.32633-15-kishon@ti.com/ Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [lorenzo.pieralisi@arm.com: made dev_vdbg() call a comment] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
This commit is contained in:
Kishon Vijay Abraham I
Lorenzo Pieralisi
parent
9bc755d2cf
commit
23284ad677
@ -103,15 +103,32 @@ config PCIE_SPEAR13XX
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Say Y here if you want PCIe support on SPEAr13XX SoCs.
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config PCI_KEYSTONE
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bool "TI Keystone PCIe controller"
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bool
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config PCI_KEYSTONE_HOST
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bool "PCI Keystone Host Mode"
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depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST)
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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select PCI_KEYSTONE
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default y
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help
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Say Y here if you want to enable PCI controller support on Keystone
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SoCs. The PCI controller on Keystone is based on DesignWare hardware
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and therefore the driver re-uses the DesignWare core functions to
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implement the driver.
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Enables support for the PCIe controller in the Keystone SoC to
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work in host mode. The PCI controller on Keystone is based on
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DesignWare hardware and therefore the driver re-uses the
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DesignWare core functions to implement the driver.
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config PCI_KEYSTONE_EP
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bool "PCI Keystone Endpoint Mode"
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depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST)
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PCI_KEYSTONE
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help
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Enables support for the PCIe controller in the Keystone SoC to
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work in endpoint mode. The PCI controller on Keystone is based
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on DesignWare hardware and therefore the driver re-uses the
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DesignWare core functions to implement the driver.
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config PCI_LAYERSCAPE
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bool "Freescale Layerscape PCIe controller"
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@ -52,6 +52,12 @@
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#define OB_ENABLEN BIT(0)
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#define OB_WIN_SIZE 8 /* 8MB */
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#define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1)))
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#define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1)))
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#define PCIE_EP_IRQ_SET 0x64
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#define PCIE_EP_IRQ_CLR 0x68
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#define INT_ENABLE BIT(0)
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/* IRQ register defines */
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#define IRQ_EOI 0x050
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@ -95,11 +101,16 @@
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#define KS_PCIE_SYSCLOCKOUTEN BIT(0)
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#define AM654_PCIE_DEV_TYPE_MASK 0x3
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#define AM654_WIN_SIZE SZ_64K
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#define APP_ADDR_SPACE_0 (16 * SZ_1K)
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#define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
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struct ks_pcie_of_data {
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enum dw_pcie_device_mode mode;
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const struct dw_pcie_host_ops *host_ops;
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const struct dw_pcie_ep_ops *ep_ops;
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unsigned int version;
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};
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@ -264,13 +275,11 @@ static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie,
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ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset);
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}
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/*
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* Dummy function so that DW core doesn't configure MSI
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*/
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static int ks_pcie_am654_msi_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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dev_vdbg(dev, "dummy function so that DW core doesn't configure MSI\n");
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return 0;
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}
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@ -877,12 +886,139 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie,
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return 0;
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}
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static u32 ks_pcie_am654_read_dbi2(struct dw_pcie *pci, void __iomem *base,
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u32 reg, size_t size)
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{
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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u32 val;
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ks_pcie_set_dbi_mode(ks_pcie);
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dw_pcie_read(base + reg, size, &val);
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ks_pcie_clear_dbi_mode(ks_pcie);
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return val;
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}
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static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base,
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u32 reg, size_t size, u32 val)
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{
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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ks_pcie_set_dbi_mode(ks_pcie);
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dw_pcie_write(base + reg, size, val);
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ks_pcie_clear_dbi_mode(ks_pcie);
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}
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static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = {
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.start_link = ks_pcie_start_link,
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.stop_link = ks_pcie_stop_link,
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.link_up = ks_pcie_link_up,
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.read_dbi2 = ks_pcie_am654_read_dbi2,
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.write_dbi2 = ks_pcie_am654_write_dbi2,
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};
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static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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int flags;
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ep->page_size = AM654_WIN_SIZE;
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flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32;
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dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1);
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags);
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}
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static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie)
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{
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struct dw_pcie *pci = ks_pcie->pci;
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u8 int_pin;
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int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN);
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if (int_pin == 0 || int_pin > 4)
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return;
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ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin),
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INT_ENABLE);
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ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE);
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mdelay(1);
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ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE);
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ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin),
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INT_ENABLE);
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}
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static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
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enum pci_epc_irq_type type,
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u16 interrupt_num)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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switch (type) {
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case PCI_EPC_IRQ_LEGACY:
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ks_pcie_am654_raise_legacy_irq(ks_pcie);
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break;
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case PCI_EPC_IRQ_MSI:
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dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
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break;
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default:
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dev_err(pci->dev, "UNKNOWN IRQ type\n");
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return -EINVAL;
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}
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return 0;
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}
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static const struct pci_epc_features ks_pcie_am654_epc_features = {
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.linkup_notifier = false,
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.msi_capable = true,
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.msix_capable = false,
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.reserved_bar = 1 << BAR_0 | 1 << BAR_1,
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.bar_fixed_64bit = 1 << BAR_0,
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.bar_fixed_size[2] = SZ_1M,
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.bar_fixed_size[3] = SZ_64K,
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.bar_fixed_size[4] = 256,
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.bar_fixed_size[5] = SZ_1M,
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.align = SZ_1M,
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};
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static const struct pci_epc_features*
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ks_pcie_am654_get_features(struct dw_pcie_ep *ep)
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{
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return &ks_pcie_am654_epc_features;
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}
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static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = {
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.ep_init = ks_pcie_am654_ep_init,
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.raise_irq = ks_pcie_am654_raise_irq,
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.get_features = &ks_pcie_am654_get_features,
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};
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static int __init ks_pcie_add_pcie_ep(struct keystone_pcie *ks_pcie,
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struct platform_device *pdev)
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{
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int ret;
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struct dw_pcie_ep *ep;
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struct resource *res;
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci = ks_pcie->pci;
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ep = &pci->ep;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
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if (!res)
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return -EINVAL;
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ep->phys_base = res->start;
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ep->addr_size = resource_size(res);
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ret = dw_pcie_ep_init(ep);
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if (ret) {
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dev_err(dev, "failed to initialize endpoint\n");
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return ret;
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}
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return 0;
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}
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static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie)
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{
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int num_lanes = ks_pcie->num_lanes;
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@ -950,7 +1086,8 @@ static int ks_pcie_set_mode(struct device *dev)
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return 0;
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}
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static int ks_pcie_am654_set_mode(struct device *dev)
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static int ks_pcie_am654_set_mode(struct device *dev,
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enum dw_pcie_device_mode mode)
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{
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struct device_node *np = dev->of_node;
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struct regmap *syscon;
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@ -963,7 +1100,18 @@ static int ks_pcie_am654_set_mode(struct device *dev)
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return 0;
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mask = AM654_PCIE_DEV_TYPE_MASK;
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val = RC;
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switch (mode) {
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case DW_PCIE_RC_TYPE:
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val = RC;
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break;
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case DW_PCIE_EP_TYPE:
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val = EP;
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break;
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default:
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dev_err(dev, "INVALID device type %d\n", mode);
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return -EINVAL;
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}
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ret = regmap_update_bits(syscon, 0, mask, val);
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if (ret) {
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@ -1006,6 +1154,13 @@ static const struct ks_pcie_of_data ks_pcie_rc_of_data = {
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static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = {
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.host_ops = &ks_pcie_am654_host_ops,
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.mode = DW_PCIE_RC_TYPE,
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.version = 0x490A,
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};
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static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = {
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.ep_ops = &ks_pcie_am654_ep_ops,
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.mode = DW_PCIE_EP_TYPE,
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.version = 0x490A,
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};
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@ -1019,16 +1174,22 @@ static const struct of_device_id ks_pcie_of_match[] = {
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.data = &ks_pcie_am654_rc_of_data,
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.compatible = "ti,am654-pcie-rc",
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},
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{
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.data = &ks_pcie_am654_ep_of_data,
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.compatible = "ti,am654-pcie-ep",
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},
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{ },
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};
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static int __init ks_pcie_probe(struct platform_device *pdev)
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{
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const struct dw_pcie_host_ops *host_ops;
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const struct dw_pcie_ep_ops *ep_ops;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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const struct ks_pcie_of_data *data;
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const struct of_device_id *match;
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enum dw_pcie_device_mode mode;
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struct dw_pcie *pci;
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struct keystone_pcie *ks_pcie;
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struct device_link **link;
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@ -1053,6 +1214,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
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version = data->version;
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host_ops = data->host_ops;
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ep_ops = data->ep_ops;
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mode = data->mode;
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ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL);
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if (!ks_pcie)
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@ -1078,16 +1241,11 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
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ks_pcie->is_am6 = true;
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pci->dbi_base = base;
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pci->dbi_base2 = base;
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pci->dev = dev;
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pci->ops = &ks_pcie_dw_pcie_ops;
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pci->version = version;
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ret = of_property_read_u32(np, "num-viewport", &num_viewport);
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if (ret < 0) {
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dev_err(dev, "unable to read *num-viewport* property\n");
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return ret;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(dev, "missing IRQ resource: %d\n", irq);
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@ -1136,7 +1294,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
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ks_pcie->pci = pci;
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ks_pcie->link = link;
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ks_pcie->num_lanes = num_lanes;
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ks_pcie->num_viewport = num_viewport;
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ks_pcie->phy = phy;
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gpiod = devm_gpiod_get_optional(dev, "reset",
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@ -1172,7 +1329,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
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pci->atu_base = atu_base;
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ret = ks_pcie_am654_set_mode(dev);
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ret = ks_pcie_am654_set_mode(dev, mode);
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if (ret < 0)
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goto err_get_sync;
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} else {
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@ -1181,29 +1338,58 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
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goto err_get_sync;
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}
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/*
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* "Power Sequencing and Reset Signal Timings" table in
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* PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0
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* indicates PERST# should be deasserted after minimum of 100us
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* once REFCLK is stable. The REFCLK to the connector in RC
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* mode is selected while enabling the PHY. So deassert PERST#
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* after 100 us.
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*/
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if (gpiod) {
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usleep_range(100, 200);
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gpiod_set_value_cansleep(gpiod, 1);
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}
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link_speed = of_pci_get_max_link_speed(np);
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if (link_speed < 0)
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link_speed = 2;
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ks_pcie_set_link_speed(pci, link_speed);
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pci->pp.ops = host_ops;
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ret = ks_pcie_add_pcie_port(ks_pcie, pdev);
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if (ret < 0)
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goto err_get_sync;
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switch (mode) {
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case DW_PCIE_RC_TYPE:
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if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) {
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ret = -ENODEV;
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goto err_get_sync;
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}
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ret = of_property_read_u32(np, "num-viewport", &num_viewport);
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if (ret < 0) {
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dev_err(dev, "unable to read *num-viewport* property\n");
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return ret;
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}
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/*
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* "Power Sequencing and Reset Signal Timings" table in
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* PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0
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* indicates PERST# should be deasserted after minimum of 100us
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* once REFCLK is stable. The REFCLK to the connector in RC
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* mode is selected while enabling the PHY. So deassert PERST#
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* after 100 us.
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*/
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if (gpiod) {
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usleep_range(100, 200);
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gpiod_set_value_cansleep(gpiod, 1);
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}
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ks_pcie->num_viewport = num_viewport;
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pci->pp.ops = host_ops;
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ret = ks_pcie_add_pcie_port(ks_pcie, pdev);
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if (ret < 0)
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goto err_get_sync;
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break;
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case DW_PCIE_EP_TYPE:
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if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) {
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ret = -ENODEV;
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goto err_get_sync;
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}
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pci->ep.ops = ep_ops;
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ret = ks_pcie_add_pcie_ep(ks_pcie, pdev);
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if (ret < 0)
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goto err_get_sync;
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break;
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default:
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dev_err(dev, "INVALID device type %d\n", mode);
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}
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ks_pcie_enable_error_irq(ks_pcie);
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