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mlxbf_gige: add MDIO support for BlueField-3
This patch adds initial MDIO support for the BlueField-3 SoC. Separate header files for the BlueField-2 and the BlueField-3 SoCs have been created. These header files hold the SoC-specific MDIO macros since the register offsets and bit fields have changed. Also, in BlueField-3 there is a separate register for writing and reading the MDIO data. Finally, instead of having "if" statements everywhere to differentiate between SoC-specific logic, a mlxbf_gige_mdio_gw_t struct was created for this purpose. Signed-off-by: David Thompson <davthompson@nvidia.com> Signed-off-by: Asmaa Mnebhi <asmaa@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
David Thompson
Jakub Kicinski
parent
e2a9575025
commit
2321d69f92
@ -67,6 +67,23 @@ struct mlxbf_gige_stats {
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u64 rx_filter_discard_pkts;
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};
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struct mlxbf_gige_reg_param {
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u32 mask;
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u32 shift;
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};
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struct mlxbf_gige_mdio_gw {
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u32 gw_address;
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u32 read_data_address;
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struct mlxbf_gige_reg_param busy;
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struct mlxbf_gige_reg_param write_data;
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struct mlxbf_gige_reg_param read_data;
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struct mlxbf_gige_reg_param devad;
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struct mlxbf_gige_reg_param partad;
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struct mlxbf_gige_reg_param opcode;
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struct mlxbf_gige_reg_param st1;
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};
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struct mlxbf_gige {
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void __iomem *base;
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void __iomem *llu_base;
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@ -102,6 +119,8 @@ struct mlxbf_gige {
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u8 valid_polarity;
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struct napi_struct napi;
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struct mlxbf_gige_stats stats;
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u8 hw_version;
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struct mlxbf_gige_mdio_gw *mdio_gw;
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};
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/* Rx Work Queue Element definitions */
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@ -315,6 +315,8 @@ static int mlxbf_gige_probe(struct platform_device *pdev)
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spin_lock_init(&priv->lock);
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priv->hw_version = readq(base + MLXBF_GIGE_VERSION);
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/* Attach MDIO device */
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err = mlxbf_gige_mdio_probe(pdev, priv);
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if (err)
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@ -23,9 +23,75 @@
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#include "mlxbf_gige.h"
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#include "mlxbf_gige_regs.h"
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#include "mlxbf_gige_mdio_bf2.h"
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#include "mlxbf_gige_mdio_bf3.h"
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#define MLXBF_GIGE_MDIO_GW_OFFSET 0x0
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#define MLXBF_GIGE_MDIO_CFG_OFFSET 0x4
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static struct mlxbf_gige_mdio_gw mlxbf_gige_mdio_gw_t[] = {
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[MLXBF_GIGE_VERSION_BF2] = {
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.gw_address = MLXBF2_GIGE_MDIO_GW_OFFSET,
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.read_data_address = MLXBF2_GIGE_MDIO_GW_OFFSET,
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.busy = {
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.mask = MLXBF2_GIGE_MDIO_GW_BUSY_MASK,
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.shift = MLXBF2_GIGE_MDIO_GW_BUSY_SHIFT,
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},
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.read_data = {
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.mask = MLXBF2_GIGE_MDIO_GW_AD_MASK,
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.shift = MLXBF2_GIGE_MDIO_GW_AD_SHIFT,
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},
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.write_data = {
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.mask = MLXBF2_GIGE_MDIO_GW_AD_MASK,
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.shift = MLXBF2_GIGE_MDIO_GW_AD_SHIFT,
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},
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.devad = {
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.mask = MLXBF2_GIGE_MDIO_GW_DEVAD_MASK,
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.shift = MLXBF2_GIGE_MDIO_GW_DEVAD_SHIFT,
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},
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.partad = {
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.mask = MLXBF2_GIGE_MDIO_GW_PARTAD_MASK,
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.shift = MLXBF2_GIGE_MDIO_GW_PARTAD_SHIFT,
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},
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.opcode = {
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.mask = MLXBF2_GIGE_MDIO_GW_OPCODE_MASK,
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.shift = MLXBF2_GIGE_MDIO_GW_OPCODE_SHIFT,
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},
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.st1 = {
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.mask = MLXBF2_GIGE_MDIO_GW_ST1_MASK,
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.shift = MLXBF2_GIGE_MDIO_GW_ST1_SHIFT,
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},
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},
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[MLXBF_GIGE_VERSION_BF3] = {
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.gw_address = MLXBF3_GIGE_MDIO_GW_OFFSET,
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.read_data_address = MLXBF3_GIGE_MDIO_DATA_READ,
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.busy = {
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.mask = MLXBF3_GIGE_MDIO_GW_BUSY_MASK,
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.shift = MLXBF3_GIGE_MDIO_GW_BUSY_SHIFT,
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},
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.read_data = {
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.mask = MLXBF3_GIGE_MDIO_GW_DATA_READ_MASK,
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.shift = MLXBF3_GIGE_MDIO_GW_DATA_READ_SHIFT,
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},
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.write_data = {
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.mask = MLXBF3_GIGE_MDIO_GW_DATA_MASK,
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.shift = MLXBF3_GIGE_MDIO_GW_DATA_SHIFT,
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},
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.devad = {
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.mask = MLXBF3_GIGE_MDIO_GW_DEVAD_MASK,
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.shift = MLXBF3_GIGE_MDIO_GW_DEVAD_SHIFT,
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},
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.partad = {
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.mask = MLXBF3_GIGE_MDIO_GW_PARTAD_MASK,
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.shift = MLXBF3_GIGE_MDIO_GW_PARTAD_SHIFT,
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},
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.opcode = {
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.mask = MLXBF3_GIGE_MDIO_GW_OPCODE_MASK,
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.shift = MLXBF3_GIGE_MDIO_GW_OPCODE_SHIFT,
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},
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.st1 = {
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.mask = MLXBF3_GIGE_MDIO_GW_ST1_MASK,
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.shift = MLXBF3_GIGE_MDIO_GW_ST1_SHIFT,
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},
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},
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};
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#define MLXBF_GIGE_MDIO_FREQ_REFERENCE 156250000ULL
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#define MLXBF_GIGE_MDIO_COREPLL_CONST 16384ULL
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@ -47,30 +113,10 @@
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/* Busy bit is set by software and cleared by hardware */
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#define MLXBF_GIGE_MDIO_SET_BUSY 0x1
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/* MDIO GW register bits */
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#define MLXBF_GIGE_MDIO_GW_AD_MASK GENMASK(15, 0)
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#define MLXBF_GIGE_MDIO_GW_DEVAD_MASK GENMASK(20, 16)
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#define MLXBF_GIGE_MDIO_GW_PARTAD_MASK GENMASK(25, 21)
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#define MLXBF_GIGE_MDIO_GW_OPCODE_MASK GENMASK(27, 26)
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#define MLXBF_GIGE_MDIO_GW_ST1_MASK GENMASK(28, 28)
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#define MLXBF_GIGE_MDIO_GW_BUSY_MASK GENMASK(30, 30)
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/* MDIO config register bits */
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#define MLXBF_GIGE_MDIO_CFG_MDIO_MODE_MASK GENMASK(1, 0)
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#define MLXBF_GIGE_MDIO_CFG_MDIO3_3_MASK GENMASK(2, 2)
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#define MLXBF_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK GENMASK(4, 4)
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#define MLXBF_GIGE_MDIO_CFG_MDC_PERIOD_MASK GENMASK(15, 8)
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#define MLXBF_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK GENMASK(23, 16)
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#define MLXBF_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK GENMASK(31, 24)
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#define MLXBF_GIGE_MDIO_CFG_VAL (FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_MODE_MASK, 1) | \
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FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO3_3_MASK, 1) | \
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FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK, 1) | \
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FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, 6) | \
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FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, 13))
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#define MLXBF_GIGE_BF2_COREPLL_ADDR 0x02800c30
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#define MLXBF_GIGE_BF2_COREPLL_SIZE 0x0000000c
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#define MLXBF_GIGE_BF3_COREPLL_ADDR 0x13409824
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#define MLXBF_GIGE_BF3_COREPLL_SIZE 0x00000010
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static struct resource corepll_params[] = {
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[MLXBF_GIGE_VERSION_BF2] = {
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@ -78,6 +124,11 @@ static struct resource corepll_params[] = {
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.end = MLXBF_GIGE_BF2_COREPLL_ADDR + MLXBF_GIGE_BF2_COREPLL_SIZE - 1,
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.name = "COREPLL_RES"
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},
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[MLXBF_GIGE_VERSION_BF3] = {
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.start = MLXBF_GIGE_BF3_COREPLL_ADDR,
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.end = MLXBF_GIGE_BF3_COREPLL_ADDR + MLXBF_GIGE_BF3_COREPLL_SIZE - 1,
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.name = "COREPLL_RES"
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}
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};
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/* Returns core clock i1clk in Hz */
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@ -134,19 +185,23 @@ static u8 mdio_period_map(struct mlxbf_gige *priv)
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return mdio_period;
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}
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static u32 mlxbf_gige_mdio_create_cmd(u16 data, int phy_add,
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static u32 mlxbf_gige_mdio_create_cmd(struct mlxbf_gige_mdio_gw *mdio_gw, u16 data, int phy_add,
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int phy_reg, u32 opcode)
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{
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u32 gw_reg = 0;
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gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_AD_MASK, data);
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gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_DEVAD_MASK, phy_reg);
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gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_PARTAD_MASK, phy_add);
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gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_OPCODE_MASK, opcode);
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gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_ST1_MASK,
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MLXBF_GIGE_MDIO_CL22_ST1);
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gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_BUSY_MASK,
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MLXBF_GIGE_MDIO_SET_BUSY);
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gw_reg |= ((data << mdio_gw->write_data.shift) &
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mdio_gw->write_data.mask);
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gw_reg |= ((phy_reg << mdio_gw->devad.shift) &
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mdio_gw->devad.mask);
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gw_reg |= ((phy_add << mdio_gw->partad.shift) &
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mdio_gw->partad.mask);
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gw_reg |= ((opcode << mdio_gw->opcode.shift) &
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mdio_gw->opcode.mask);
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gw_reg |= ((MLXBF_GIGE_MDIO_CL22_ST1 << mdio_gw->st1.shift) &
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mdio_gw->st1.mask);
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gw_reg |= ((MLXBF_GIGE_MDIO_SET_BUSY << mdio_gw->busy.shift) &
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mdio_gw->busy.mask);
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return gw_reg;
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}
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@ -162,25 +217,26 @@ static int mlxbf_gige_mdio_read(struct mii_bus *bus, int phy_add, int phy_reg)
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return -EOPNOTSUPP;
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/* Send mdio read request */
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cmd = mlxbf_gige_mdio_create_cmd(0, phy_add, phy_reg, MLXBF_GIGE_MDIO_CL22_READ);
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cmd = mlxbf_gige_mdio_create_cmd(priv->mdio_gw, 0, phy_add, phy_reg,
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MLXBF_GIGE_MDIO_CL22_READ);
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writel(cmd, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
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writel(cmd, priv->mdio_io + priv->mdio_gw->gw_address);
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ret = readl_poll_timeout_atomic(priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET,
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val, !(val & MLXBF_GIGE_MDIO_GW_BUSY_MASK),
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ret = readl_poll_timeout_atomic(priv->mdio_io + priv->mdio_gw->gw_address,
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val, !(val & priv->mdio_gw->busy.mask),
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5, 1000000);
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if (ret) {
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writel(0, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
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writel(0, priv->mdio_io + priv->mdio_gw->gw_address);
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return ret;
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}
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ret = readl(priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
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ret = readl(priv->mdio_io + priv->mdio_gw->read_data_address);
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/* Only return ad bits of the gw register */
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ret &= MLXBF_GIGE_MDIO_GW_AD_MASK;
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ret &= priv->mdio_gw->read_data.mask;
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/* The MDIO lock is set on read. To release it, clear gw register */
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writel(0, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
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writel(0, priv->mdio_io + priv->mdio_gw->gw_address);
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return ret;
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}
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@ -197,17 +253,17 @@ static int mlxbf_gige_mdio_write(struct mii_bus *bus, int phy_add,
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return -EOPNOTSUPP;
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/* Send mdio write request */
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cmd = mlxbf_gige_mdio_create_cmd(val, phy_add, phy_reg,
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cmd = mlxbf_gige_mdio_create_cmd(priv->mdio_gw, val, phy_add, phy_reg,
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MLXBF_GIGE_MDIO_CL22_WRITE);
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writel(cmd, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
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writel(cmd, priv->mdio_io + priv->mdio_gw->gw_address);
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/* If the poll timed out, drop the request */
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ret = readl_poll_timeout_atomic(priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET,
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temp, !(temp & MLXBF_GIGE_MDIO_GW_BUSY_MASK),
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ret = readl_poll_timeout_atomic(priv->mdio_io + priv->mdio_gw->gw_address,
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temp, !(temp & priv->mdio_gw->busy.mask),
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5, 1000000);
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/* The MDIO lock is set on read. To release it, clear gw register */
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writel(0, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
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writel(0, priv->mdio_io + priv->mdio_gw->gw_address);
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return ret;
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}
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@ -219,9 +275,20 @@ static void mlxbf_gige_mdio_cfg(struct mlxbf_gige *priv)
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mdio_period = mdio_period_map(priv);
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val = MLXBF_GIGE_MDIO_CFG_VAL;
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val |= FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDC_PERIOD_MASK, mdio_period);
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writel(val, priv->mdio_io + MLXBF_GIGE_MDIO_CFG_OFFSET);
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if (priv->hw_version == MLXBF_GIGE_VERSION_BF2) {
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val = MLXBF2_GIGE_MDIO_CFG_VAL;
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val |= FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDC_PERIOD_MASK, mdio_period);
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writel(val, priv->mdio_io + MLXBF2_GIGE_MDIO_CFG_OFFSET);
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} else {
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val = FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_MODE_MASK, 1) |
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FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK, 1);
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writel(val, priv->mdio_io + MLXBF3_GIGE_MDIO_CFG_REG0);
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val = FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDC_PERIOD_MASK, mdio_period);
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writel(val, priv->mdio_io + MLXBF3_GIGE_MDIO_CFG_REG1);
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val = FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, 6) |
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FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, 13);
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writel(val, priv->mdio_io + MLXBF3_GIGE_MDIO_CFG_REG2);
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}
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}
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int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv)
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@ -230,6 +297,9 @@ int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv)
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struct resource *res;
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int ret;
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if (priv->hw_version > MLXBF_GIGE_VERSION_BF3)
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return -ENODEV;
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priv->mdio_io = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_MDIO9);
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if (IS_ERR(priv->mdio_io))
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return PTR_ERR(priv->mdio_io);
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@ -242,13 +312,15 @@ int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv)
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/* For backward compatibility with older ACPI tables, also keep
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* CLK resource internal to the driver.
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*/
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res = &corepll_params[MLXBF_GIGE_VERSION_BF2];
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res = &corepll_params[priv->hw_version];
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}
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priv->clk_io = devm_ioremap(dev, res->start, resource_size(res));
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if (!priv->clk_io)
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return -ENOMEM;
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priv->mdio_gw = &mlxbf_gige_mdio_gw_t[priv->hw_version];
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mlxbf_gige_mdio_cfg(priv);
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priv->mdiobus = devm_mdiobus_alloc(dev);
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@ -0,0 +1,53 @@
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
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/* MDIO support for Mellanox Gigabit Ethernet driver
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*
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* Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES, ALL RIGHTS RESERVED.
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*
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* This software product is a proprietary product of NVIDIA CORPORATION &
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* AFFILIATES (the "Company") and all right, title, and interest in and to the
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* software product, including all associated intellectual property rights, are
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* and shall remain exclusively with the Company.
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*
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* This software product is governed by the End User License Agreement
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* provided with the software product.
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*/
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#ifndef __MLXBF_GIGE_MDIO_BF2_H__
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#define __MLXBF_GIGE_MDIO_BF2_H__
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#include <linux/bitfield.h>
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#define MLXBF2_GIGE_MDIO_GW_OFFSET 0x0
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#define MLXBF2_GIGE_MDIO_CFG_OFFSET 0x4
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/* MDIO GW register bits */
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#define MLXBF2_GIGE_MDIO_GW_AD_MASK GENMASK(15, 0)
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#define MLXBF2_GIGE_MDIO_GW_DEVAD_MASK GENMASK(20, 16)
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#define MLXBF2_GIGE_MDIO_GW_PARTAD_MASK GENMASK(25, 21)
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#define MLXBF2_GIGE_MDIO_GW_OPCODE_MASK GENMASK(27, 26)
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#define MLXBF2_GIGE_MDIO_GW_ST1_MASK GENMASK(28, 28)
|
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#define MLXBF2_GIGE_MDIO_GW_BUSY_MASK GENMASK(30, 30)
|
||||
|
||||
#define MLXBF2_GIGE_MDIO_GW_AD_SHIFT 0
|
||||
#define MLXBF2_GIGE_MDIO_GW_DEVAD_SHIFT 16
|
||||
#define MLXBF2_GIGE_MDIO_GW_PARTAD_SHIFT 21
|
||||
#define MLXBF2_GIGE_MDIO_GW_OPCODE_SHIFT 26
|
||||
#define MLXBF2_GIGE_MDIO_GW_ST1_SHIFT 28
|
||||
#define MLXBF2_GIGE_MDIO_GW_BUSY_SHIFT 30
|
||||
|
||||
/* MDIO config register bits */
|
||||
#define MLXBF2_GIGE_MDIO_CFG_MDIO_MODE_MASK GENMASK(1, 0)
|
||||
#define MLXBF2_GIGE_MDIO_CFG_MDIO3_3_MASK GENMASK(2, 2)
|
||||
#define MLXBF2_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK GENMASK(4, 4)
|
||||
#define MLXBF2_GIGE_MDIO_CFG_MDC_PERIOD_MASK GENMASK(15, 8)
|
||||
#define MLXBF2_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK GENMASK(23, 16)
|
||||
#define MLXBF2_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK GENMASK(31, 24)
|
||||
|
||||
#define MLXBF2_GIGE_MDIO_CFG_VAL (FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_MODE_MASK, 1) | \
|
||||
FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO3_3_MASK, 1) | \
|
||||
FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK, 1) | \
|
||||
FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, 6) | \
|
||||
FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, 13))
|
||||
|
||||
#endif /* __MLXBF_GIGE_MDIO_BF2_H__ */
|
||||
@ -0,0 +1,54 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
|
||||
|
||||
/* MDIO support for Mellanox Gigabit Ethernet driver
|
||||
*
|
||||
* Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES, ALL RIGHTS RESERVED.
|
||||
*
|
||||
* This software product is a proprietary product of NVIDIA CORPORATION &
|
||||
* AFFILIATES (the "Company") and all right, title, and interest in and to the
|
||||
* software product, including all associated intellectual property rights, are
|
||||
* and shall remain exclusively with the Company.
|
||||
*
|
||||
* This software product is governed by the End User License Agreement
|
||||
* provided with the software product.
|
||||
*/
|
||||
|
||||
#ifndef __MLXBF_GIGE_MDIO_BF3_H__
|
||||
#define __MLXBF_GIGE_MDIO_BF3_H__
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
|
||||
#define MLXBF3_GIGE_MDIO_GW_OFFSET 0x80
|
||||
#define MLXBF3_GIGE_MDIO_DATA_READ 0x8c
|
||||
#define MLXBF3_GIGE_MDIO_CFG_REG0 0x100
|
||||
#define MLXBF3_GIGE_MDIO_CFG_REG1 0x104
|
||||
#define MLXBF3_GIGE_MDIO_CFG_REG2 0x108
|
||||
|
||||
/* MDIO GW register bits */
|
||||
#define MLXBF3_GIGE_MDIO_GW_ST1_MASK GENMASK(1, 1)
|
||||
#define MLXBF3_GIGE_MDIO_GW_OPCODE_MASK GENMASK(3, 2)
|
||||
#define MLXBF3_GIGE_MDIO_GW_PARTAD_MASK GENMASK(8, 4)
|
||||
#define MLXBF3_GIGE_MDIO_GW_DEVAD_MASK GENMASK(13, 9)
|
||||
/* For BlueField-3, this field is only used for mdio write */
|
||||
#define MLXBF3_GIGE_MDIO_GW_DATA_MASK GENMASK(29, 14)
|
||||
#define MLXBF3_GIGE_MDIO_GW_BUSY_MASK GENMASK(30, 30)
|
||||
|
||||
#define MLXBF3_GIGE_MDIO_GW_DATA_READ_MASK GENMASK(15, 0)
|
||||
|
||||
#define MLXBF3_GIGE_MDIO_GW_ST1_SHIFT 1
|
||||
#define MLXBF3_GIGE_MDIO_GW_OPCODE_SHIFT 2
|
||||
#define MLXBF3_GIGE_MDIO_GW_PARTAD_SHIFT 4
|
||||
#define MLXBF3_GIGE_MDIO_GW_DEVAD_SHIFT 9
|
||||
#define MLXBF3_GIGE_MDIO_GW_DATA_SHIFT 14
|
||||
#define MLXBF3_GIGE_MDIO_GW_BUSY_SHIFT 30
|
||||
|
||||
#define MLXBF3_GIGE_MDIO_GW_DATA_READ_SHIFT 0
|
||||
|
||||
/* MDIO config register bits */
|
||||
#define MLXBF3_GIGE_MDIO_CFG_MDIO_MODE_MASK GENMASK(1, 0)
|
||||
#define MLXBF3_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK GENMASK(2, 2)
|
||||
#define MLXBF3_GIGE_MDIO_CFG_MDC_PERIOD_MASK GENMASK(7, 0)
|
||||
#define MLXBF3_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK GENMASK(7, 0)
|
||||
#define MLXBF3_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK GENMASK(15, 8)
|
||||
|
||||
#endif /* __MLXBF_GIGE_MDIO_BF3_H__ */
|
||||
@ -10,6 +10,7 @@
|
||||
|
||||
#define MLXBF_GIGE_VERSION 0x0000
|
||||
#define MLXBF_GIGE_VERSION_BF2 0x0
|
||||
#define MLXBF_GIGE_VERSION_BF3 0x1
|
||||
#define MLXBF_GIGE_STATUS 0x0010
|
||||
#define MLXBF_GIGE_STATUS_READY BIT(0)
|
||||
#define MLXBF_GIGE_INT_STATUS 0x0028
|
||||
|
||||
Loading…
Reference in New Issue
Block a user