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arm64: dts: renesas: r9a07g043: Add RSPI{0,1,2} nodes
Add RSPI{0,1,2} nodes to R9A07G043 (RZ/G2UL) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501112926.47024-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -158,11 +158,52 @@
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status = "disabled";
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};
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spi1: spi@1004b000 {
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reg = <0 0x1004b000 0 0x400>;
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spi0: spi@1004ac00 {
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compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
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reg = <0 0x1004ac00 0 0x400>;
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interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>;
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resets = <&cpg R9A07G043_RSPI0_RST>;
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power-domains = <&cpg>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* place holder */
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status = "disabled";
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};
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spi1: spi@1004b000 {
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compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
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reg = <0 0x1004b000 0 0x400>;
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interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>;
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resets = <&cpg R9A07G043_RSPI1_RST>;
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power-domains = <&cpg>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@1004b400 {
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compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
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reg = <0 0x1004b400 0 0x400>;
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interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>;
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resets = <&cpg R9A07G043_RSPI2_RST>;
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power-domains = <&cpg>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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scif0: serial@1004b800 {
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