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- Remove unused dw_apb_clockevent_[pause|resume|stop] functions as

Browse Source 
they are unused since 2021 (David Alan Gilbert)
 
 - Make the sp804 driver user selectable as they may be unused on some
   platforms (Mark Brown)
 
 - Don't fail if the ti-dm does not describe an interrupt in the DT as
   this could be a normal situation if the PWM is used (Judith Mendez)
 
 - Always use cluster 0 counter as a clocksource on a multi-cluster
   system to prevent problems related to the time shifting between
   clusters if multiple per cluster clocksource is used (Paul Burton)
 
 - Move the RaLink system tick counter from the arch directory to the
   clocksource directory (Sergio Paracuellos)
 
 - Convert the owl-timer bindings into yaml schema (Ivaylo Ivanov)
 
 - Fix child node refcount handling on the TI DM by relying on the
   __free annotation to automatically release the refcount on the node
   (Javier Carrasco)
 
 - Remove pointless cast in the GPX driver as PTR_ERR already does that
   (Tang Bin)
 
 - Use of_property_present() for non-boolean properties where it is
   possible in the different drivers (Rob Herring)
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Merge tag 'timers-v6.13-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core

Pull clocksource/event updates from Daniel Lezcano:

  - Remove unused dw_apb_clockevent_[pause|resume|stop] functions as
    they are unused since 2021 (David Alan Gilbert)

  - Make the sp804 driver user selectable as they may be unused on some
    platforms (Mark Brown)

  - Don't fail if the ti-dm does not describe an interrupt in the DT as
    this could be a normal situation if the PWM is used (Judith Mendez)

  - Always use cluster 0 counter as a clocksource on a multi-cluster
    system to prevent problems related to the time shifting between
    clusters if multiple per cluster clocksource is used (Paul Burton)

  - Move the RaLink system tick counter from the arch directory to the
    clocksource directory (Sergio Paracuellos)

  - Convert the owl-timer bindings into yaml schema (Ivaylo Ivanov)

  - Fix child node refcount handling on the TI DM by relying on the
    __free annotation to automatically release the refcount on the node
    (Javier Carrasco)

  - Remove pointless cast in the GPX driver as PTR_ERR already does that
    (Tang Bin)

  - Use of_property_present() for non-boolean properties where it is
    possible in the different drivers (Rob Herring)

Link: https://lore.kernel.org/lkml/8d402321-96f1-47f7-9347-a850350d60de@linaro.org
This commit is contained in:
Thomas Gleixner 2024-11-13 21:09:35 +01:00
commit 228ad72e76
15 changed files with 174 additions and 90 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
Documentation/devicetree/bindings/timer/actions,owl-timer.txt
View File

@ -1,21 +0,0 @@
Actions Semi Owl Timer
Required properties:
- compatible : "actions,s500-timer" for S500
"actions,s700-timer" for S700
"actions,s900-timer" for S900
- reg : Offset and length of the register set for the device.
- interrupts : Should contain the interrupts.
- interrupt-names : Valid names are: "2hz0", "2hz1",
"timer0", "timer1", "timer2", "timer3"
See ../resource-names.txt
Example:
timer@b0168000 {
compatible = "actions,s500-timer";
reg = <0xb0168000 0x100>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "timer0", "timer1";
};

107
Documentation/devicetree/bindings/timer/actions,owl-timer.yaml Normal file
View File

@ -0,0 +1,107 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/actions,owl-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Actions Semi Owl timer
maintainers:
- Andreas Färber <afaerber@suse.de>
description:
Actions Semi Owl SoCs provide 32bit and 2Hz timers.
The 32bit timers support dynamic irq, as well as one-shot mode.
properties:
compatible:
enum:
- actions,s500-timer
- actions,s700-timer
- actions,s900-timer
clocks:
maxItems: 1
interrupts:
minItems: 1
maxItems: 6
interrupt-names:
minItems: 1
maxItems: 6
items:
enum:
- 2hz0
- 2hz1
- timer0
- timer1
- timer2
- timer3
reg:
maxItems: 1
required:
- compatible
- clocks
- interrupts
- interrupt-names
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- actions,s500-timer
then:
properties:
interrupts:
minItems: 4
maxItems: 4
interrupt-names:
items:
- const: 2hz0
- const: 2hz1
- const: timer0
- const: timer1
- if:
properties:
compatible:
contains:
enum:
- actions,s700-timer
- actions,s900-timer
then:
properties:
interrupts:
minItems: 1
maxItems: 1
interrupt-names:
items:
- const: timer1
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
soc {
#address-cells = <1>;
#size-cells = <1>;
timer@b0168000 {
compatible = "actions,s500-timer";
reg = <0xb0168000 0x100>;
clocks = <&hosc>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "2hz0", "2hz1", "timer0", "timer1";
};
};
...

2
MAINTAINERS
View File

@ -2004,7 +2004,7 @@ F: Documentation/devicetree/bindings/mmc/owl-mmc.yaml
F: Documentation/devicetree/bindings/net/actions,owl-emac.yaml
F: Documentation/devicetree/bindings/pinctrl/actions,*
F: Documentation/devicetree/bindings/power/actions,owl-sps.txt
F: Documentation/devicetree/bindings/timer/actions,owl-timer.txt
F: Documentation/devicetree/bindings/timer/actions,owl-timer.yaml
F: arch/arm/boot/dts/actions/
F: arch/arm/mach-actions/
F: arch/arm64/boot/dts/actions/

7
arch/mips/ralink/Kconfig
View File

@ -1,13 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
if RALINK
config CLKEVT_RT3352
bool
depends on SOC_RT305X || SOC_MT7620
default y
select TIMER_OF
select CLKSRC_MMIO
config RALINK_ILL_ACC
bool
depends on SOC_RT305X

2
arch/mips/ralink/Makefile
View File

@ -10,8 +10,6 @@ ifndef CONFIG_MIPS_GIC
obj-y += clk.o timer.o
endif
obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
obj-$(CONFIG_IRQ_INTC) += irq.o

12
drivers/clocksource/Kconfig
View File

@ -400,7 +400,8 @@ config ARM_GT_INITIAL_PRESCALER_VAL
This affects CPU_FREQ max delta from the initial frequency.
config ARM_TIMER_SP804
bool "Support for Dual Timer SP804 module" if COMPILE_TEST
bool "Support for Dual Timer SP804 module"
depends on ARM || ARM64 || COMPILE_TEST
depends on GENERIC_SCHED_CLOCK && HAVE_CLK
select CLKSRC_MMIO
select TIMER_OF if OF
@ -753,4 +754,13 @@ config EP93XX_TIMER
Enables support for the Cirrus Logic timer block
EP93XX.
config RALINK_TIMER
bool "Ralink System Tick Counter"
depends on SOC_RT305X || SOC_MT7620 || COMPILE_TEST
select CLKSRC_MMIO
select TIMER_OF
help
Enables support for system tick counter present on
Ralink SoCs RT3352 and MT7620.
endmenu

1
drivers/clocksource/Makefile
View File

@ -91,3 +91,4 @@ obj-$(CONFIG_GOLDFISH_TIMER) += timer-goldfish.o
obj-$(CONFIG_GXP_TIMER) += timer-gxp.o
obj-$(CONFIG_CLKSRC_LOONGSON1_PWM) += timer-loongson1-pwm.o
obj-$(CONFIG_EP93XX_TIMER) += timer-ep93xx.o
obj-$(CONFIG_RALINK_TIMER) += timer-ralink.o

2
drivers/clocksource/arm_arch_timer.c
View File

@ -1428,7 +1428,7 @@ static int __init arch_timer_of_init(struct device_node *np)
arch_timers_present |= ARCH_TIMER_TYPE_CP15;
has_names = of_property_read_bool(np, "interrupt-names");
has_names = of_property_present(np, "interrupt-names");
for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++) {
if (has_names)

39
drivers/clocksource/dw_apb_timer.c
View File

@ -68,25 +68,6 @@ static inline void apbt_writel_relaxed(struct dw_apb_timer *timer, u32 val,
writel_relaxed(val, timer->base + offs);
}
static void apbt_disable_int(struct dw_apb_timer *timer)
{
u32 ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
ctrl |= APBTMR_CONTROL_INT;
apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
}
/**
* dw_apb_clockevent_pause() - stop the clock_event_device from running
*
* @dw_ced: The APB clock to stop generating events.
*/
void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced)
{
disable_irq(dw_ced->timer.irq);
apbt_disable_int(&dw_ced->timer);
}
static void apbt_eoi(struct dw_apb_timer *timer)
{
apbt_readl_relaxed(timer, APBTMR_N_EOI);
@ -284,26 +265,6 @@ dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
return dw_ced;
}
/**
* dw_apb_clockevent_resume() - resume a clock that has been paused.
*
* @dw_ced: The APB clock to resume.
*/
void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced)
{
enable_irq(dw_ced->timer.irq);
}
/**
* dw_apb_clockevent_stop() - stop the clock_event_device and release the IRQ.
*
* @dw_ced: The APB clock to stop generating the events.
*/
void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced)
{
free_irq(dw_ced->timer.irq, &dw_ced->ced);
}
/**
* dw_apb_clockevent_register() - register the clock with the generic layer
*

39
drivers/clocksource/mips-gic-timer.c
View File

@ -166,6 +166,37 @@ static u64 gic_hpt_read(struct clocksource *cs)
return gic_read_count();
}
static u64 gic_hpt_read_multicluster(struct clocksource *cs)
{
unsigned int hi, hi2, lo;
u64 count;
mips_cm_lock_other(0, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
if (mips_cm_is64) {
count = read_gic_redir_counter();
goto out;
}
hi = read_gic_redir_counter_32h();
while (true) {
lo = read_gic_redir_counter_32l();
/* If hi didn't change then lo didn't wrap & we're done */
hi2 = read_gic_redir_counter_32h();
if (hi2 == hi)
break;
/* Otherwise, repeat with the latest hi value */
hi = hi2;
}
count = (((u64)hi) << 32) + lo;
out:
mips_cm_unlock_other();
return count;
}
static struct clocksource gic_clocksource = {
.name = "GIC",
.read = gic_hpt_read,
@ -203,6 +234,11 @@ static int __init __gic_clocksource_init(void)
gic_clocksource.rating = 200;
gic_clocksource.rating += clamp(gic_frequency / 10000000, 0, 99);
if (mips_cps_multicluster_cpus()) {
gic_clocksource.read = &gic_hpt_read_multicluster;
gic_clocksource.vdso_clock_mode = VDSO_CLOCKMODE_NONE;
}
ret = clocksource_register_hz(&gic_clocksource, gic_frequency);
if (ret < 0)
pr_warn("Unable to register clocksource\n");
@ -261,7 +297,8 @@ static int __init gic_clocksource_of_init(struct device_node *node)
* stable CPU frequency or on the platforms with CM3 and CPU frequency
* change performed by the CPC core clocks divider.
*/
if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) {
if ((mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) &&
!mips_cps_multicluster_cpus()) {
sched_clock_register(mips_cm_is64 ?
gic_read_count_64 : gic_read_count_2x32,
gic_count_width, gic_frequency);

2
drivers/clocksource/timer-gxp.c
View File

@ -85,7 +85,7 @@ static int __init gxp_timer_init(struct device_node *node)
clk = of_clk_get(node, 0);
if (IS_ERR(clk)) {
ret = (int)PTR_ERR(clk);
ret = PTR_ERR(clk);
pr_err("%pOFn clock not found: %d\n", node, ret);
goto err_free;
}

11
arch/mips/ralink/cevt-rt3352.c → drivers/clocksource/timer-ralink.c
View File

@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
* Ralink System Tick Counter driver present on RT3352 and MT7620 SoCs.
*
* Copyright (C) 2013 by John Crispin <john@phrozen.org>
*/
@ -16,8 +15,6 @@
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <asm/mach-ralink/ralink_regs.h>
#define SYSTICK_FREQ (50 * 1000)
#define SYSTICK_CONFIG 0x00
@ -40,7 +37,7 @@ static int systick_set_oneshot(struct clock_event_device *evt);
static int systick_shutdown(struct clock_event_device *evt);
static int systick_next_event(unsigned long delta,
struct clock_event_device *evt)
struct clock_event_device *evt)
{
struct systick_device *sdev;
u32 count;
@ -60,7 +57,7 @@ static void systick_event_handler(struct clock_event_device *dev)
static irqreturn_t systick_interrupt(int irq, void *dev_id)
{
struct clock_event_device *dev = (struct clock_event_device *) dev_id;
struct clock_event_device *dev = (struct clock_event_device *)dev_id;
dev->event_handler(dev);

8
drivers/clocksource/timer-ti-dm-systimer.c
View File

@ -202,10 +202,10 @@ static bool __init dmtimer_is_preferred(struct device_node *np)
/* Secure gptimer12 is always clocked with a fixed source */
if (!of_property_read_bool(np, "ti,timer-secure")) {
if (!of_property_read_bool(np, "assigned-clocks"))
if (!of_property_present(np, "assigned-clocks"))
return false;
if (!of_property_read_bool(np, "assigned-clock-parents"))
if (!of_property_present(np, "assigned-clock-parents"))
return false;
}
@ -686,9 +686,9 @@ subsys_initcall(dmtimer_percpu_timer_startup);
static int __init dmtimer_percpu_quirk_init(struct device_node *np, u32 pa)
{
struct device_node *arm_timer;
struct device_node *arm_timer __free(device_node) =
of_find_compatible_node(NULL, NULL, "arm,armv7-timer");
arm_timer = of_find_compatible_node(NULL, NULL, "arm,armv7-timer");
if (of_device_is_available(arm_timer)) {
pr_warn_once("ARM architected timer wrap issue i940 detected\n");
return 0;

8
drivers/clocksource/timer-ti-dm.c
View File

@ -1104,8 +1104,12 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
return -ENOMEM;
timer->irq = platform_get_irq(pdev, 0);
if (timer->irq < 0)
return timer->irq;
if (timer->irq < 0) {
if (of_property_read_bool(dev->of_node, "ti,timer-pwm"))
dev_info(dev, "Did not find timer interrupt, timer usable in PWM mode only\n");
else
return timer->irq;
}
timer->io_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(timer->io_base))

3
include/linux/dw_apb_timer.h
View File

@ -34,9 +34,6 @@ struct dw_apb_clocksource {
};
void dw_apb_clockevent_register(struct dw_apb_clock_event_device *dw_ced);
void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced);
void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced);
void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced);
struct dw_apb_clock_event_device *
dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,