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spi: spi-zynqmp-gqspi: Set CPOL and CPHA during hardware init

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During every transfer GQSPI driver writes the CPOL & CPHA values to the
configuration register. But the CPOL & CPHA values do not change in between
multiple transfers, so moved the CPOL & CPHA initialization to hardware
init so that the values are written only once.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Link: https://lore.kernel.org/r/20221011062040.12116-3-amit.kumar-mahapatra@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Amit Kumar Mahapatra 2022-10-11 11:50:35 +05:30 committed by Mark Brown
parent b3b953084b
commit 22742b8bbd
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GPG Key ID: 24D68B725D5487D0
1 changed files with 17 additions and 15 deletions
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32
drivers/spi/spi-zynqmp-gqspi.c
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@ -266,7 +266,9 @@ static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
* - Enable manual slave select * - Enable manual slave select
* - Enable manual start * - Enable manual start
* - Deselect all the chip select lines * - Deselect all the chip select lines
* - Set the little endian mode of TX FIFO and * - Set the little endian mode of TX FIFO
* - Set clock phase
* - Set clock polarity and
* - Enable the QSPI controller * - Enable the QSPI controller
*/ */
static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi) static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
@ -305,10 +307,17 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
config_reg |= GQSPI_CFG_WP_HOLD_MASK; config_reg |= GQSPI_CFG_WP_HOLD_MASK;
/* Clear pre-scalar by default */ /* Clear pre-scalar by default */
config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
/* CPHA 0 */ /* Set CPHA */
config_reg &= ~GQSPI_CFG_CLK_PHA_MASK; if (xqspi->ctlr->mode_bits & SPI_CPHA)
/* CPOL 0 */ config_reg |= GQSPI_CFG_CLK_PHA_MASK;
config_reg &= ~GQSPI_CFG_CLK_POL_MASK; else
config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
/* Set CPOL */
if (xqspi->ctlr->mode_bits & SPI_CPOL)
config_reg |= GQSPI_CFG_CLK_POL_MASK;
else
config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
/* Clear the TX and RX FIFO */ /* Clear the TX and RX FIFO */
@ -470,14 +479,6 @@ static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,
config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
/* Set the QSPI clock phase and clock polarity */
config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
if (qspi->mode & SPI_CPHA)
config_reg |= GQSPI_CFG_CLK_PHA_MASK;
if (qspi->mode & SPI_CPOL)
config_reg |= GQSPI_CFG_CLK_POL_MASK;
config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT); config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
@ -1170,6 +1171,9 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
goto clk_dis_all; goto clk_dis_all;
} }
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
SPI_TX_DUAL | SPI_TX_QUAD;
/* QSPI controller initializations */ /* QSPI controller initializations */
zynqmp_qspi_init_hw(xqspi); zynqmp_qspi_init_hw(xqspi);
@ -1207,8 +1211,6 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
ctlr->setup = zynqmp_qspi_setup_op; ctlr->setup = zynqmp_qspi_setup_op;
ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
ctlr->bits_per_word_mask = SPI_BPW_MASK(8); ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
SPI_TX_DUAL | SPI_TX_QUAD;
ctlr->dev.of_node = np; ctlr->dev.of_node = np;
ctlr->auto_runtime_pm = true; ctlr->auto_runtime_pm = true;