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Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes
Daniel writes: "Two tiny patches and one revert: - Kill a bogus error message introduced in 3.4, further Bspec reading indicates that this is how the hw is supposed to work. - Reorder one backlight register restore, fixing broken backlight on some machines after resume. - Revert a hack from Jesse for ivb backlight control - it breaks the backlight controls on my shiny new ivb laptop." * 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel: Revert "drm/i915: allow PCH PWM override on IVB" drm/i915: Fix eDP blank screen after S3 resume on HP desktops drm/i915: rip out the PM_IIR WARN
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commit
2266b058d3
@ -412,7 +412,6 @@ static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
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*/
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spin_lock_irqsave(&dev_priv->rps_lock, flags);
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WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
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dev_priv->pm_iir |= pm_iir;
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I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
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POSTING_READ(GEN6_PMIMR);
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@ -740,8 +740,11 @@ static void i915_restore_display(struct drm_device *dev)
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if (HAS_PCH_SPLIT(dev)) {
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I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
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I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
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I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
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/* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
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* otherwise we get blank eDP screen after S3 on some machines
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*/
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I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
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I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
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I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
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I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
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I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
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@ -6921,19 +6921,6 @@ static void i915_disable_vga(struct drm_device *dev)
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POSTING_READ(vga_reg);
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}
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static void ivb_pch_pwm_override(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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/*
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* IVB has CPU eDP backlight regs too, set things up to let the
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* PCH regs control the backlight
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*/
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I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
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I915_WRITE(BLC_PWM_CPU_CTL, 0);
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I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
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}
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void intel_modeset_init_hw(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -6950,9 +6937,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
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gen6_enable_rps(dev_priv);
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gen6_update_ring_freq(dev_priv);
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}
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if (IS_IVYBRIDGE(dev))
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ivb_pch_pwm_override(dev);
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}
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void intel_modeset_init(struct drm_device *dev)
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