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intel-pinctrl for v5.13-1
* Don't disable disabled IRQs in the handler * Fix the base calculation for groups defined by size The following is an automated git shortlog grouped by driver: intel: - No need to disable IRQs in the handler - Show the GPIO base calculation explicitly -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmBh6oAACgkQb7wzTHR8 rCgM4hAAmOYYpWsG+rZ9FOBY5C5qQeHvrzDEsEzjDIkYvuxltS2bGVNnZJkeqCua 8dVxumzKL1m7LaP+xOWVCKMyd8MrX8ZLQLxO4KTPMwW8/GkjBCnO2WZIlaVY8vFr 48mcsYXY3m90XlHINMxWu60e0h2GP90Qw1hwyp4J8X2llzZEVZOegSUdW3G9idZk xL7GARAWekJab8jRWnpHALRCas54XyEGcqVkkiRk/23SHa5HLbk/DZWIGpVT0ySA Fw6hGGnXDGc0GhZNqOEP8JDaR71Nrzq0S1HkWfRakGoR22yLXe1jLLaWojJ1U28j fELjqw7NfdXmDihLluHklWWLHlnN/lJp6m08E6tEC+yLKzl7B/GzvaUSFTPElslr YlbDjubDFBIaOW2Ypmp+k9jFdIlLyyrBV3WTzMQKQVE5i7A6S7bK692+DlPP2gNC qwYbo9f8eZQkE1X/q3TKA4jJIBkWDcR1cv9pzI2ADUq4nOLND+3VbaaDp1m0A2a/ 3LSPGnrbBLt0PRcKFRuE6Uz8eA4PpyvMTLJztM7JUpH0nIOdhvZwqEJZjX4Qo43R +0dVJIDki0tezOITYv0kHvBdctDcVd/SED/UmS15zCmJbmSUsFsoyghyJs1bsM9h 17Xeaj7L/twv/8QHqJQvodDj8808xAQT8M7xY6j2MKCKwx3QR2A= =SaxW -----END PGP SIGNATURE----- Merge tag 'intel-pinctrl-v5.13-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.13-1 * Don't disable disabled IRQs in the handler * Fix the base calculation for groups defined by size The following is an automated git shortlog grouped by driver: intel: - No need to disable IRQs in the handler - Show the GPIO base calculation explicitly
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commit
22667a63fe
@ -1173,16 +1173,15 @@ static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
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for (gpp = 0; gpp < community->ngpps; gpp++) {
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const struct intel_padgroup *padgrp = &community->gpps[gpp];
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unsigned long pending, enabled, gpp_offset;
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unsigned long flags;
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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raw_spin_lock(&pctrl->lock);
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pending = readl(community->regs + community->is_offset +
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padgrp->reg_num * 4);
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enabled = readl(community->regs + community->ie_offset +
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padgrp->reg_num * 4);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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raw_spin_unlock(&pctrl->lock);
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/* Only interrupts that are enabled */
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pending &= enabled;
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@ -1357,6 +1356,7 @@ static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
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gpps[i].gpio_base = 0;
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break;
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case INTEL_GPIO_BASE_NOMAP:
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break;
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default:
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break;
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}
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@ -1393,6 +1393,7 @@ static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
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gpps[i].size = min(gpp_size, npins);
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npins -= gpps[i].size;
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gpps[i].gpio_base = gpps[i].base;
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gpps[i].padown_num = padown_num;
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/*
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