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kbuild: skip parsing pre sub-make code for recursion
When Make recurses to the top Makefile with sub-make-done unset, the code block surrounded by 'ifneq ($(sub-make-done),1) ... endif' is parsed multiple times. This happens for in-tree building of include/config/auto.conf, *-pkg, etc. with GNU Make 4.x. This is a slight regression by commit688931a5ad
("kbuild: skip sub-make for in-tree build with GNU Make 4.x") in terms of performance since that code block contains one $(shell ...) invocation. Fix it by exporting the variable irrespective of sub-make being run. I renamed it because GNU Make cannot properly export variables containing hyphens. This is probably a bug of GNU Make, and the issue in Kbuild had already been reported by commit2bfbe7881e
("kbuild: Do not use hyphen in exported variable name"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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parent
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commit
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8
Makefile
8
Makefile
@ -31,7 +31,7 @@ _all:
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# descending is started. They are now explicitly listed as the
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# prepare rule.
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ifneq ($(sub-make-done),1)
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ifneq ($(sub_make_done),1)
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# Do not use make's built-in rules and variables
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# (this increases performance and avoids hard-to-debug behaviour)
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@ -155,6 +155,8 @@ need-sub-make := 1
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$(lastword $(MAKEFILE_LIST)): ;
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endif
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export sub_make_done := 1
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ifeq ($(need-sub-make),1)
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PHONY += $(MAKECMDGOALS) sub-make
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@ -164,12 +166,12 @@ $(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make
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# Invoke a second make in the output directory, passing relevant variables
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sub-make:
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$(Q)$(MAKE) sub-make-done=1 \
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$(Q)$(MAKE) \
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$(if $(KBUILD_OUTPUT),-C $(KBUILD_OUTPUT) KBUILD_SRC=$(CURDIR)) \
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-f $(CURDIR)/Makefile $(filter-out _all sub-make,$(MAKECMDGOALS))
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endif # need-sub-make
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endif # sub-make-done
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endif # sub_make_done
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# We process the rest of the Makefile if this is the final invocation of make
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ifeq ($(need-sub-make),)
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