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ARM: dts: r7s72100: Remove unnecessary clock-output-names properties

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* Fixed rate and fixed factor clocks do not require an
  clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
  optional") Renesas div6 clocks do not require a clock-output-names
  property.

In the above cases there is only one clock output and its name is taken
from that of the clock node.  Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Simon Horman 2016-03-18 08:10:44 +09:00
parent b19dd47b27
commit 21f1897059
1 changed files with 5 additions and 10 deletions
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15
arch/arm/boot/dts/r7s72100.dtsi
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@ -37,46 +37,41 @@
#size-cells = <1>; #size-cells = <1>;
/* External clocks */ /* External clocks */
extal_clk: extal_clk { extal_clk: extal {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
/* If clk present, value must be set by board */ /* If clk present, value must be set by board */
clock-frequency = <0>; clock-frequency = <0>;
clock-output-names = "extal";
}; };
usb_x1_clk: usb_x1_clk { usb_x1_clk: usb_x1 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
/* If clk present, value must be set by board */ /* If clk present, value must be set by board */
clock-frequency = <0>; clock-frequency = <0>;
clock-output-names = "usb_x1";
}; };
/* Fixed factor clocks */ /* Fixed factor clocks */
b_clk: b_clk { b_clk: b {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R7S72100_CLK_PLL>; clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>; clock-mult = <1>;
clock-div = <3>; clock-div = <3>;
clock-output-names = "b";
}; };
p1_clk: p1_clk { p1_clk: p1 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R7S72100_CLK_PLL>; clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>; clock-mult = <1>;
clock-div = <6>; clock-div = <6>;
clock-output-names = "p1";
}; };
p0_clk: p0_clk { p0_clk: p0 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R7S72100_CLK_PLL>; clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>; clock-mult = <1>;
clock-div = <12>; clock-div = <12>;
clock-output-names = "p0";
}; };
/* Special CPG clocks */ /* Special CPG clocks */