korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-11-11 21:38:32 +08:00
Code Issues Packages Projects Releases Wiki Activity

clk: qcom: Don't overwrite 'cfg' in clk_rcg2_dfs_populate_freq()

Browse Source 
The DFS frequency table logic overwrites 'cfg' while detecting the
parent clk and then later on in clk_rcg2_dfs_populate_freq() we use that
same variable to figure out the mode of the clk, either MND or not. Add
a new variable to hold the parent clk bit so that 'cfg' is left
untouched for use later.

This fixes problems in detecting the supported frequencies for any clks
in DFS mode.

Fixes: cc4f6944d0 ("clk: qcom: Add support for RCG to register for DFS")
Reported-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200128193329.45635-1-sboyd@kernel.org
Tested-by: Rajendra Nayak <rnayak@codeaurora.org>
This commit is contained in:
Stephen Boyd 2020-01-28 11:33:29 -08:00
parent fc6a15c853
commit 21e157c62e
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/clk/qcom/clk-rcg2.c
View File

@ -953,7 +953,7 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
struct clk_rcg2 *rcg = to_clk_rcg2(hw); struct clk_rcg2 *rcg = to_clk_rcg2(hw);
struct clk_hw *p; struct clk_hw *p;
unsigned long prate = 0; unsigned long prate = 0;
u32 val, mask, cfg, mode; u32 val, mask, cfg, mode, src;
int i, num_parents; int i, num_parents;
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg); regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg);
@ -963,12 +963,12 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
if (cfg & mask) if (cfg & mask)
f->pre_div = cfg & mask; f->pre_div = cfg & mask;
cfg &= CFG_SRC_SEL_MASK; src = cfg & CFG_SRC_SEL_MASK;
cfg >>= CFG_SRC_SEL_SHIFT; src >>= CFG_SRC_SEL_SHIFT;
num_parents = clk_hw_get_num_parents(hw); num_parents = clk_hw_get_num_parents(hw);
for (i = 0; i < num_parents; i++) { for (i = 0; i < num_parents; i++) {
if (cfg == rcg->parent_map[i].cfg) { if (src == rcg->parent_map[i].cfg) {
f->src = rcg->parent_map[i].src; f->src = rcg->parent_map[i].src;
p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i); p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i);
prate = clk_hw_get_rate(p); prate = clk_hw_get_rate(p);