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bpf, riscv: Implement bpf_addr_space_cast instruction
LLVM generates bpf_addr_space_cast instruction while translating pointers between native (zero) address space and __attribute__((address_space(N))). The addr_space=0 is reserved as bpf_arena address space. rY = addr_space_cast(rX, 0, 1) is processed by the verifier and converted to normal 32-bit move: wX = wY rY = addr_space_cast(rX, 1, 0) has to be converted by JIT. Signed-off-by: Puranjay Mohan <puranjay12@gmail.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Tested-by: Björn Töpel <bjorn@rivosinc.com> Tested-by: Pu Lehui <pulehui@huawei.com> Reviewed-by: Pu Lehui <pulehui@huawei.com> Acked-by: Björn Töpel <bjorn@kernel.org> Link: https://lore.kernel.org/bpf/20240404114203.105970-3-puranjay12@gmail.com
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@ -82,6 +82,7 @@ struct rv_jit_context {
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unsigned long flags;
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int stack_size;
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u64 arena_vm_start;
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u64 user_vm_start;
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};
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/* Convert from ninsns to bytes. */
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@ -1081,6 +1081,15 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
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/* dst = src */
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case BPF_ALU | BPF_MOV | BPF_X:
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case BPF_ALU64 | BPF_MOV | BPF_X:
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if (insn_is_cast_user(insn)) {
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emit_mv(RV_REG_T1, rs, ctx);
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emit_zextw(RV_REG_T1, RV_REG_T1, ctx);
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emit_imm(rd, (ctx->user_vm_start >> 32) << 32, ctx);
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emit(rv_beq(RV_REG_T1, RV_REG_ZERO, 4), ctx);
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emit_or(RV_REG_T1, rd, RV_REG_T1, ctx);
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emit_mv(rd, RV_REG_T1, ctx);
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break;
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}
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if (imm == 1) {
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/* Special mov32 for zext */
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emit_zextw(rd, rd, ctx);
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@ -2024,3 +2033,8 @@ bool bpf_jit_supports_ptr_xchg(void)
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{
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return true;
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}
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bool bpf_jit_supports_arena(void)
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{
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return true;
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}
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@ -81,6 +81,7 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
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}
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ctx->arena_vm_start = bpf_arena_get_kern_vm_start(prog->aux->arena);
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ctx->user_vm_start = bpf_arena_get_user_vm_start(prog->aux->arena);
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ctx->prog = prog;
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ctx->offset = kcalloc(prog->len, sizeof(int), GFP_KERNEL);
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if (!ctx->offset) {
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