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nvme-pci: do not directly handle subsys reset fallout
Scheduling reset_work after a nvme subsystem reset is expected to fail on pcie, but this also prevents potential handling the platform's pcie services may provide that might successfully recovering the link without re-enumeration. Such examples include AER, DPC, and power's EEH. Provide a pci specific operation that safely initiates a subsystem reset, and instead of scheduling reset work, read back the status register to trigger a pcie read error. Since this only affects pci, the other fabrics drivers subscribe to a generic nvmf subsystem reset that is exactly the same as before. The loop fabric doesn't use it because nvmet doesn't support setting that property anyway. And since we're using the magic NSSR value in two places now, provide a symbolic define for it. Reported-by: Nilay Shroff <nilay@linux.ibm.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Keith Busch <kbusch@kernel.org>
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@ -280,6 +280,21 @@ int nvmf_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
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}
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EXPORT_SYMBOL_GPL(nvmf_reg_write32);
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int nvmf_subsystem_reset(struct nvme_ctrl *ctrl)
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{
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int ret;
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if (!nvme_wait_reset(ctrl))
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return -EBUSY;
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ret = ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, NVME_SUBSYS_RESET);
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if (ret)
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return ret;
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return nvme_try_sched_reset(ctrl);
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}
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EXPORT_SYMBOL_GPL(nvmf_subsystem_reset);
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/**
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* nvmf_log_connect_error() - Error-parsing-diagnostic print out function for
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* connect() errors.
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@ -217,6 +217,7 @@ static inline unsigned int nvmf_nr_io_queues(struct nvmf_ctrl_options *opts)
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int nvmf_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val);
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int nvmf_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val);
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int nvmf_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val);
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int nvmf_subsystem_reset(struct nvme_ctrl *ctrl);
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int nvmf_connect_admin_queue(struct nvme_ctrl *ctrl);
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int nvmf_connect_io_queue(struct nvme_ctrl *ctrl, u16 qid);
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int nvmf_register_transport(struct nvmf_transport_ops *ops);
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@ -3382,6 +3382,7 @@ static const struct nvme_ctrl_ops nvme_fc_ctrl_ops = {
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.reg_read32 = nvmf_reg_read32,
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.reg_read64 = nvmf_reg_read64,
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.reg_write32 = nvmf_reg_write32,
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.subsystem_reset = nvmf_subsystem_reset,
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.free_ctrl = nvme_fc_free_ctrl,
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.submit_async_event = nvme_fc_submit_async_event,
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.delete_ctrl = nvme_fc_delete_ctrl,
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@ -551,6 +551,7 @@ struct nvme_ctrl_ops {
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int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
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void (*free_ctrl)(struct nvme_ctrl *ctrl);
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void (*submit_async_event)(struct nvme_ctrl *ctrl);
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int (*subsystem_reset)(struct nvme_ctrl *ctrl);
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void (*delete_ctrl)(struct nvme_ctrl *ctrl);
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void (*stop_ctrl)(struct nvme_ctrl *ctrl);
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int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
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@ -649,18 +650,9 @@ int nvme_try_sched_reset(struct nvme_ctrl *ctrl);
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static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
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{
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int ret;
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if (!ctrl->subsystem)
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if (!ctrl->subsystem || !ctrl->ops->subsystem_reset)
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return -ENOTTY;
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if (!nvme_wait_reset(ctrl))
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return -EBUSY;
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ret = ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
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if (ret)
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return ret;
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return nvme_try_sched_reset(ctrl);
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return ctrl->ops->subsystem_reset(ctrl);
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}
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/*
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@ -1143,6 +1143,41 @@ static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
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spin_unlock(&nvmeq->sq_lock);
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}
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static int nvme_pci_subsystem_reset(struct nvme_ctrl *ctrl)
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{
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struct nvme_dev *dev = to_nvme_dev(ctrl);
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int ret = 0;
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/*
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* Taking the shutdown_lock ensures the BAR mapping is not being
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* altered by reset_work. Holding this lock before the RESETTING state
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* change, if successful, also ensures nvme_remove won't be able to
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* proceed to iounmap until we're done.
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*/
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mutex_lock(&dev->shutdown_lock);
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if (!dev->bar_mapped_size) {
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ret = -ENODEV;
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goto unlock;
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}
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if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) {
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ret = -EBUSY;
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goto unlock;
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}
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writel(NVME_SUBSYS_RESET, dev->bar + NVME_REG_NSSR);
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nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE);
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/*
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* Read controller status to flush the previous write and trigger a
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* pcie read error.
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*/
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readl(dev->bar + NVME_REG_CSTS);
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unlock:
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mutex_unlock(&dev->shutdown_lock);
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return ret;
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}
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static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
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{
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struct nvme_command c = { };
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@ -2859,6 +2894,7 @@ static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
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.reg_read64 = nvme_pci_reg_read64,
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.free_ctrl = nvme_pci_free_ctrl,
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.submit_async_event = nvme_pci_submit_async_event,
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.subsystem_reset = nvme_pci_subsystem_reset,
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.get_address = nvme_pci_get_address,
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.print_device_info = nvme_pci_print_device_info,
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.supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
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@ -2201,6 +2201,7 @@ static const struct nvme_ctrl_ops nvme_rdma_ctrl_ops = {
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.reg_read32 = nvmf_reg_read32,
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.reg_read64 = nvmf_reg_read64,
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.reg_write32 = nvmf_reg_write32,
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.subsystem_reset = nvmf_subsystem_reset,
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.free_ctrl = nvme_rdma_free_ctrl,
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.submit_async_event = nvme_rdma_submit_async_event,
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.delete_ctrl = nvme_rdma_delete_ctrl,
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@ -2662,6 +2662,7 @@ static const struct nvme_ctrl_ops nvme_tcp_ctrl_ops = {
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.reg_read32 = nvmf_reg_read32,
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.reg_read64 = nvmf_reg_read64,
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.reg_write32 = nvmf_reg_write32,
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.subsystem_reset = nvmf_subsystem_reset,
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.free_ctrl = nvme_tcp_free_ctrl,
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.submit_async_event = nvme_tcp_submit_async_event,
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.delete_ctrl = nvme_tcp_delete_ctrl,
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@ -25,6 +25,9 @@
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#define NVME_NSID_ALL 0xffffffff
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/* Special NSSR value, 'NVMe' */
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#define NVME_SUBSYS_RESET 0x4E564D65
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enum nvme_subsys_type {
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/* Referral to another discovery type target subsystem */
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NVME_NQN_DISC = 1,
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