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arm64: Check if GMID_EL1.BS is the same on all CPUs
The GMID_EL1.BS field determines the number of tags accessed by the LDGM/STGM instructions (EL1 and up), used by the kernel for copying or zeroing page tags. Taint the kernel if GMID_EL1.BS differs between CPUs but only of CONFIG_ARM64_MTE is enabled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com> Link: https://lore.kernel.org/r/20210526193621.21559-3-catalin.marinas@arm.com Signed-off-by: Will Deacon <will@kernel.org>
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@ -20,6 +20,7 @@ struct cpuinfo_arm64 {
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u64 reg_dczid;
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u64 reg_midr;
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u64 reg_revidr;
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u64 reg_gmid;
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u64 reg_id_aa64dfr0;
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u64 reg_id_aa64dfr1;
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@ -619,6 +619,13 @@ static inline bool id_aa64pfr0_sve(u64 pfr0)
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return val > 0;
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}
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static inline bool id_aa64pfr1_mte(u64 pfr1)
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{
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u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_MTE_SHIFT);
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return val >= ID_AA64PFR1_MTE;
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}
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void __init setup_cpu_features(void);
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void check_local_cpu_capabilities(void);
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@ -400,6 +400,11 @@ static const struct arm64_ftr_bits ftr_dczid[] = {
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ARM64_FTR_END,
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};
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static const struct arm64_ftr_bits ftr_gmid[] = {
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),
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ARM64_FTR_END,
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};
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static const struct arm64_ftr_bits ftr_id_isar0[] = {
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
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@ -617,6 +622,9 @@ static const struct __ftr_reg_entry {
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/* Op1 = 0, CRn = 1, CRm = 2 */
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ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
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/* Op1 = 1, CRn = 0, CRm = 0 */
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ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
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/* Op1 = 3, CRn = 0, CRm = 0 */
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{ SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
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ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
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@ -911,6 +919,9 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
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sve_init_vq_map();
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}
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if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
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init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
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/*
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* Initialize the indirect array of CPU hwcaps capabilities pointers
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* before we handle the boot CPU below.
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@ -1134,6 +1145,16 @@ void update_cpu_features(int cpu,
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sve_update_vq_map();
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}
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/*
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* The kernel uses the LDGM/STGM instructions and the number of tags
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* they read/write depends on the GMID_EL1.BS field. Check that the
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* value is the same on all CPUs.
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*/
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if (IS_ENABLED(CONFIG_ARM64_MTE) &&
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id_aa64pfr1_mte(info->reg_id_aa64pfr1))
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taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
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info->reg_gmid, boot->reg_gmid);
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/*
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* This relies on a sanitised view of the AArch64 ID registers
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* (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
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@ -371,6 +371,9 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
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info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
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info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
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if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
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info->reg_gmid = read_cpuid(GMID_EL1);
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/* Update the 32bit ID registers only if AArch32 is implemented */
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if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
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info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
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