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i3c: master: svc: use slow speed for first broadcast address
I3C controller should support adjusting open drain timing for the first broadcast address to make I3C device working as a i2c device can see slow broadcast address to close its Spike Filter to change working at i3c mode. Signed-off-by: Carlos Song <carlos.song@nxp.com> Reviewed-by: Frank Li <frank.li@nxp.com> Link: https://lore.kernel.org/r/20240910051626.4052552-2-carlos.song@nxp.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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@ -182,6 +182,7 @@ struct svc_i3c_regs_save {
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* @ibi.lock: IBI lock
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* @lock: Transfer lock, protect between IBI work thread and callbacks from master
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* @enabled_events: Bit masks for enable events (IBI, HotJoin).
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* @mctrl_config: Configuration value in SVC_I3C_MCTRL for setting speed back.
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*/
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struct svc_i3c_master {
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struct i3c_master_controller base;
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@ -212,6 +213,7 @@ struct svc_i3c_master {
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} ibi;
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struct mutex lock;
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int enabled_events;
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u32 mctrl_config;
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};
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/**
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@ -529,6 +531,54 @@ static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static int svc_i3c_master_set_speed(struct i3c_master_controller *m,
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enum i3c_open_drain_speed speed)
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{
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struct svc_i3c_master *master = to_svc_i3c_master(m);
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struct i3c_bus *bus = i3c_master_get_bus(&master->base);
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u32 ppbaud, odbaud, odhpp, mconfig;
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unsigned long fclk_rate;
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int ret;
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ret = pm_runtime_resume_and_get(master->dev);
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if (ret < 0) {
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dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
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return ret;
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}
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switch (speed) {
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case I3C_OPEN_DRAIN_SLOW_SPEED:
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fclk_rate = clk_get_rate(master->fclk);
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if (!fclk_rate) {
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ret = -EINVAL;
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goto rpm_out;
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}
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/*
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* Set 50% duty-cycle I2C speed to I3C OPEN-DRAIN mode, so the first
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* broadcast address is visible to all I2C/I3C devices on the I3C bus.
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* I3C device working as a I2C device will turn off its 50ns Spike
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* Filter to change to I3C mode.
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*/
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mconfig = master->mctrl_config;
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ppbaud = FIELD_GET(GENMASK(11, 8), mconfig);
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odhpp = 0;
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odbaud = DIV_ROUND_UP(fclk_rate, bus->scl_rate.i2c * (2 + 2 * ppbaud)) - 1;
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mconfig &= ~GENMASK(24, 16);
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mconfig |= SVC_I3C_MCONFIG_ODBAUD(odbaud) | SVC_I3C_MCONFIG_ODHPP(odhpp);
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writel(mconfig, master->regs + SVC_I3C_MCONFIG);
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break;
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case I3C_OPEN_DRAIN_NORMAL_SPEED:
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writel(master->mctrl_config, master->regs + SVC_I3C_MCONFIG);
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break;
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}
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rpm_out:
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pm_runtime_mark_last_busy(master->dev);
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pm_runtime_put_autosuspend(master->dev);
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return ret;
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}
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static int svc_i3c_master_bus_init(struct i3c_master_controller *m)
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{
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struct svc_i3c_master *master = to_svc_i3c_master(m);
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@ -611,6 +661,7 @@ static int svc_i3c_master_bus_init(struct i3c_master_controller *m)
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SVC_I3C_MCONFIG_I2CBAUD(i2cbaud);
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writel(reg, master->regs + SVC_I3C_MCONFIG);
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master->mctrl_config = reg;
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/* Master core's registration */
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ret = i3c_master_get_free_addr(m, 0);
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if (ret < 0)
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@ -1645,6 +1696,7 @@ static const struct i3c_master_controller_ops svc_i3c_master_ops = {
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.disable_ibi = svc_i3c_master_disable_ibi,
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.enable_hotjoin = svc_i3c_master_enable_hotjoin,
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.disable_hotjoin = svc_i3c_master_disable_hotjoin,
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.set_speed = svc_i3c_master_set_speed,
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};
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static int svc_i3c_master_prepare_clks(struct svc_i3c_master *master)
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