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https://mirrors.bfsu.edu.cn/git/linux.git
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Merge branch 'drm-etnaviv-fixes' of git://git.pengutronix.de/git/lst/linux into drm-fixes
A bunch of etnaviv fixes for 4.5-rc. Most of them are fixing things in code paths that will only be hit if something goes wrong, which have been unearthed by more extensive testing. The only thing that doesn't really qualify as fixes is an UAPI extension that userspace wants to rely on being present, so I want to fast-track this into 4.5 before etnaviv ends up in a released kernel. * 'drm-etnaviv-fixes' of git://git.pengutronix.de/git/lst/linux: drm/etnaviv: call correct function when trying to vmap a DMABUF drm/etnaviv: rename etnaviv_gem_vaddr to etnaviv_gem_vmap drm/etnaviv: fix get pages error path in etnaviv_gem_vaddr drm/etnaviv: fix memory leak in IOMMU init path drm/etnaviv: add further minor features and varyings count drm/etnaviv: add helper for comparing model/revision IDs drm/etnaviv: add helper to extract bitfields drm/etnaviv: use defined constants for the chip model drm/etnaviv: update common and state_hi xml.h files drm/etnaviv: ignore VG GPUs with FE2.0 drm/etnaviv: fix failure path if model is zero drm/etnaviv: hold object lock while getting pages for coredump drm/etnaviv: remove owner assignment from platform_driver
This commit is contained in:
Dave Airlie
commit
2081e78a5c
@ -8,8 +8,8 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
|
||||
git clone git://0x04.net/rules-ng-ng
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- state_vg.xml ( 5973 bytes, from 2015-03-25 11:26:01)
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||||
- common.xml ( 18437 bytes, from 2015-03-25 11:27:41)
|
||||
- state_hi.xml ( 24309 bytes, from 2015-12-12 09:02:53)
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||||
- common.xml ( 18379 bytes, from 2015-12-12 09:02:53)
|
||||
|
||||
Copyright (C) 2015
|
||||
*/
|
||||
@ -30,15 +30,19 @@ Copyright (C) 2015
|
||||
#define ENDIAN_MODE_NO_SWAP 0x00000000
|
||||
#define ENDIAN_MODE_SWAP_16 0x00000001
|
||||
#define ENDIAN_MODE_SWAP_32 0x00000002
|
||||
#define chipModel_GC200 0x00000200
|
||||
#define chipModel_GC300 0x00000300
|
||||
#define chipModel_GC320 0x00000320
|
||||
#define chipModel_GC328 0x00000328
|
||||
#define chipModel_GC350 0x00000350
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||||
#define chipModel_GC355 0x00000355
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||||
#define chipModel_GC400 0x00000400
|
||||
#define chipModel_GC410 0x00000410
|
||||
#define chipModel_GC420 0x00000420
|
||||
#define chipModel_GC428 0x00000428
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||||
#define chipModel_GC450 0x00000450
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||||
#define chipModel_GC500 0x00000500
|
||||
#define chipModel_GC520 0x00000520
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||||
#define chipModel_GC530 0x00000530
|
||||
#define chipModel_GC600 0x00000600
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||||
#define chipModel_GC700 0x00000700
|
||||
@ -46,9 +50,16 @@ Copyright (C) 2015
|
||||
#define chipModel_GC860 0x00000860
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||||
#define chipModel_GC880 0x00000880
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||||
#define chipModel_GC1000 0x00001000
|
||||
#define chipModel_GC1500 0x00001500
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||||
#define chipModel_GC2000 0x00002000
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||||
#define chipModel_GC2100 0x00002100
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||||
#define chipModel_GC2200 0x00002200
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||||
#define chipModel_GC2500 0x00002500
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||||
#define chipModel_GC3000 0x00003000
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||||
#define chipModel_GC4000 0x00004000
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||||
#define chipModel_GC5000 0x00005000
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||||
#define chipModel_GC5200 0x00005200
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||||
#define chipModel_GC6400 0x00006400
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||||
#define RGBA_BITS_R 0x00000001
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||||
#define RGBA_BITS_G 0x00000002
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||||
#define RGBA_BITS_B 0x00000004
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||||
@ -160,7 +171,7 @@ Copyright (C) 2015
|
||||
#define chipMinorFeatures2_UNK8 0x00000100
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||||
#define chipMinorFeatures2_UNK9 0x00000200
|
||||
#define chipMinorFeatures2_UNK10 0x00000400
|
||||
#define chipMinorFeatures2_SAMPLERBASE_16 0x00000800
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||||
#define chipMinorFeatures2_HALTI1 0x00000800
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||||
#define chipMinorFeatures2_UNK12 0x00001000
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||||
#define chipMinorFeatures2_UNK13 0x00002000
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||||
#define chipMinorFeatures2_UNK14 0x00004000
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||||
@ -189,7 +200,7 @@ Copyright (C) 2015
|
||||
#define chipMinorFeatures3_UNK5 0x00000020
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||||
#define chipMinorFeatures3_UNK6 0x00000040
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||||
#define chipMinorFeatures3_UNK7 0x00000080
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||||
#define chipMinorFeatures3_UNK8 0x00000100
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||||
#define chipMinorFeatures3_FAST_MSAA 0x00000100
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||||
#define chipMinorFeatures3_UNK9 0x00000200
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||||
#define chipMinorFeatures3_BUG_FIXES10 0x00000400
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||||
#define chipMinorFeatures3_UNK11 0x00000800
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||||
@ -199,7 +210,7 @@ Copyright (C) 2015
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#define chipMinorFeatures3_UNK15 0x00008000
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#define chipMinorFeatures3_UNK16 0x00010000
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||||
#define chipMinorFeatures3_UNK17 0x00020000
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||||
#define chipMinorFeatures3_UNK18 0x00040000
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||||
#define chipMinorFeatures3_ACE 0x00040000
|
||||
#define chipMinorFeatures3_UNK19 0x00080000
|
||||
#define chipMinorFeatures3_UNK20 0x00100000
|
||||
#define chipMinorFeatures3_UNK21 0x00200000
|
||||
@ -207,7 +218,7 @@ Copyright (C) 2015
|
||||
#define chipMinorFeatures3_UNK23 0x00800000
|
||||
#define chipMinorFeatures3_UNK24 0x01000000
|
||||
#define chipMinorFeatures3_UNK25 0x02000000
|
||||
#define chipMinorFeatures3_UNK26 0x04000000
|
||||
#define chipMinorFeatures3_NEW_HZ 0x04000000
|
||||
#define chipMinorFeatures3_UNK27 0x08000000
|
||||
#define chipMinorFeatures3_UNK28 0x10000000
|
||||
#define chipMinorFeatures3_UNK29 0x20000000
|
||||
@ -229,9 +240,9 @@ Copyright (C) 2015
|
||||
#define chipMinorFeatures4_UNK13 0x00002000
|
||||
#define chipMinorFeatures4_UNK14 0x00004000
|
||||
#define chipMinorFeatures4_UNK15 0x00008000
|
||||
#define chipMinorFeatures4_UNK16 0x00010000
|
||||
#define chipMinorFeatures4_HALTI2 0x00010000
|
||||
#define chipMinorFeatures4_UNK17 0x00020000
|
||||
#define chipMinorFeatures4_UNK18 0x00040000
|
||||
#define chipMinorFeatures4_SMALL_MSAA 0x00040000
|
||||
#define chipMinorFeatures4_UNK19 0x00080000
|
||||
#define chipMinorFeatures4_UNK20 0x00100000
|
||||
#define chipMinorFeatures4_UNK21 0x00200000
|
||||
@ -245,5 +256,37 @@ Copyright (C) 2015
|
||||
#define chipMinorFeatures4_UNK29 0x20000000
|
||||
#define chipMinorFeatures4_UNK30 0x40000000
|
||||
#define chipMinorFeatures4_UNK31 0x80000000
|
||||
#define chipMinorFeatures5_UNK0 0x00000001
|
||||
#define chipMinorFeatures5_UNK1 0x00000002
|
||||
#define chipMinorFeatures5_UNK2 0x00000004
|
||||
#define chipMinorFeatures5_UNK3 0x00000008
|
||||
#define chipMinorFeatures5_UNK4 0x00000010
|
||||
#define chipMinorFeatures5_UNK5 0x00000020
|
||||
#define chipMinorFeatures5_UNK6 0x00000040
|
||||
#define chipMinorFeatures5_UNK7 0x00000080
|
||||
#define chipMinorFeatures5_UNK8 0x00000100
|
||||
#define chipMinorFeatures5_HALTI3 0x00000200
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||||
#define chipMinorFeatures5_UNK10 0x00000400
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||||
#define chipMinorFeatures5_UNK11 0x00000800
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||||
#define chipMinorFeatures5_UNK12 0x00001000
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||||
#define chipMinorFeatures5_UNK13 0x00002000
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#define chipMinorFeatures5_UNK14 0x00004000
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||||
#define chipMinorFeatures5_UNK15 0x00008000
|
||||
#define chipMinorFeatures5_UNK16 0x00010000
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||||
#define chipMinorFeatures5_UNK17 0x00020000
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||||
#define chipMinorFeatures5_UNK18 0x00040000
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||||
#define chipMinorFeatures5_UNK19 0x00080000
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||||
#define chipMinorFeatures5_UNK20 0x00100000
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||||
#define chipMinorFeatures5_UNK21 0x00200000
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#define chipMinorFeatures5_UNK22 0x00400000
|
||||
#define chipMinorFeatures5_UNK23 0x00800000
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||||
#define chipMinorFeatures5_UNK24 0x01000000
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||||
#define chipMinorFeatures5_UNK25 0x02000000
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||||
#define chipMinorFeatures5_UNK26 0x04000000
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||||
#define chipMinorFeatures5_UNK27 0x08000000
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||||
#define chipMinorFeatures5_UNK28 0x10000000
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#define chipMinorFeatures5_UNK29 0x20000000
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#define chipMinorFeatures5_UNK30 0x40000000
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||||
#define chipMinorFeatures5_UNK31 0x80000000
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#endif /* COMMON_XML */
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@ -668,7 +668,6 @@ static struct platform_driver etnaviv_platform_driver = {
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.probe = etnaviv_pdev_probe,
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.remove = etnaviv_pdev_remove,
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.driver = {
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.owner = THIS_MODULE,
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.name = "etnaviv",
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.of_match_table = dt_match,
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},
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@ -85,7 +85,7 @@ struct drm_gem_object *etnaviv_gem_prime_import_sg_table(struct drm_device *dev,
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struct dma_buf_attachment *attach, struct sg_table *sg);
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int etnaviv_gem_prime_pin(struct drm_gem_object *obj);
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void etnaviv_gem_prime_unpin(struct drm_gem_object *obj);
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void *etnaviv_gem_vaddr(struct drm_gem_object *obj);
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void *etnaviv_gem_vmap(struct drm_gem_object *obj);
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int etnaviv_gem_cpu_prep(struct drm_gem_object *obj, u32 op,
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struct timespec *timeout);
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int etnaviv_gem_cpu_fini(struct drm_gem_object *obj);
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@ -201,7 +201,9 @@ void etnaviv_core_dump(struct etnaviv_gpu *gpu)
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obj = vram->object;
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mutex_lock(&obj->lock);
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pages = etnaviv_gem_get_pages(obj);
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mutex_unlock(&obj->lock);
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if (pages) {
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int j;
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@ -213,8 +215,8 @@ void etnaviv_core_dump(struct etnaviv_gpu *gpu)
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iter.hdr->iova = cpu_to_le64(vram->iova);
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vaddr = etnaviv_gem_vaddr(&obj->base);
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if (vaddr && !IS_ERR(vaddr))
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vaddr = etnaviv_gem_vmap(&obj->base);
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if (vaddr)
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memcpy(iter.data, vaddr, obj->base.size);
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etnaviv_core_dump_header(&iter, ETDUMP_BUF_BO, iter.data +
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@ -353,25 +353,39 @@ void etnaviv_gem_put_iova(struct etnaviv_gpu *gpu, struct drm_gem_object *obj)
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drm_gem_object_unreference_unlocked(obj);
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}
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void *etnaviv_gem_vaddr(struct drm_gem_object *obj)
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void *etnaviv_gem_vmap(struct drm_gem_object *obj)
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{
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struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj);
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if (etnaviv_obj->vaddr)
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return etnaviv_obj->vaddr;
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mutex_lock(&etnaviv_obj->lock);
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if (!etnaviv_obj->vaddr) {
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struct page **pages = etnaviv_gem_get_pages(etnaviv_obj);
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if (IS_ERR(pages))
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return ERR_CAST(pages);
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etnaviv_obj->vaddr = vmap(pages, obj->size >> PAGE_SHIFT,
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VM_MAP, pgprot_writecombine(PAGE_KERNEL));
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}
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/*
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* Need to check again, as we might have raced with another thread
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* while waiting for the mutex.
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*/
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if (!etnaviv_obj->vaddr)
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etnaviv_obj->vaddr = etnaviv_obj->ops->vmap(etnaviv_obj);
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mutex_unlock(&etnaviv_obj->lock);
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return etnaviv_obj->vaddr;
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}
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static void *etnaviv_gem_vmap_impl(struct etnaviv_gem_object *obj)
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{
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struct page **pages;
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lockdep_assert_held(&obj->lock);
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pages = etnaviv_gem_get_pages(obj);
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if (IS_ERR(pages))
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return NULL;
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return vmap(pages, obj->base.size >> PAGE_SHIFT,
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VM_MAP, pgprot_writecombine(PAGE_KERNEL));
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}
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static inline enum dma_data_direction etnaviv_op_to_dma_dir(u32 op)
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{
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if (op & ETNA_PREP_READ)
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@ -522,6 +536,7 @@ static void etnaviv_gem_shmem_release(struct etnaviv_gem_object *etnaviv_obj)
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static const struct etnaviv_gem_ops etnaviv_gem_shmem_ops = {
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.get_pages = etnaviv_gem_shmem_get_pages,
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.release = etnaviv_gem_shmem_release,
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.vmap = etnaviv_gem_vmap_impl,
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};
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void etnaviv_gem_free_object(struct drm_gem_object *obj)
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@ -866,6 +881,7 @@ static void etnaviv_gem_userptr_release(struct etnaviv_gem_object *etnaviv_obj)
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static const struct etnaviv_gem_ops etnaviv_gem_userptr_ops = {
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.get_pages = etnaviv_gem_userptr_get_pages,
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.release = etnaviv_gem_userptr_release,
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.vmap = etnaviv_gem_vmap_impl,
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};
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|
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int etnaviv_gem_new_userptr(struct drm_device *dev, struct drm_file *file,
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@ -78,6 +78,7 @@ struct etnaviv_gem_object *to_etnaviv_bo(struct drm_gem_object *obj)
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struct etnaviv_gem_ops {
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int (*get_pages)(struct etnaviv_gem_object *);
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void (*release)(struct etnaviv_gem_object *);
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void *(*vmap)(struct etnaviv_gem_object *);
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};
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||||
|
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static inline bool is_active(struct etnaviv_gem_object *etnaviv_obj)
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|
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@ -31,7 +31,7 @@ struct sg_table *etnaviv_gem_prime_get_sg_table(struct drm_gem_object *obj)
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|
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void *etnaviv_gem_prime_vmap(struct drm_gem_object *obj)
|
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{
|
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return etnaviv_gem_vaddr(obj);
|
||||
return etnaviv_gem_vmap(obj);
|
||||
}
|
||||
|
||||
void etnaviv_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
|
||||
@ -77,9 +77,17 @@ static void etnaviv_gem_prime_release(struct etnaviv_gem_object *etnaviv_obj)
|
||||
drm_prime_gem_destroy(&etnaviv_obj->base, etnaviv_obj->sgt);
|
||||
}
|
||||
|
||||
static void *etnaviv_gem_prime_vmap_impl(struct etnaviv_gem_object *etnaviv_obj)
|
||||
{
|
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lockdep_assert_held(&etnaviv_obj->lock);
|
||||
|
||||
return dma_buf_vmap(etnaviv_obj->base.import_attach->dmabuf);
|
||||
}
|
||||
|
||||
static const struct etnaviv_gem_ops etnaviv_gem_prime_ops = {
|
||||
/* .get_pages should never be called */
|
||||
.release = etnaviv_gem_prime_release,
|
||||
.vmap = etnaviv_gem_prime_vmap_impl,
|
||||
};
|
||||
|
||||
struct drm_gem_object *etnaviv_gem_prime_import_sg_table(struct drm_device *dev,
|
||||
|
||||
@ -72,6 +72,14 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
|
||||
*value = gpu->identity.minor_features3;
|
||||
break;
|
||||
|
||||
case ETNAVIV_PARAM_GPU_FEATURES_5:
|
||||
*value = gpu->identity.minor_features4;
|
||||
break;
|
||||
|
||||
case ETNAVIV_PARAM_GPU_FEATURES_6:
|
||||
*value = gpu->identity.minor_features5;
|
||||
break;
|
||||
|
||||
case ETNAVIV_PARAM_GPU_STREAM_COUNT:
|
||||
*value = gpu->identity.stream_count;
|
||||
break;
|
||||
@ -112,6 +120,10 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
|
||||
*value = gpu->identity.num_constants;
|
||||
break;
|
||||
|
||||
case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
|
||||
*value = gpu->identity.varyings_count;
|
||||
break;
|
||||
|
||||
default:
|
||||
DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
|
||||
return -EINVAL;
|
||||
@ -120,46 +132,56 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#define etnaviv_is_model_rev(gpu, mod, rev) \
|
||||
((gpu)->identity.model == chipModel_##mod && \
|
||||
(gpu)->identity.revision == rev)
|
||||
#define etnaviv_field(val, field) \
|
||||
(((val) & field##__MASK) >> field##__SHIFT)
|
||||
|
||||
static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
|
||||
{
|
||||
if (gpu->identity.minor_features0 &
|
||||
chipMinorFeatures0_MORE_MINOR_FEATURES) {
|
||||
u32 specs[2];
|
||||
u32 specs[4];
|
||||
unsigned int streams;
|
||||
|
||||
specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
|
||||
specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
|
||||
specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
|
||||
specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
|
||||
|
||||
gpu->identity.stream_count =
|
||||
(specs[0] & VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK)
|
||||
>> VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT;
|
||||
gpu->identity.register_max =
|
||||
(specs[0] & VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK)
|
||||
>> VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT;
|
||||
gpu->identity.thread_count =
|
||||
(specs[0] & VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK)
|
||||
>> VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT;
|
||||
gpu->identity.vertex_cache_size =
|
||||
(specs[0] & VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK)
|
||||
>> VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT;
|
||||
gpu->identity.shader_core_count =
|
||||
(specs[0] & VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK)
|
||||
>> VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT;
|
||||
gpu->identity.pixel_pipes =
|
||||
(specs[0] & VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK)
|
||||
>> VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT;
|
||||
gpu->identity.stream_count = etnaviv_field(specs[0],
|
||||
VIVS_HI_CHIP_SPECS_STREAM_COUNT);
|
||||
gpu->identity.register_max = etnaviv_field(specs[0],
|
||||
VIVS_HI_CHIP_SPECS_REGISTER_MAX);
|
||||
gpu->identity.thread_count = etnaviv_field(specs[0],
|
||||
VIVS_HI_CHIP_SPECS_THREAD_COUNT);
|
||||
gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
|
||||
VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
|
||||
gpu->identity.shader_core_count = etnaviv_field(specs[0],
|
||||
VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
|
||||
gpu->identity.pixel_pipes = etnaviv_field(specs[0],
|
||||
VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
|
||||
gpu->identity.vertex_output_buffer_size =
|
||||
(specs[0] & VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK)
|
||||
>> VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT;
|
||||
etnaviv_field(specs[0],
|
||||
VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
|
||||
|
||||
gpu->identity.buffer_size =
|
||||
(specs[1] & VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK)
|
||||
>> VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT;
|
||||
gpu->identity.instruction_count =
|
||||
(specs[1] & VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK)
|
||||
>> VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT;
|
||||
gpu->identity.num_constants =
|
||||
(specs[1] & VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK)
|
||||
>> VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT;
|
||||
gpu->identity.buffer_size = etnaviv_field(specs[1],
|
||||
VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
|
||||
gpu->identity.instruction_count = etnaviv_field(specs[1],
|
||||
VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
|
||||
gpu->identity.num_constants = etnaviv_field(specs[1],
|
||||
VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
|
||||
|
||||
gpu->identity.varyings_count = etnaviv_field(specs[2],
|
||||
VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
|
||||
|
||||
/* This overrides the value from older register if non-zero */
|
||||
streams = etnaviv_field(specs[3],
|
||||
VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
|
||||
if (streams)
|
||||
gpu->identity.stream_count = streams;
|
||||
}
|
||||
|
||||
/* Fill in the stream count if not specified */
|
||||
@ -173,7 +195,7 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
|
||||
/* Convert the register max value */
|
||||
if (gpu->identity.register_max)
|
||||
gpu->identity.register_max = 1 << gpu->identity.register_max;
|
||||
else if (gpu->identity.model == 0x0400)
|
||||
else if (gpu->identity.model == chipModel_GC400)
|
||||
gpu->identity.register_max = 32;
|
||||
else
|
||||
gpu->identity.register_max = 64;
|
||||
@ -181,10 +203,10 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
|
||||
/* Convert thread count */
|
||||
if (gpu->identity.thread_count)
|
||||
gpu->identity.thread_count = 1 << gpu->identity.thread_count;
|
||||
else if (gpu->identity.model == 0x0400)
|
||||
else if (gpu->identity.model == chipModel_GC400)
|
||||
gpu->identity.thread_count = 64;
|
||||
else if (gpu->identity.model == 0x0500 ||
|
||||
gpu->identity.model == 0x0530)
|
||||
else if (gpu->identity.model == chipModel_GC500 ||
|
||||
gpu->identity.model == chipModel_GC530)
|
||||
gpu->identity.thread_count = 128;
|
||||
else
|
||||
gpu->identity.thread_count = 256;
|
||||
@ -206,7 +228,7 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
|
||||
if (gpu->identity.vertex_output_buffer_size) {
|
||||
gpu->identity.vertex_output_buffer_size =
|
||||
1 << gpu->identity.vertex_output_buffer_size;
|
||||
} else if (gpu->identity.model == 0x0400) {
|
||||
} else if (gpu->identity.model == chipModel_GC400) {
|
||||
if (gpu->identity.revision < 0x4000)
|
||||
gpu->identity.vertex_output_buffer_size = 512;
|
||||
else if (gpu->identity.revision < 0x4200)
|
||||
@ -219,9 +241,8 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
|
||||
|
||||
switch (gpu->identity.instruction_count) {
|
||||
case 0:
|
||||
if ((gpu->identity.model == 0x2000 &&
|
||||
gpu->identity.revision == 0x5108) ||
|
||||
gpu->identity.model == 0x880)
|
||||
if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
|
||||
gpu->identity.model == chipModel_GC880)
|
||||
gpu->identity.instruction_count = 512;
|
||||
else
|
||||
gpu->identity.instruction_count = 256;
|
||||
@ -242,6 +263,30 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
|
||||
|
||||
if (gpu->identity.num_constants == 0)
|
||||
gpu->identity.num_constants = 168;
|
||||
|
||||
if (gpu->identity.varyings_count == 0) {
|
||||
if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
|
||||
gpu->identity.varyings_count = 12;
|
||||
else
|
||||
gpu->identity.varyings_count = 8;
|
||||
}
|
||||
|
||||
/*
|
||||
* For some cores, two varyings are consumed for position, so the
|
||||
* maximum varying count needs to be reduced by one.
|
||||
*/
|
||||
if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
|
||||
etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
|
||||
etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
|
||||
etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
|
||||
etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
|
||||
etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
|
||||
etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
|
||||
etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
|
||||
etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
|
||||
etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
|
||||
etnaviv_is_model_rev(gpu, GC880, 0x5106))
|
||||
gpu->identity.varyings_count -= 1;
|
||||
}
|
||||
|
||||
static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
|
||||
@ -251,12 +296,10 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
|
||||
chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
|
||||
|
||||
/* Special case for older graphic cores. */
|
||||
if (((chipIdentity & VIVS_HI_CHIP_IDENTITY_FAMILY__MASK)
|
||||
>> VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT) == 0x01) {
|
||||
gpu->identity.model = 0x500; /* gc500 */
|
||||
gpu->identity.revision =
|
||||
(chipIdentity & VIVS_HI_CHIP_IDENTITY_REVISION__MASK)
|
||||
>> VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT;
|
||||
if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
|
||||
gpu->identity.model = chipModel_GC500;
|
||||
gpu->identity.revision = etnaviv_field(chipIdentity,
|
||||
VIVS_HI_CHIP_IDENTITY_REVISION);
|
||||
} else {
|
||||
|
||||
gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
|
||||
@ -269,13 +312,12 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
|
||||
* same. Only for GC400 family.
|
||||
*/
|
||||
if ((gpu->identity.model & 0xff00) == 0x0400 &&
|
||||
gpu->identity.model != 0x0420) {
|
||||
gpu->identity.model != chipModel_GC420) {
|
||||
gpu->identity.model = gpu->identity.model & 0x0400;
|
||||
}
|
||||
|
||||
/* Another special case */
|
||||
if (gpu->identity.model == 0x300 &&
|
||||
gpu->identity.revision == 0x2201) {
|
||||
if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
|
||||
u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
|
||||
u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
|
||||
|
||||
@ -295,11 +337,13 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
|
||||
gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
|
||||
|
||||
/* Disable fast clear on GC700. */
|
||||
if (gpu->identity.model == 0x700)
|
||||
if (gpu->identity.model == chipModel_GC700)
|
||||
gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
|
||||
|
||||
if ((gpu->identity.model == 0x500 && gpu->identity.revision < 2) ||
|
||||
(gpu->identity.model == 0x300 && gpu->identity.revision < 0x2000)) {
|
||||
if ((gpu->identity.model == chipModel_GC500 &&
|
||||
gpu->identity.revision < 2) ||
|
||||
(gpu->identity.model == chipModel_GC300 &&
|
||||
gpu->identity.revision < 0x2000)) {
|
||||
|
||||
/*
|
||||
* GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
|
||||
@ -309,6 +353,8 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
|
||||
gpu->identity.minor_features1 = 0;
|
||||
gpu->identity.minor_features2 = 0;
|
||||
gpu->identity.minor_features3 = 0;
|
||||
gpu->identity.minor_features4 = 0;
|
||||
gpu->identity.minor_features5 = 0;
|
||||
} else
|
||||
gpu->identity.minor_features0 =
|
||||
gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
|
||||
@ -321,6 +367,10 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
|
||||
gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
|
||||
gpu->identity.minor_features3 =
|
||||
gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
|
||||
gpu->identity.minor_features4 =
|
||||
gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
|
||||
gpu->identity.minor_features5 =
|
||||
gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
|
||||
}
|
||||
|
||||
/* GC600 idle register reports zero bits where modules aren't present */
|
||||
@ -441,10 +491,9 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
|
||||
{
|
||||
u16 prefetch;
|
||||
|
||||
if (gpu->identity.model == chipModel_GC320 &&
|
||||
gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400 &&
|
||||
(gpu->identity.revision == 0x5007 ||
|
||||
gpu->identity.revision == 0x5220)) {
|
||||
if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
|
||||
etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
|
||||
gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
|
||||
u32 mc_memory_debug;
|
||||
|
||||
mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
|
||||
@ -466,7 +515,7 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
|
||||
VIVS_HI_AXI_CONFIG_ARCACHE(2));
|
||||
|
||||
/* GC2000 rev 5108 needs a special bus config */
|
||||
if (gpu->identity.model == 0x2000 && gpu->identity.revision == 0x5108) {
|
||||
if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
|
||||
u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
|
||||
bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
|
||||
VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
|
||||
@ -511,8 +560,16 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
|
||||
|
||||
if (gpu->identity.model == 0) {
|
||||
dev_err(gpu->dev, "Unknown GPU model\n");
|
||||
pm_runtime_put_autosuspend(gpu->dev);
|
||||
return -ENXIO;
|
||||
ret = -ENXIO;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* Exclude VG cores with FE2.0 */
|
||||
if (gpu->identity.features & chipFeatures_PIPE_VG &&
|
||||
gpu->identity.features & chipFeatures_FE20) {
|
||||
dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
|
||||
ret = -ENXIO;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
ret = etnaviv_hw_reset(gpu);
|
||||
@ -539,10 +596,9 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* TODO: we will leak here memory - fix it! */
|
||||
|
||||
gpu->mmu = etnaviv_iommu_new(gpu, iommu, version);
|
||||
if (!gpu->mmu) {
|
||||
iommu_domain_free(iommu);
|
||||
ret = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
@ -552,7 +608,7 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
|
||||
if (!gpu->buffer) {
|
||||
ret = -ENOMEM;
|
||||
dev_err(gpu->dev, "could not create command buffer\n");
|
||||
goto fail;
|
||||
goto destroy_iommu;
|
||||
}
|
||||
if (gpu->buffer->paddr - gpu->memory_base > 0x80000000) {
|
||||
ret = -EINVAL;
|
||||
@ -582,6 +638,9 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
|
||||
free_buffer:
|
||||
etnaviv_gpu_cmdbuf_free(gpu->buffer);
|
||||
gpu->buffer = NULL;
|
||||
destroy_iommu:
|
||||
etnaviv_iommu_destroy(gpu->mmu);
|
||||
gpu->mmu = NULL;
|
||||
fail:
|
||||
pm_runtime_mark_last_busy(gpu->dev);
|
||||
pm_runtime_put_autosuspend(gpu->dev);
|
||||
@ -642,6 +701,10 @@ int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
|
||||
gpu->identity.minor_features2);
|
||||
seq_printf(m, "\t minor_features3: 0x%08x\n",
|
||||
gpu->identity.minor_features3);
|
||||
seq_printf(m, "\t minor_features4: 0x%08x\n",
|
||||
gpu->identity.minor_features4);
|
||||
seq_printf(m, "\t minor_features5: 0x%08x\n",
|
||||
gpu->identity.minor_features5);
|
||||
|
||||
seq_puts(m, "\tspecs\n");
|
||||
seq_printf(m, "\t stream_count: %d\n",
|
||||
@ -664,6 +727,8 @@ int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
|
||||
gpu->identity.instruction_count);
|
||||
seq_printf(m, "\t num_constants: %d\n",
|
||||
gpu->identity.num_constants);
|
||||
seq_printf(m, "\t varyings_count: %d\n",
|
||||
gpu->identity.varyings_count);
|
||||
|
||||
seq_printf(m, "\taxi: 0x%08x\n", axi);
|
||||
seq_printf(m, "\tidle: 0x%08x\n", idle);
|
||||
|
||||
@ -46,6 +46,12 @@ struct etnaviv_chip_identity {
|
||||
/* Supported minor feature 3 fields. */
|
||||
u32 minor_features3;
|
||||
|
||||
/* Supported minor feature 4 fields. */
|
||||
u32 minor_features4;
|
||||
|
||||
/* Supported minor feature 5 fields. */
|
||||
u32 minor_features5;
|
||||
|
||||
/* Number of streams supported. */
|
||||
u32 stream_count;
|
||||
|
||||
@ -75,6 +81,9 @@ struct etnaviv_chip_identity {
|
||||
|
||||
/* Buffer size */
|
||||
u32 buffer_size;
|
||||
|
||||
/* Number of varyings */
|
||||
u8 varyings_count;
|
||||
};
|
||||
|
||||
struct etnaviv_event {
|
||||
|
||||
@ -8,8 +8,8 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
|
||||
git clone git://0x04.net/rules-ng-ng
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- state_hi.xml ( 23420 bytes, from 2015-03-25 11:47:21)
|
||||
- common.xml ( 18437 bytes, from 2015-03-25 11:27:41)
|
||||
- state_hi.xml ( 24309 bytes, from 2015-12-12 09:02:53)
|
||||
- common.xml ( 18437 bytes, from 2015-12-12 09:02:53)
|
||||
|
||||
Copyright (C) 2015
|
||||
*/
|
||||
@ -182,8 +182,25 @@ Copyright (C) 2015
|
||||
|
||||
#define VIVS_HI_CHIP_MINOR_FEATURE_3 0x00000088
|
||||
|
||||
#define VIVS_HI_CHIP_SPECS_3 0x0000008c
|
||||
#define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK 0x000001f0
|
||||
#define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT 4
|
||||
#define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK)
|
||||
#define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK 0x00000007
|
||||
#define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT 0
|
||||
#define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK)
|
||||
|
||||
#define VIVS_HI_CHIP_MINOR_FEATURE_4 0x00000094
|
||||
|
||||
#define VIVS_HI_CHIP_SPECS_4 0x0000009c
|
||||
#define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK 0x0001f000
|
||||
#define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT 12
|
||||
#define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK)
|
||||
|
||||
#define VIVS_HI_CHIP_MINOR_FEATURE_5 0x000000a0
|
||||
|
||||
#define VIVS_HI_CHIP_PRODUCT_ID 0x000000a8
|
||||
|
||||
#define VIVS_PM 0x00000000
|
||||
|
||||
#define VIVS_PM_POWER_CONTROLS 0x00000100
|
||||
@ -206,6 +223,11 @@ Copyright (C) 2015
|
||||
#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE 0x00000001
|
||||
#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_DE 0x00000002
|
||||
#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PE 0x00000004
|
||||
#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SH 0x00000008
|
||||
#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PA 0x00000010
|
||||
#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SE 0x00000020
|
||||
#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_RA 0x00000040
|
||||
#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX 0x00000080
|
||||
|
||||
#define VIVS_PM_PULSE_EATER 0x0000010c
|
||||
|
||||
|
||||
@ -48,6 +48,8 @@ struct drm_etnaviv_timespec {
|
||||
#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05
|
||||
#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06
|
||||
#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07
|
||||
#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08
|
||||
#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09
|
||||
|
||||
#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10
|
||||
#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11
|
||||
@ -59,6 +61,7 @@ struct drm_etnaviv_timespec {
|
||||
#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17
|
||||
#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
|
||||
#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
|
||||
#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
|
||||
|
||||
#define ETNA_MAX_PIPES 4
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user