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soc: mediatek: pm-domains: Add support for mt8167

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Add the needed board data to support mt8167 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Fabien Parent 2020-12-09 14:32:37 +01:00 committed by Matthias Brugger
parent c70d0f16f3
commit 207f13b419
4 changed files with 100 additions and 0 deletions
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86
drivers/soc/mediatek/mt8167-pm-domains.h Normal file
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@ -0,0 +1,86 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
#define __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
#include "mtk-pm-domains.h"
#include <dt-bindings/power/mt8167-power.h>
#define MT8167_PWR_STATUS_MFG_2D BIT(24)
#define MT8167_PWR_STATUS_MFG_ASYNC BIT(25)
/*
* MT8167 power domain support
*/
static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
[MT8167_POWER_DOMAIN_MM] = {
.sta_mask = PWR_STATUS_DISP,
.ctl_offs = SPM_DIS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
MT8167_TOP_AXI_PROT_EN_MCU_MM),
},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8167_POWER_DOMAIN_VDEC] = {
.sta_mask = PWR_STATUS_VDEC,
.ctl_offs = SPM_VDE_PWR_CON,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8167_POWER_DOMAIN_ISP] = {
.sta_mask = PWR_STATUS_ISP,
.ctl_offs = SPM_ISP_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8167_POWER_DOMAIN_MFG_ASYNC] = {
.sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,
.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
.bp_infracfg = {
BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
MT8167_TOP_AXI_PROT_EN_MFG_EMI),
},
},
[MT8167_POWER_DOMAIN_MFG_2D] = {
.sta_mask = MT8167_PWR_STATUS_MFG_2D,
.ctl_offs = SPM_MFG_2D_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
},
[MT8167_POWER_DOMAIN_MFG] = {
.sta_mask = PWR_STATUS_MFG,
.ctl_offs = SPM_MFG_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
},
[MT8167_POWER_DOMAIN_CONN] = {
.sta_mask = PWR_STATUS_CONN,
.ctl_offs = SPM_CONN_PWR_CON,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = 0,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
.bp_infracfg = {
BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
MT8167_TOP_AXI_PROT_EN_CONN_MCU |
MT8167_TOP_AXI_PROT_EN_MCU_CONN),
},
},
};
static const struct scpsys_soc_data mt8167_scpsys_data = {
.domains_data = scpsys_domain_data_mt8167,
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167),
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
};
#endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */

5
drivers/soc/mediatek/mtk-pm-domains.c
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@ -15,6 +15,7 @@
#include <linux/regmap.h> #include <linux/regmap.h>
#include <linux/soc/mediatek/infracfg.h> #include <linux/soc/mediatek/infracfg.h>
#include "mt8167-pm-domains.h"
#include "mt8173-pm-domains.h" #include "mt8173-pm-domains.h"
#include "mt8183-pm-domains.h" #include "mt8183-pm-domains.h"
#include "mt8192-pm-domains.h" #include "mt8192-pm-domains.h"
@ -514,6 +515,10 @@ static void scpsys_domain_cleanup(struct scpsys *scpsys)
} }
static const struct of_device_id scpsys_of_match[] = { static const struct of_device_id scpsys_of_match[] = {
{
.compatible = "mediatek,mt8167-power-controller",
.data = &mt8167_scpsys_data,
},
{ {
.compatible = "mediatek,mt8173-power-controller", .compatible = "mediatek,mt8173-power-controller",
.data = &mt8173_scpsys_data, .data = &mt8173_scpsys_data,

1
drivers/soc/mediatek/mtk-pm-domains.h
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@ -14,6 +14,7 @@
#define SPM_VEN_PWR_CON 0x0230 #define SPM_VEN_PWR_CON 0x0230
#define SPM_ISP_PWR_CON 0x0238 #define SPM_ISP_PWR_CON 0x0238
#define SPM_DIS_PWR_CON 0x023c #define SPM_DIS_PWR_CON 0x023c
#define SPM_CONN_PWR_CON 0x0280
#define SPM_VEN2_PWR_CON 0x0298 #define SPM_VEN2_PWR_CON 0x0298
#define SPM_AUDIO_PWR_CON 0x029c #define SPM_AUDIO_PWR_CON 0x029c
#define SPM_MFG_2D_PWR_CON 0x02c0 #define SPM_MFG_2D_PWR_CON 0x02c0

8
include/linux/soc/mediatek/infracfg.h
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@ -123,6 +123,14 @@
#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) #define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) #define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
#define MT8167_TOP_AXI_PROT_EN_MM_EMI BIT(1)
#define MT8167_TOP_AXI_PROT_EN_MCU_MFG BIT(2)
#define MT8167_TOP_AXI_PROT_EN_CONN_EMI BIT(4)
#define MT8167_TOP_AXI_PROT_EN_MFG_EMI BIT(5)
#define MT8167_TOP_AXI_PROT_EN_CONN_MCU BIT(8)
#define MT8167_TOP_AXI_PROT_EN_MCU_CONN BIT(9)
#define MT8167_TOP_AXI_PROT_EN_MCU_MM BIT(11)
#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) #define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) #define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) #define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)