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ixgbe: Add definitions for x550em_a 10G MAC
Add definitions for a x550em_a 10G MAC device with a native SFP interface. Signed-off-by: Mark Rustad <mark.d.rustad@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -81,16 +81,18 @@
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#define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC
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#define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD
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#define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE
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#define IXGBE_DEV_ID_X550EM_A_SFP_N 0x15C4
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/* VF Device IDs */
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#define IXGBE_DEV_ID_X550_VF_HV 0x1564
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#define IXGBE_DEV_ID_X550_VF 0x1565
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#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
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#define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
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/* VF Device IDs */
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#define IXGBE_DEV_ID_82599_VF 0x10ED
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#define IXGBE_DEV_ID_X540_VF 0x1515
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#define IXGBE_DEV_ID_X550_VF 0x1565
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#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
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#define IXGBE_DEV_ID_X550EM_A_VF 0x15C5
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#define IXGBE_CAT(r, m) IXGBE_##r##_##m
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@ -129,7 +131,7 @@
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#define IXGBE_FLA_X540 IXGBE_FLA_8259X
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#define IXGBE_FLA_X550 IXGBE_FLA_8259X
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#define IXGBE_FLA_X550EM_x IXGBE_FLA_8259X
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#define IXGBE_FLA_X550EM_a 0x15F6C
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#define IXGBE_FLA_X550EM_a 0x15F68
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#define IXGBE_FLA(_hw) IXGBE_BY_MAC((_hw), FLA)
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#define IXGBE_EEMNGCTL 0x10110
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#define IXGBE_EEMNGDATA 0x10114
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@ -369,6 +371,8 @@ struct ixgbe_thermal_sensor_data {
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#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4))
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#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
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#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
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#define IXGBE_WQBR_RX(_i) (0x2FB0 + ((_i) * 4)) /* 4 total */
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#define IXGBE_WQBR_TX(_i) (0x8130 + ((_i) * 4)) /* 4 total */
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#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
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#define IXGBE_RXFECCERR0 0x051B8
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#define IXGBE_LLITHRESH 0x0EC90
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@ -440,6 +444,8 @@ struct ixgbe_thermal_sensor_data {
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#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
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#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
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#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
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#define IXGBE_DMATXCTL_MDP_EN 0x20 /* Bit 5 */
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#define IXGBE_DMATXCTL_MBINTEN 0x40 /* Bit 6 */
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#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
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#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
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@ -548,7 +554,6 @@ struct ixgbe_thermal_sensor_data {
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#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
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#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
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/* Security Control Registers */
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#define IXGBE_SECTXCTRL 0x08800
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#define IXGBE_SECTXSTAT 0x08804
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@ -1197,6 +1202,8 @@ struct ixgbe_thermal_sensor_data {
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#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */
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#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */
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#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */
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#define IXGBE_RDRXCTL_MBINTEN 0x10000000
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#define IXGBE_RDRXCTL_MDP_EN 0x20000000
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/* RQTC Bit Masks and Shifts */
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#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
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@ -1951,7 +1958,9 @@ enum {
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#define IXGBE_GSSR_PHY1_SM 0x0004
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#define IXGBE_GSSR_MAC_CSR_SM 0x0008
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#define IXGBE_GSSR_FLASH_SM 0x0010
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#define IXGBE_GSSR_NVM_UPDATE_SM 0x0200
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#define IXGBE_GSSR_SW_MNG_SM 0x0400
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#define IXGBE_GSSR_TOKEN_SM 0x40000000 /* SW bit for shared access */
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#define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys & I2Cs */
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#define IXGBE_GSSR_I2C_MASK 0x1800
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#define IXGBE_GSSR_NVM_PHY_MASK 0xF
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@ -2524,6 +2533,10 @@ enum ixgbe_fdir_pballoc_type {
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#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
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#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
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#define IXGBE_FDIRCTRL_FLEX_SHIFT 16
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#define IXGBE_FDIRCTRL_DROP_NO_MATCH 0x00008000
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#define IXGBE_FDIRCTRL_FILTERMODE_SHIFT 21
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#define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN 0x0001 /* bit 23:21, 001b */
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#define IXGBE_FDIRCTRL_FILTERMODE_CLOUD 0x0002 /* bit 23:21, 010b */
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#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
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#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
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#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
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@ -2982,6 +2995,7 @@ enum ixgbe_mac_type {
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ixgbe_mac_X540,
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ixgbe_mac_X550,
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ixgbe_mac_X550EM_x,
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ixgbe_mac_x550em_a,
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ixgbe_num_macs
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};
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