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drm/amdgpu: port SRIOV VF missed changes
port SRIOV VF missed changes from gfx_v9_0 to gfx_v9_4_3. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Zhigang Luo <Zhigang.Luo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1762,6 +1762,8 @@ static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id)
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((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
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((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
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mutex_lock(&adev->srbm_mutex);
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if (amdgpu_sriov_vf(adev) && adev->in_suspend)
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amdgpu_ring_clear_ring(ring);
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soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
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gfx_v9_4_3_xcc_mqd_init(ring, xcc_id);
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gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id);
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@ -1960,6 +1962,16 @@ static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id)
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if (amdgpu_gfx_disable_kcq(adev, xcc_id))
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DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id);
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if (amdgpu_sriov_vf(adev)) {
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/* must disable polling for SRIOV when hw finished, otherwise
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* CPC engine may still keep fetching WB address which is already
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* invalid after sw finished and trigger DMAR reading error in
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* hypervisor side.
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*/
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WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);
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return;
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}
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/* Use deinitialize sequence from CAIL when unbinding device
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* from driver, otherwise KIQ is hanging when binding back
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*/
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@ -1984,7 +1996,8 @@ static int gfx_v9_4_3_hw_init(void *handle)
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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gfx_v9_4_3_init_golden_registers(adev);
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if (!amdgpu_sriov_vf(adev))
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gfx_v9_4_3_init_golden_registers(adev);
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gfx_v9_4_3_constants_init(adev);
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