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ARM: arm-soc fixes for 3.8
This is a batch of fixes for arm-soc platforms, most of it is for OMAP
but there are others too (i.MX, Tegra, ep93xx). Fixes warnings, some
broken platforms and drivers, etc. A bit all over the map really.
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Merge tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"This is a batch of fixes for arm-soc platforms, most of it is for OMAP
but there are others too (i.MX, Tegra, ep93xx). Fixes warnings, some
broken platforms and drivers, etc. A bit all over the map really."
There was some concern about commit 68136b10 ("RM: sunxi: Change device
tree naming scheme for sunxi"), but Tony says:
"Looks like that's trivial to fix as needed, no need to rebuild the
branch to fix that AFAIK.
The fix can be done once Olof is available online again.
Linus, I suggest that you go ahead and pull this if there are no other
issues with this branch."
* tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (32 commits)
ARM: sunxi: Change device tree naming scheme for sunxi
ARM: ux500: fix missing include
ARM: u300: delete custom pin hog code
ARM: davinci: fix build break due to missing include
ARM: exynos: Fix warning due to missing 'inline' in stub
ARM: imx: Move platform-mx2-emma to arch/arm/mach-imx/devices
ARM i.MX51 clock: Fix regression since enabling MIPI/HSP clocks
ARM: dts: mx27: Fix the AIPI bus for FEC
ARM: OMAP2+: common: remove use of vram
ARM: OMAP3/4: cpuidle: fix sparse and checkpatch warnings
ARM: OMAP4: clock data: DPLLs are missing bypass clocks in their parent lists
ARM: OMAP4: clock data: div_iva_hs_clk is a power-of-two divider
ARM: OMAP4: Fix EMU clock domain always on
ARM: OMAP4460: Workaround ABE DPLL failing to turn-on
ARM: OMAP4: Enhance support for DPLLs with 4X multiplier
ARM: OMAP4: Add function table for non-M4X dplls
ARM: OMAP4: Update timer clock aliases
ARM: OMAP: Move plat/omap-serial.h to include/linux/platform_data/serial-omap.h
ARM: dts: Add build target for omap4-panda-a4
ARM: dts: OMAP2420: Correct H4 board memory size
...
This commit is contained in:
Linus Torvalds
commit
1ffab3d413
@ -107,6 +107,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
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omap3-evm.dtb \
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omap3-tobi.dtb \
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omap4-panda.dtb \
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omap4-panda-a4.dtb \
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omap4-panda-es.dtb \
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omap4-var-som.dtb \
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omap4-sdp.dtb \
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@ -131,8 +132,8 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
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spear320-evb.dtb \
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spear320-hmi.dtb
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dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun4i-cubieboard.dtb \
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sun5i-olinuxino.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \
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sun5i-a13-olinuxino.dtb
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dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
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tegra20-medcom-wide.dtb \
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tegra20-paz00.dtb \
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@ -21,17 +21,17 @@
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};
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soc {
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aipi@10000000 { /* aipi */
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aipi@10000000 { /* aipi1 */
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uart1: serial@1000a000 {
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fsl,uart-has-rtscts;
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status = "okay";
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};
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};
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fec@1002b000 {
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aipi@10020000 { /* aipi2 */
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ethernet@1002b000 {
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status = "okay";
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};
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};
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};
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};
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@ -21,8 +21,7 @@
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};
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soc {
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aipi@10000000 { /* aipi */
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aipi@10000000 { /* aipi1 */
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serial@1000a000 {
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fsl,uart-has-rtscts;
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status = "okay";
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@ -38,10 +37,6 @@
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status = "okay";
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};
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ethernet@1002b000 {
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status = "okay";
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};
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i2c@1001d000 {
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clock-frequency = <400000>;
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status = "okay";
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@ -60,6 +55,12 @@
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};
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};
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};
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aipi@10020000 { /* aipi2 */
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ethernet@1002b000 {
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status = "okay";
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};
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};
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};
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nor_flash@c0000000 {
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@ -55,7 +55,7 @@
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compatible = "fsl,aipi-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10000000 0x10000000>;
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reg = <0x10000000 0x20000>;
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ranges;
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wdog: wdog@10002000 {
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@ -211,6 +211,15 @@
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status = "disabled";
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};
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};
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aipi@10020000 { /* AIPI2 */
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compatible = "fsl,aipi-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10020000 0x20000>;
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ranges;
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fec: ethernet@1002b000 {
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compatible = "fsl,imx27-fec";
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reg = <0x1002b000 0x4000>;
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@ -15,6 +15,6 @@
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memory {
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device_type = "memory";
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reg = <0x80000000 0x84000000>; /* 64 MB */
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reg = <0x80000000 0x4000000>; /* 64 MB */
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};
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};
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@ -11,11 +11,11 @@
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*/
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/dts-v1/;
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/include/ "sun4i.dtsi"
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/include/ "sun4i-a10.dtsi"
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/ {
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model = "Cubietech Cubieboard";
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compatible = "cubietech,cubieboard", "allwinner,sun4i";
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compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10";
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aliases {
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serial0 = &uart0;
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@ -12,11 +12,11 @@
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*/
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/dts-v1/;
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/include/ "sun5i.dtsi"
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/include/ "sun5i-a13.dtsi"
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/ {
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model = "Olimex A13-Olinuxino";
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compatible = "olimex,a13-olinuxino", "allwinner,sun5i";
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compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
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chosen {
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bootargs = "earlyprintk console=ttyS0,115200";
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@ -41,6 +41,7 @@
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#include <mach/cp_intc.h>
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#include <mach/da8xx.h>
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#include <mach/mux.h>
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#include <mach/sram.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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@ -47,13 +47,9 @@ static void __raw_writel(unsigned int value, unsigned int ptr)
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static inline void putc(int c)
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{
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int i;
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for (i = 0; i < 1000; i++) {
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/* Transmit fifo not full? */
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if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF))
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break;
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}
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/* Transmit fifo not full? */
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while (__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF)
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;
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__raw_writeb(c, PHYS_UART_DATA);
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}
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@ -25,7 +25,7 @@ void exynos_init_late(void);
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#ifdef CONFIG_PM_GENERIC_DOMAINS
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int exynos_pm_late_initcall(void);
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#else
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static int exynos_pm_late_initcall(void) { return 0; }
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static inline int exynos_pm_late_initcall(void) { return 0; }
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#endif
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#ifdef CONFIG_ARCH_EXYNOS4
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@ -319,6 +319,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
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unsigned long rate_ckih1, unsigned long rate_ckih2)
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{
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int i;
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u32 val;
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struct device_node *np;
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clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
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@ -390,6 +391,21 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
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imx_print_silicon_rev("i.MX51", mx51_revision());
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clk_disable_unprepare(clk[iim_gate]);
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/*
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* Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
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* longer supported. Set to one for better power saving.
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*
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* The effect of not setting these bits is that MIPI clocks can't be
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* enabled without the IPU clock being enabled aswell.
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*/
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val = readl(MXC_CCM_CCDR);
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val |= 1 << 18;
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writel(val, MXC_CCM_CCDR);
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val = readl(MXC_CCM_CLPCR);
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val |= 1 << 23;
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writel(val, MXC_CCM_CLPCR);
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return 0;
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}
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@ -6,8 +6,8 @@
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* the terms of the GNU General Public License version 2 as published by the
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* Free Software Foundation.
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*/
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#include <mach/hardware.h>
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#include <mach/devices-common.h>
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#include "../hardware.h"
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#include "devices-common.h"
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#define imx_mx2_emmaprp_data_entry_single(soc) \
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{ \
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@ -26,6 +26,8 @@ config SOC_HAS_OMAP2_SDRC
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config SOC_HAS_REALTIME_COUNTER
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bool "Real time free running counter"
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depends on SOC_OMAP5
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default y
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config ARCH_OMAP2
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bool "TI OMAP2"
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@ -79,7 +81,6 @@ config SOC_OMAP5
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select ARM_GIC
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select CPU_V7
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select HAVE_SMP
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select SOC_HAS_REALTIME_COUNTER
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select COMMON_CLK
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comment "OMAP Core Type"
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@ -157,6 +157,7 @@ static struct omap_dss_device sdp3430_lcd_device = {
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static struct tfp410_platform_data dvi_panel = {
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.power_down_gpio = -1,
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.i2c_bus_num = -1,
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};
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static struct omap_dss_device sdp3430_dvi_device = {
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@ -208,6 +208,7 @@ static struct omap_dss_device am3517_evm_tv_device = {
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static struct tfp410_platform_data dvi_panel = {
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.power_down_gpio = -1,
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.i2c_bus_num = -1,
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};
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static struct omap_dss_device am3517_evm_dvi_device = {
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@ -241,6 +241,7 @@ static struct omap_dss_device cm_t35_lcd_device = {
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static struct tfp410_platform_data dvi_panel = {
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.power_down_gpio = CM_T35_DVI_EN_GPIO,
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.i2c_bus_num = -1,
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};
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static struct omap_dss_device cm_t35_dvi_device = {
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@ -141,6 +141,7 @@ static struct omap_dss_device devkit8000_lcd_device = {
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static struct tfp410_platform_data dvi_panel = {
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.power_down_gpio = -1,
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.i2c_bus_num = 1,
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};
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static struct omap_dss_device devkit8000_dvi_device = {
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@ -27,14 +27,12 @@
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#include <linux/io.h>
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#include <linux/input/matrix_keypad.h>
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#include <linux/mfd/menelaus.h>
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#include <linux/omap-dma.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <linux/omap-dma.h>
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#include <plat/debug-devices.h>
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#include <video/omapdss.h>
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#include <video/omap-panel-generic-dpi.h>
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@ -42,11 +40,9 @@
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#include "mux.h"
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#include "control.h"
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#include "gpmc.h"
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#include "gpmc-smc91x.h"
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#define H4_FLASH_CS 0
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#define H4_SMC91X_CS 1
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#define H4_ETHR_GPIO_IRQ 92
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#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
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static const uint32_t board_matrix_keys[] = {
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@ -250,71 +246,31 @@ static u32 is_gpmc_muxed(void)
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return 0;
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}
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static inline void __init h4_init_debug(void)
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#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE)
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static struct omap_smc91x_platform_data board_smc91x_data = {
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.cs = 1,
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.gpio_irq = 92,
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.flags = GPMC_TIMINGS_SMC91C96 | IORESOURCE_IRQ_LOWLEVEL,
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};
|
||||
|
||||
static void __init board_smc91x_init(void)
|
||||
{
|
||||
int eth_cs;
|
||||
unsigned long cs_mem_base;
|
||||
unsigned int muxed, rate;
|
||||
struct clk *gpmc_fck;
|
||||
|
||||
eth_cs = H4_SMC91X_CS;
|
||||
|
||||
gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
|
||||
if (IS_ERR(gpmc_fck)) {
|
||||
WARN_ON(1);
|
||||
return;
|
||||
}
|
||||
|
||||
clk_prepare_enable(gpmc_fck);
|
||||
rate = clk_get_rate(gpmc_fck);
|
||||
clk_disable_unprepare(gpmc_fck);
|
||||
clk_put(gpmc_fck);
|
||||
|
||||
if (is_gpmc_muxed())
|
||||
muxed = 0x200;
|
||||
else
|
||||
muxed = 0;
|
||||
board_smc91x_data.flags |= GPMC_MUX_ADD_DATA;
|
||||
|
||||
/* Make sure CS1 timings are correct */
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1,
|
||||
0x00011000 | muxed);
|
||||
|
||||
if (rate >= 160000000) {
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
|
||||
} else if (rate >= 130000000) {
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
|
||||
} else {/* rate = 100000000 */
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
|
||||
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
|
||||
}
|
||||
|
||||
if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
|
||||
printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
udelay(100);
|
||||
|
||||
omap_mux_init_gpio(92, 0);
|
||||
if (debug_card_init(cs_mem_base, H4_ETHR_GPIO_IRQ) < 0)
|
||||
gpmc_cs_free(eth_cs);
|
||||
|
||||
out:
|
||||
clk_disable_unprepare(gpmc_fck);
|
||||
clk_put(gpmc_fck);
|
||||
omap_mux_init_gpio(board_smc91x_data.gpio_irq, OMAP_PIN_INPUT);
|
||||
gpmc_smc91x_init(&board_smc91x_data);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline void board_smc91x_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static void __init h4_init_flash(void)
|
||||
{
|
||||
unsigned long base;
|
||||
@ -371,6 +327,7 @@ static void __init omap_h4_init(void)
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
h4_init_flash();
|
||||
board_smc91x_init();
|
||||
|
||||
omap_display_init(&h4_dss_data);
|
||||
}
|
||||
|
||||
@ -240,6 +240,7 @@ static struct omap_dss_device omap3_evm_tv_device = {
|
||||
|
||||
static struct tfp410_platform_data dvi_panel = {
|
||||
.power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO,
|
||||
.i2c_bus_num = -1,
|
||||
};
|
||||
|
||||
static struct omap_dss_device omap3_evm_dvi_device = {
|
||||
|
||||
@ -118,6 +118,7 @@ static struct omap_dss_device omap3_stalker_tv_device = {
|
||||
|
||||
static struct tfp410_platform_data dvi_panel = {
|
||||
.power_down_gpio = DSS_ENABLE_GPIO,
|
||||
.i2c_bus_num = -1,
|
||||
};
|
||||
|
||||
static struct omap_dss_device omap3_stalker_dvi_device = {
|
||||
|
||||
@ -40,6 +40,14 @@
|
||||
#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0
|
||||
#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1
|
||||
|
||||
/*
|
||||
* OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
|
||||
* "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
|
||||
* must be set to 196.608 MHz" and hence, the DPLL locked frequency is
|
||||
* half of this value.
|
||||
*/
|
||||
#define OMAP4_DPLL_ABE_DEFFREQ 98304000
|
||||
|
||||
/* Root clocks */
|
||||
|
||||
DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
|
||||
@ -124,6 +132,8 @@ static struct dpll_data dpll_abe_dd = {
|
||||
.enable_mask = OMAP4430_DPLL_EN_MASK,
|
||||
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
|
||||
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
|
||||
.m4xen_mask = OMAP4430_DPLL_REGM4XEN_MASK,
|
||||
.lpmode_mask = OMAP4430_DPLL_LPMODE_EN_MASK,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
@ -233,7 +243,7 @@ static struct dpll_data dpll_core_dd = {
|
||||
|
||||
|
||||
static const char *dpll_core_ck_parents[] = {
|
||||
"sys_clkin_ck",
|
||||
"sys_clkin_ck", "core_hsd_byp_clk_mux_ck"
|
||||
};
|
||||
|
||||
static struct clk dpll_core_ck;
|
||||
@ -286,9 +296,9 @@ DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
|
||||
OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
|
||||
OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
|
||||
|
||||
DEFINE_CLK_OMAP_HSDIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck",
|
||||
&dpll_core_m5x2_ck, 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA,
|
||||
OMAP4430_CLKSEL_0_1_MASK);
|
||||
DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
|
||||
0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
|
||||
OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
|
||||
|
||||
DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
|
||||
0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
|
||||
@ -363,8 +373,21 @@ static struct dpll_data dpll_iva_dd = {
|
||||
.min_divider = 1,
|
||||
};
|
||||
|
||||
static const char *dpll_iva_ck_parents[] = {
|
||||
"sys_clkin_ck", "iva_hsd_byp_clk_mux_ck"
|
||||
};
|
||||
|
||||
static struct clk dpll_iva_ck;
|
||||
|
||||
static const struct clk_ops dpll_ck_ops = {
|
||||
.enable = &omap3_noncore_dpll_enable,
|
||||
.disable = &omap3_noncore_dpll_disable,
|
||||
.recalc_rate = &omap3_dpll_recalc,
|
||||
.round_rate = &omap2_dpll_round_rate,
|
||||
.set_rate = &omap3_noncore_dpll_set_rate,
|
||||
.get_parent = &omap2_init_dpll_parent,
|
||||
};
|
||||
|
||||
static struct clk_hw_omap dpll_iva_ck_hw = {
|
||||
.hw = {
|
||||
.clk = &dpll_iva_ck,
|
||||
@ -373,7 +396,7 @@ static struct clk_hw_omap dpll_iva_ck_hw = {
|
||||
.ops = &clkhwops_omap3_dpll,
|
||||
};
|
||||
|
||||
DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
|
||||
DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops);
|
||||
|
||||
static const char *dpll_iva_x2_ck_parents[] = {
|
||||
"dpll_iva_ck",
|
||||
@ -416,6 +439,10 @@ static struct dpll_data dpll_mpu_dd = {
|
||||
.min_divider = 1,
|
||||
};
|
||||
|
||||
static const char *dpll_mpu_ck_parents[] = {
|
||||
"sys_clkin_ck", "div_mpu_hs_clk"
|
||||
};
|
||||
|
||||
static struct clk dpll_mpu_ck;
|
||||
|
||||
static struct clk_hw_omap dpll_mpu_ck_hw = {
|
||||
@ -426,7 +453,7 @@ static struct clk_hw_omap dpll_mpu_ck_hw = {
|
||||
.ops = &clkhwops_omap3_dpll,
|
||||
};
|
||||
|
||||
DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
|
||||
DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops);
|
||||
|
||||
DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
|
||||
|
||||
@ -464,6 +491,9 @@ static struct dpll_data dpll_per_dd = {
|
||||
.min_divider = 1,
|
||||
};
|
||||
|
||||
static const char *dpll_per_ck_parents[] = {
|
||||
"sys_clkin_ck", "per_hsd_byp_clk_mux_ck"
|
||||
};
|
||||
|
||||
static struct clk dpll_per_ck;
|
||||
|
||||
@ -475,7 +505,7 @@ static struct clk_hw_omap dpll_per_ck_hw = {
|
||||
.ops = &clkhwops_omap3_dpll,
|
||||
};
|
||||
|
||||
DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
|
||||
DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
|
||||
|
||||
DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
|
||||
OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
|
||||
@ -559,6 +589,10 @@ static struct dpll_data dpll_usb_dd = {
|
||||
.min_divider = 1,
|
||||
};
|
||||
|
||||
static const char *dpll_usb_ck_parents[] = {
|
||||
"sys_clkin_ck", "usb_hs_clk_div_ck"
|
||||
};
|
||||
|
||||
static struct clk dpll_usb_ck;
|
||||
|
||||
static struct clk_hw_omap dpll_usb_ck_hw = {
|
||||
@ -569,7 +603,7 @@ static struct clk_hw_omap dpll_usb_ck_hw = {
|
||||
.ops = &clkhwops_omap3_dpll,
|
||||
};
|
||||
|
||||
DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
|
||||
DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_ck_ops);
|
||||
|
||||
static const char *dpll_usb_clkdcoldo_ck_parents[] = {
|
||||
"dpll_usb_ck",
|
||||
@ -696,9 +730,13 @@ DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
|
||||
OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
|
||||
OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
|
||||
|
||||
static const char *dbgclk_mux_ck_parents[] = {
|
||||
"sys_clkin_ck"
|
||||
};
|
||||
|
||||
static struct clk dbgclk_mux_ck;
|
||||
DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
|
||||
DEFINE_STRUCT_CLK(dbgclk_mux_ck, dpll_core_ck_parents,
|
||||
DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents,
|
||||
dpll_usb_clkdcoldo_ck_ops);
|
||||
|
||||
/* Leaf clocks controlled by modules */
|
||||
@ -1935,10 +1973,10 @@ static struct omap_clk omap44xx_clks[] = {
|
||||
CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
|
||||
};
|
||||
|
||||
@ -1955,6 +1993,7 @@ int __init omap4xxx_clk_init(void)
|
||||
{
|
||||
u32 cpu_clkflg;
|
||||
struct omap_clk *c;
|
||||
int rc;
|
||||
|
||||
if (cpu_is_omap443x()) {
|
||||
cpu_mask = RATE_IN_4430;
|
||||
@ -1983,5 +2022,18 @@ int __init omap4xxx_clk_init(void)
|
||||
omap2_clk_enable_init_clocks(enable_init_clks,
|
||||
ARRAY_SIZE(enable_init_clks));
|
||||
|
||||
/*
|
||||
* On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
|
||||
* state when turning the ABE clock domain. Workaround this by
|
||||
* locking the ABE DPLL on boot.
|
||||
*/
|
||||
if (cpu_is_omap446x()) {
|
||||
rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
|
||||
if (!rc)
|
||||
rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
|
||||
if (rc)
|
||||
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -195,6 +195,10 @@ struct clksel {
|
||||
* @enable_mask: mask of the DPLL mode bitfield in @control_reg
|
||||
* @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
|
||||
* @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
|
||||
* @last_rounded_m4xen: cache of the last M4X result of
|
||||
* omap4_dpll_regm4xen_round_rate()
|
||||
* @last_rounded_lpmode: cache of the last lpmode result of
|
||||
* omap4_dpll_lpmode_recalc()
|
||||
* @max_multiplier: maximum valid non-bypass multiplier value (actual)
|
||||
* @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
|
||||
* @min_divider: minimum valid non-bypass divider value (actual)
|
||||
@ -205,6 +209,8 @@ struct clksel {
|
||||
* @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
|
||||
* @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
|
||||
* @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
|
||||
* @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
|
||||
* @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
|
||||
* @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
|
||||
* @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
|
||||
* @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
|
||||
@ -233,6 +239,8 @@ struct dpll_data {
|
||||
u32 enable_mask;
|
||||
unsigned long last_rounded_rate;
|
||||
u16 last_rounded_m;
|
||||
u8 last_rounded_m4xen;
|
||||
u8 last_rounded_lpmode;
|
||||
u16 max_multiplier;
|
||||
u8 last_rounded_n;
|
||||
u8 min_divider;
|
||||
@ -245,6 +253,8 @@ struct dpll_data {
|
||||
u32 idlest_mask;
|
||||
u32 dco_mask;
|
||||
u32 sddiv_mask;
|
||||
u32 lpmode_mask;
|
||||
u32 m4xen_mask;
|
||||
u8 auto_recal_bit;
|
||||
u8 recal_en_bit;
|
||||
u8 recal_st_bit;
|
||||
|
||||
@ -998,7 +998,8 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
|
||||
spin_lock_irqsave(&clkdm->lock, flags);
|
||||
|
||||
/* corner case: disabling unused clocks */
|
||||
if (__clk_get_enable_count(clk) == 0)
|
||||
if ((__clk_get_enable_count(clk) == 0) &&
|
||||
(atomic_read(&clkdm->usecount) == 0))
|
||||
goto ccd_exit;
|
||||
|
||||
if (atomic_read(&clkdm->usecount) == 0) {
|
||||
|
||||
@ -16,8 +16,6 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_data/dsp-omap.h>
|
||||
|
||||
#include <plat/vram.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "omap-secure.h"
|
||||
|
||||
@ -32,7 +30,6 @@ int __weak omap_secure_ram_reserve_memblock(void)
|
||||
|
||||
void __init omap_reserve(void)
|
||||
{
|
||||
omap_vram_reserve_sdram_memblock();
|
||||
omap_dsp_reserve_sdram_memblock();
|
||||
omap_secure_ram_reserve_memblock();
|
||||
omap_barrier_reserve_memblock();
|
||||
|
||||
@ -40,6 +40,8 @@ struct omap3_idle_statedata {
|
||||
u32 core_state;
|
||||
};
|
||||
|
||||
static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
|
||||
|
||||
static struct omap3_idle_statedata omap3_idle_data[] = {
|
||||
{
|
||||
.mpu_state = PWRDM_POWER_ON,
|
||||
@ -71,7 +73,7 @@ static struct omap3_idle_statedata omap3_idle_data[] = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
|
||||
/* Private functions */
|
||||
|
||||
static int __omap3_enter_idle(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv,
|
||||
@ -260,11 +262,11 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
|
||||
return ret;
|
||||
}
|
||||
|
||||
DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
|
||||
static DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
|
||||
|
||||
struct cpuidle_driver omap3_idle_driver = {
|
||||
.name = "omap3_idle",
|
||||
.owner = THIS_MODULE,
|
||||
static struct cpuidle_driver omap3_idle_driver = {
|
||||
.name = "omap3_idle",
|
||||
.owner = THIS_MODULE,
|
||||
.states = {
|
||||
{
|
||||
.enter = omap3_enter_idle_bm,
|
||||
@ -327,6 +329,8 @@ struct cpuidle_driver omap3_idle_driver = {
|
||||
.safe_state_index = 0,
|
||||
};
|
||||
|
||||
/* Public functions */
|
||||
|
||||
/**
|
||||
* omap3_idle_init - Init routine for OMAP3 idle
|
||||
*
|
||||
|
||||
@ -54,6 +54,8 @@ static struct clockdomain *cpu_clkdm[NR_CPUS];
|
||||
static atomic_t abort_barrier;
|
||||
static bool cpu_done[NR_CPUS];
|
||||
|
||||
/* Private functions */
|
||||
|
||||
/**
|
||||
* omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
|
||||
* @dev: cpuidle device
|
||||
@ -161,9 +163,19 @@ fail:
|
||||
return index;
|
||||
}
|
||||
|
||||
DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
|
||||
/*
|
||||
* For each cpu, setup the broadcast timer because local timers
|
||||
* stops for the states above C1.
|
||||
*/
|
||||
static void omap_setup_broadcast_timer(void *arg)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
|
||||
}
|
||||
|
||||
struct cpuidle_driver omap4_idle_driver = {
|
||||
static DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
|
||||
|
||||
static struct cpuidle_driver omap4_idle_driver = {
|
||||
.name = "omap4_idle",
|
||||
.owner = THIS_MODULE,
|
||||
.en_core_tk_irqen = 1,
|
||||
@ -178,7 +190,7 @@ struct cpuidle_driver omap4_idle_driver = {
|
||||
.desc = "MPUSS ON"
|
||||
},
|
||||
{
|
||||
/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
|
||||
/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
|
||||
.exit_latency = 328 + 440,
|
||||
.target_residency = 960,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
|
||||
@ -200,15 +212,7 @@ struct cpuidle_driver omap4_idle_driver = {
|
||||
.safe_state_index = 0,
|
||||
};
|
||||
|
||||
/*
|
||||
* For each cpu, setup the broadcast timer because local timers
|
||||
* stops for the states above C1.
|
||||
*/
|
||||
static void omap_setup_broadcast_timer(void *arg)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
|
||||
}
|
||||
/* Public functions */
|
||||
|
||||
/**
|
||||
* omap4_idle_init - Init routine for OMAP4 idle
|
||||
|
||||
@ -291,16 +291,13 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
|
||||
|
||||
/*
|
||||
* _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
|
||||
* @clk: struct clk * of DPLL to set
|
||||
* @m: DPLL multiplier to set
|
||||
* @n: DPLL divider to set
|
||||
* @freqsel: FREQSEL value to set
|
||||
* @clk: struct clk * of DPLL to set
|
||||
* @freqsel: FREQSEL value to set
|
||||
*
|
||||
* Program the DPLL with the supplied M, N values, and wait for the DPLL to
|
||||
* lock.. Returns -EINVAL upon error, or 0 upon success.
|
||||
* Program the DPLL with the last M, N values calculated, and wait for
|
||||
* the DPLL to lock. Returns -EINVAL upon error, or 0 upon success.
|
||||
*/
|
||||
static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n,
|
||||
u16 freqsel)
|
||||
static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
|
||||
{
|
||||
struct dpll_data *dd = clk->dpll_data;
|
||||
u8 dco, sd_div;
|
||||
@ -323,23 +320,45 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n,
|
||||
/* Set DPLL multiplier, divider */
|
||||
v = __raw_readl(dd->mult_div1_reg);
|
||||
v &= ~(dd->mult_mask | dd->div1_mask);
|
||||
v |= m << __ffs(dd->mult_mask);
|
||||
v |= (n - 1) << __ffs(dd->div1_mask);
|
||||
v |= dd->last_rounded_m << __ffs(dd->mult_mask);
|
||||
v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
|
||||
|
||||
/* Configure dco and sd_div for dplls that have these fields */
|
||||
if (dd->dco_mask) {
|
||||
_lookup_dco(clk, &dco, m, n);
|
||||
_lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);
|
||||
v &= ~(dd->dco_mask);
|
||||
v |= dco << __ffs(dd->dco_mask);
|
||||
}
|
||||
if (dd->sddiv_mask) {
|
||||
_lookup_sddiv(clk, &sd_div, m, n);
|
||||
_lookup_sddiv(clk, &sd_div, dd->last_rounded_m,
|
||||
dd->last_rounded_n);
|
||||
v &= ~(dd->sddiv_mask);
|
||||
v |= sd_div << __ffs(dd->sddiv_mask);
|
||||
}
|
||||
|
||||
__raw_writel(v, dd->mult_div1_reg);
|
||||
|
||||
/* Set 4X multiplier and low-power mode */
|
||||
if (dd->m4xen_mask || dd->lpmode_mask) {
|
||||
v = __raw_readl(dd->control_reg);
|
||||
|
||||
if (dd->m4xen_mask) {
|
||||
if (dd->last_rounded_m4xen)
|
||||
v |= dd->m4xen_mask;
|
||||
else
|
||||
v &= ~dd->m4xen_mask;
|
||||
}
|
||||
|
||||
if (dd->lpmode_mask) {
|
||||
if (dd->last_rounded_lpmode)
|
||||
v |= dd->lpmode_mask;
|
||||
else
|
||||
v &= ~dd->lpmode_mask;
|
||||
}
|
||||
|
||||
__raw_writel(v, dd->control_reg);
|
||||
}
|
||||
|
||||
/* We let the clock framework set the other output dividers later */
|
||||
|
||||
/* REVISIT: Set ramp-up delay? */
|
||||
@ -492,8 +511,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
pr_debug("%s: %s: set rate: locking rate to %lu.\n",
|
||||
__func__, __clk_get_name(hw->clk), rate);
|
||||
|
||||
ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
|
||||
dd->last_rounded_n, freqsel);
|
||||
ret = omap3_noncore_dpll_program(clk, freqsel);
|
||||
if (!ret)
|
||||
new_parent = dd->clk_ref;
|
||||
}
|
||||
|
||||
@ -20,6 +20,15 @@
|
||||
#include "clock44xx.h"
|
||||
#include "cm-regbits-44xx.h"
|
||||
|
||||
/*
|
||||
* Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
|
||||
* can supported when using the DPLL low-power mode. Frequencies are
|
||||
* defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control,
|
||||
* Status, and Low-Power Operation Mode".
|
||||
*/
|
||||
#define OMAP4_DPLL_LP_FINT_MAX 1000000
|
||||
#define OMAP4_DPLL_LP_FOUT_MAX 100000000
|
||||
|
||||
/* Supported only on OMAP4 */
|
||||
int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
|
||||
{
|
||||
@ -81,6 +90,31 @@ const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
|
||||
.deny_idle = omap4_dpllmx_deny_gatectrl,
|
||||
};
|
||||
|
||||
/**
|
||||
* omap4_dpll_lpmode_recalc - compute DPLL low-power setting
|
||||
* @dd: pointer to the dpll data structure
|
||||
*
|
||||
* Calculates if low-power mode can be enabled based upon the last
|
||||
* multiplier and divider values calculated. If low-power mode can be
|
||||
* enabled, then the bit to enable low-power mode is stored in the
|
||||
* last_rounded_lpmode variable. This implementation is based upon the
|
||||
* criteria for enabling low-power mode as described in the OMAP4430/60
|
||||
* Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power
|
||||
* Operation Mode".
|
||||
*/
|
||||
static void omap4_dpll_lpmode_recalc(struct dpll_data *dd)
|
||||
{
|
||||
long fint, fout;
|
||||
|
||||
fint = __clk_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1);
|
||||
fout = fint * dd->last_rounded_m;
|
||||
|
||||
if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX))
|
||||
dd->last_rounded_lpmode = 1;
|
||||
else
|
||||
dd->last_rounded_lpmode = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
|
||||
* @clk: struct clk * of the DPLL to compute the rate for
|
||||
@ -130,7 +164,6 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
||||
u32 v;
|
||||
struct dpll_data *dd;
|
||||
long r;
|
||||
|
||||
@ -139,18 +172,31 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
|
||||
|
||||
dd = clk->dpll_data;
|
||||
|
||||
/* regm4xen adds a multiplier of 4 to DPLL calculations */
|
||||
v = __raw_readl(dd->control_reg) & OMAP4430_DPLL_REGM4XEN_MASK;
|
||||
|
||||
if (v)
|
||||
target_rate = target_rate / OMAP4430_REGM4XEN_MULT;
|
||||
dd->last_rounded_m4xen = 0;
|
||||
|
||||
/*
|
||||
* First try to compute the DPLL configuration for
|
||||
* target rate without using the 4X multiplier.
|
||||
*/
|
||||
r = omap2_dpll_round_rate(hw, target_rate, NULL);
|
||||
if (r != ~0)
|
||||
goto out;
|
||||
|
||||
/*
|
||||
* If we did not find a valid DPLL configuration, try again, but
|
||||
* this time see if using the 4X multiplier can help. Enabling the
|
||||
* 4X multiplier is equivalent to dividing the target rate by 4.
|
||||
*/
|
||||
r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT,
|
||||
NULL);
|
||||
if (r == ~0)
|
||||
return r;
|
||||
|
||||
if (v)
|
||||
clk->dpll_data->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
|
||||
dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
|
||||
dd->last_rounded_m4xen = 1;
|
||||
|
||||
return clk->dpll_data->last_rounded_rate;
|
||||
out:
|
||||
omap4_dpll_lpmode_recalc(dd);
|
||||
|
||||
return dd->last_rounded_rate;
|
||||
}
|
||||
|
||||
@ -135,10 +135,7 @@ static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
|
||||
|
||||
old_mode = omap_mux_read(partition, gpio_mux->reg_offset);
|
||||
mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
|
||||
if (partition->flags & OMAP_MUX_GPIO_IN_MODE3)
|
||||
mux_mode |= OMAP_MUX_MODE3;
|
||||
else
|
||||
mux_mode |= OMAP_MUX_MODE4;
|
||||
mux_mode |= partition->gpio;
|
||||
pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__,
|
||||
gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
|
||||
omap_mux_write(partition, mux_mode, gpio_mux->reg_offset);
|
||||
@ -800,7 +797,7 @@ int __init omap_mux_late_init(void)
|
||||
struct omap_mux *m = &e->mux;
|
||||
u16 mode = omap_mux_read(partition, m->reg_offset);
|
||||
|
||||
if (OMAP_MODE_GPIO(mode))
|
||||
if (OMAP_MODE_GPIO(partition, mode))
|
||||
continue;
|
||||
|
||||
#ifndef CONFIG_DEBUG_FS
|
||||
@ -1065,7 +1062,7 @@ static void __init omap_mux_init_list(struct omap_mux_partition *partition,
|
||||
}
|
||||
#else
|
||||
/* Skip pins that are not muxed as GPIO by bootloader */
|
||||
if (!OMAP_MODE_GPIO(omap_mux_read(partition,
|
||||
if (!OMAP_MODE_GPIO(partition, omap_mux_read(partition,
|
||||
superset->reg_offset))) {
|
||||
superset++;
|
||||
continue;
|
||||
@ -1132,6 +1129,7 @@ int __init omap_mux_init(const char *name, u32 flags,
|
||||
|
||||
partition->name = name;
|
||||
partition->flags = flags;
|
||||
partition->gpio = flags & OMAP_MUX_MODE7;
|
||||
partition->size = mux_size;
|
||||
partition->phys = mux_pbase;
|
||||
partition->base = ioremap(mux_pbase, mux_size);
|
||||
|
||||
@ -58,7 +58,8 @@
|
||||
#define OMAP_PIN_OFF_INPUT_PULLDOWN (OMAP_OFF_EN | OMAP_OFF_PULL_EN)
|
||||
#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN
|
||||
|
||||
#define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4)
|
||||
#define OMAP_MODE_GPIO(partition, x) (((x) & OMAP_MUX_MODE7) == \
|
||||
partition->gpio)
|
||||
#define OMAP_MODE_UART(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE0)
|
||||
|
||||
/* Flags for omapX_mux_init */
|
||||
@ -79,13 +80,20 @@
|
||||
/*
|
||||
* omap_mux_init flags definition:
|
||||
*
|
||||
* OMAP_GPIO_MUX_MODE, bits 0-2: gpio muxing mode, same like pad control
|
||||
* register which includes values from 0-7.
|
||||
* OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits.
|
||||
* The default value is 16 bits.
|
||||
* OMAP_MUX_GPIO_IN_MODE3: The GPIO is selected in mode3.
|
||||
* The default is mode4.
|
||||
*/
|
||||
#define OMAP_MUX_REG_8BIT (1 << 0)
|
||||
#define OMAP_MUX_GPIO_IN_MODE3 (1 << 1)
|
||||
#define OMAP_MUX_GPIO_IN_MODE0 OMAP_MUX_MODE0
|
||||
#define OMAP_MUX_GPIO_IN_MODE1 OMAP_MUX_MODE1
|
||||
#define OMAP_MUX_GPIO_IN_MODE2 OMAP_MUX_MODE2
|
||||
#define OMAP_MUX_GPIO_IN_MODE3 OMAP_MUX_MODE3
|
||||
#define OMAP_MUX_GPIO_IN_MODE4 OMAP_MUX_MODE4
|
||||
#define OMAP_MUX_GPIO_IN_MODE5 OMAP_MUX_MODE5
|
||||
#define OMAP_MUX_GPIO_IN_MODE6 OMAP_MUX_MODE6
|
||||
#define OMAP_MUX_GPIO_IN_MODE7 OMAP_MUX_MODE7
|
||||
#define OMAP_MUX_REG_8BIT (1 << 3)
|
||||
|
||||
/**
|
||||
* struct omap_board_data - board specific device data
|
||||
@ -105,6 +113,7 @@ struct omap_board_data {
|
||||
* struct mux_partition - contain partition related information
|
||||
* @name: name of the current partition
|
||||
* @flags: flags specific to this partition
|
||||
* @gpio: gpio mux mode
|
||||
* @phys: physical address
|
||||
* @size: partition size
|
||||
* @base: virtual address after ioremap
|
||||
@ -114,6 +123,7 @@ struct omap_board_data {
|
||||
struct omap_mux_partition {
|
||||
const char *name;
|
||||
u32 flags;
|
||||
u32 gpio;
|
||||
u32 phys;
|
||||
u32 size;
|
||||
void __iomem *base;
|
||||
|
||||
@ -2053,7 +2053,7 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return omap_mux_init("core", 0,
|
||||
return omap_mux_init("core", OMAP_MUX_GPIO_IN_MODE4,
|
||||
OMAP3_CONTROL_PADCONF_MUX_PBASE,
|
||||
OMAP3_CONTROL_PADCONF_MUX_SIZE,
|
||||
omap3_muxmodes, package_subset, board_subset,
|
||||
|
||||
@ -27,8 +27,7 @@
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/console.h>
|
||||
#include <linux/omap-dma.h>
|
||||
|
||||
#include <plat/omap-serial.h>
|
||||
#include <linux/platform_data/serial-omap.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "omap_hwmod.h"
|
||||
|
||||
@ -190,7 +190,7 @@ static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
|
||||
* kernel registering these devices remove them dynamically from the device
|
||||
* tree on boot.
|
||||
*/
|
||||
void __init omap_dmtimer_init(void)
|
||||
static void __init omap_dmtimer_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
@ -210,7 +210,7 @@ void __init omap_dmtimer_init(void)
|
||||
*
|
||||
* Get the timer errata flags that are specific to the OMAP device being used.
|
||||
*/
|
||||
u32 __init omap_dm_timer_get_errata(void)
|
||||
static u32 __init omap_dm_timer_get_errata(void)
|
||||
{
|
||||
if (cpu_is_omap24xx())
|
||||
return 0;
|
||||
@ -392,7 +392,7 @@ static struct of_device_id omap_counter_match[] __initdata = {
|
||||
};
|
||||
|
||||
/* Setup free-running counter for clocksource */
|
||||
static int __init omap2_sync32k_clocksource_init(void)
|
||||
static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
|
||||
{
|
||||
int ret;
|
||||
struct device_node *np = NULL;
|
||||
|
||||
@ -508,6 +508,10 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
|
||||
if (cpu_is_omap34xx()) {
|
||||
setup_ehci_io_mux(pdata->port_mode);
|
||||
setup_ohci_io_mux(pdata->port_mode);
|
||||
|
||||
if (omap_rev() <= OMAP3430_REV_ES2_1)
|
||||
usbhs_data.single_ulpi_bypass = true;
|
||||
|
||||
} else if (cpu_is_omap44xx()) {
|
||||
setup_4430ehci_io_mux(pdata->port_mode);
|
||||
setup_4430ohci_io_mux(pdata->port_mode);
|
||||
|
||||
@ -104,7 +104,7 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
|
||||
static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
|
||||
/* name parent rate enabled */
|
||||
{ "clk_m", NULL, 0, true },
|
||||
{ "pll_p", "clk_m", 408000000, true },
|
||||
{ "pll_p", "pll_ref", 408000000, true },
|
||||
{ "pll_p_out1", "pll_p", 9600000, true },
|
||||
{ "pll_p_out4", "pll_p", 102000000, true },
|
||||
{ "sclk", "pll_p_out4", 102000000, true },
|
||||
|
||||
@ -2045,9 +2045,7 @@ struct clk_ops tegra30_periph_clk_ops = {
|
||||
static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct clk *d = clk_get_sys(NULL, "pll_d");
|
||||
/* The DSIB parent selection bit is in PLLD base
|
||||
register - can not do direct r-m-w, must be
|
||||
protected by PLLD lock */
|
||||
/* The DSIB parent selection bit is in PLLD base register */
|
||||
tegra_clk_cfg_ex(
|
||||
d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
|
||||
|
||||
|
||||
@ -27,7 +27,6 @@
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/mtd/fsmc.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_data/clk-u300.h>
|
||||
@ -1553,39 +1552,6 @@ static struct pinctrl_map __initdata u300_pinmux_map[] = {
|
||||
pin_highz_conf),
|
||||
};
|
||||
|
||||
struct u300_mux_hog {
|
||||
struct device *dev;
|
||||
struct pinctrl *p;
|
||||
};
|
||||
|
||||
static struct u300_mux_hog u300_mux_hogs[] = {
|
||||
{
|
||||
.dev = &uart0_device.dev,
|
||||
},
|
||||
{
|
||||
.dev = &mmcsd_device.dev,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init u300_pinctrl_fetch(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) {
|
||||
struct pinctrl *p;
|
||||
|
||||
p = pinctrl_get_select_default(u300_mux_hogs[i].dev);
|
||||
if (IS_ERR(p)) {
|
||||
pr_err("u300: could not get pinmux hog for dev %s\n",
|
||||
dev_name(u300_mux_hogs[i].dev));
|
||||
continue;
|
||||
}
|
||||
u300_mux_hogs[i].p = p;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
subsys_initcall(u300_pinctrl_fetch);
|
||||
|
||||
/*
|
||||
* Notice that AMBA devices are initialized before platform devices.
|
||||
*
|
||||
|
||||
@ -8,6 +8,7 @@
|
||||
#ifndef __DEVICES_DB8500_H
|
||||
#define __DEVICES_DB8500_H
|
||||
|
||||
#include <linux/platform_data/usb-musb-ux500.h>
|
||||
#include <mach/irqs.h>
|
||||
#include "devices-common.h"
|
||||
|
||||
|
||||
@ -11,7 +11,6 @@ obj- :=
|
||||
# omap_device support (OMAP2+ only at the moment)
|
||||
|
||||
obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
|
||||
obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
|
||||
obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
|
||||
i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
|
||||
obj-y += $(i2c-omap-m) $(i2c-omap-y)
|
||||
|
||||
@ -1,92 +0,0 @@
|
||||
/*
|
||||
* linux/arch/arm/plat-omap/debug-devices.c
|
||||
*
|
||||
* Copyright (C) 2005 Nokia Corporation
|
||||
* Modified from mach-omap2/board-h4.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
#include <plat/debug-devices.h>
|
||||
|
||||
/* Many OMAP development platforms reuse the same "debug board"; these
|
||||
* platforms include H2, H3, H4, and Perseus2.
|
||||
*/
|
||||
|
||||
static struct smc91x_platdata smc91x_info = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
|
||||
.leda = RPC_LED_100_10,
|
||||
.ledb = RPC_LED_TX_RX,
|
||||
};
|
||||
|
||||
static struct resource smc91x_resources[] = {
|
||||
[0] = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &smc91x_info,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
};
|
||||
|
||||
static struct resource led_resources[] = {
|
||||
[0] = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device led_device = {
|
||||
.name = "omap_dbg_led",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(led_resources),
|
||||
.resource = led_resources,
|
||||
};
|
||||
|
||||
static struct platform_device *debug_devices[] __initdata = {
|
||||
&smc91x_device,
|
||||
&led_device,
|
||||
/* ps2 kbd + mouse ports */
|
||||
/* 4 extra uarts */
|
||||
/* 6 input dip switches */
|
||||
/* 8 output pins */
|
||||
};
|
||||
|
||||
int __init debug_card_init(u32 addr, unsigned gpio)
|
||||
{
|
||||
int status;
|
||||
|
||||
smc91x_resources[0].start = addr + 0x300;
|
||||
smc91x_resources[0].end = addr + 0x30f;
|
||||
|
||||
smc91x_resources[1].start = gpio_to_irq(gpio);
|
||||
smc91x_resources[1].end = gpio_to_irq(gpio);
|
||||
|
||||
status = gpio_request(gpio, "SMC91x irq");
|
||||
if (status < 0) {
|
||||
printk(KERN_ERR "GPIO%d unavailable for smc91x IRQ\n", gpio);
|
||||
return status;
|
||||
}
|
||||
gpio_direction_input(gpio);
|
||||
|
||||
led_resources[0].start = addr;
|
||||
led_resources[0].end = addr + SZ_4K - 1;
|
||||
|
||||
return platform_add_devices(debug_devices, ARRAY_SIZE(debug_devices));
|
||||
}
|
||||
@ -1,2 +0,0 @@
|
||||
/* for TI reference platforms sharing the same debug card */
|
||||
extern int debug_card_init(u32 addr, unsigned gpio);
|
||||
@ -157,6 +157,7 @@ int tegra_ahb_enable_smmu(struct device_node *dn)
|
||||
EXPORT_SYMBOL(tegra_ahb_enable_smmu);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int tegra_ahb_suspend(struct device *dev)
|
||||
{
|
||||
int i;
|
||||
@ -176,6 +177,7 @@ static int tegra_ahb_resume(struct device *dev)
|
||||
gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
|
||||
tegra_ahb_suspend,
|
||||
|
||||
@ -25,7 +25,6 @@
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/platform_data/usb-omap.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
@ -384,7 +383,7 @@ static void omap_usbhs_init(struct device *dev)
|
||||
reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
|
||||
|
||||
/* Bypass the TLL module for PHY mode operation */
|
||||
if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) {
|
||||
if (pdata->single_ulpi_bypass) {
|
||||
dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
|
||||
if (is_ehci_phy_mode(pdata->port_mode[0]) ||
|
||||
is_ehci_phy_mode(pdata->port_mode[1]) ||
|
||||
|
||||
@ -41,8 +41,7 @@
|
||||
#include <linux/of.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <plat/omap-serial.h>
|
||||
#include <linux/platform_data/serial-omap.h>
|
||||
|
||||
#define OMAP_MAX_HSUART_PORTS 6
|
||||
|
||||
|
||||
@ -59,6 +59,9 @@ struct usbhs_omap_platform_data {
|
||||
|
||||
struct ehci_hcd_omap_platform_data *ehci_data;
|
||||
struct ohci_hcd_omap_platform_data *ohci_data;
|
||||
|
||||
/* OMAP3 <= ES2.1 have a single ulpi bypass control bit */
|
||||
unsigned single_ulpi_bypass:1;
|
||||
};
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
@ -28,7 +28,7 @@ struct omap_dss_device;
|
||||
* @power_down_gpio: gpio number for PD pin (or -1 if not available)
|
||||
*/
|
||||
struct tfp410_platform_data {
|
||||
u16 i2c_bus_num;
|
||||
int i2c_bus_num;
|
||||
int power_down_gpio;
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user