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SoC glue layer changes for SGX on omap variants for v5.4
For a while we've had omap4 sgx glue layer defined in dts and probed with ti-sysc driver. This allows idling the sgx module for PM, and removes the need for custom platform glue layer code for any further driver changes. We first drop the unused legacy platform data for omap4 sgx. Then for omap5, we need add the missing clkctrl clock data so we can configure sgx. And we configure sgx for omap34xx, omap36xx and am3517. For am335x, we still have a dependency for rstctrl reset driver changes, so that will be added later on. Note that this branch is based on earlier ti-sysc branch for omap36xx glue layer quirk handling. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl1kD8wRHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXPYkQ/9EREzi6fePsuZfzlVFgDx8baAtyKUiiv7 GXEXecyLQkTz2eWGDrgVPShX8s/e1kfByQUyNS7GolkfOq8CRnyvdoexx3uBPIOD XpNF81Of9DpK8svlhTstJEjHDsFFGXNRg6tEASNn+LCJZGiZXZO85Av/xh2dEMoh CdvqT9cVn1e8PGvEep+gEutSjcOTOSDYHfGwn6/IDzdbtWBAekRX2LrPD8592HUk v6HsY1C1Okh25pUgoLmQEI9sfjKhjwyvEGnTesdfX3KKisOyJXp7imnGeoga0Uy4 gDEGsI59mKG3KJmoTXvLpD08GX3GNXBnnfpdux7R8Bz634HdbD+g+/6XBy5QDpso BtokfGpwfyif6ovgz6vBVZhC6ZUb4FuP+r+ozjvIJEoHdZS78pi0RlAz/YqaXGgF izGcALQQR9XV6uud/eOOB8CeX80oAxGkrw8HzKQmS6HGSwwyBW7Fgb1YExhi1oeU 5w9kILd3l0AUWfjL9eJX7L7le0ghJIWQRbdctSKkEnYFLl7EFdizX3l55fx2miPU XYe131yk0Fsh3SKWF3bJSHZSpd3D4ERsxdENKtyh/deH+8RPweGLuqs7LUOOG7Ny mixq8rCfcbI6hkHMu5Edb5qUn3tD52tDP7xXLKb8aeFVHSvuPkQOunQmUlmIXKio +FBG+HLTFS8= =a2cp -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.4/ti-sysc-sgx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late SoC glue layer changes for SGX on omap variants for v5.4 For a while we've had omap4 sgx glue layer defined in dts and probed with ti-sysc driver. This allows idling the sgx module for PM, and removes the need for custom platform glue layer code for any further driver changes. We first drop the unused legacy platform data for omap4 sgx. Then for omap5, we need add the missing clkctrl clock data so we can configure sgx. And we configure sgx for omap34xx, omap36xx and am3517. For am335x, we still have a dependency for rstctrl reset driver changes, so that will be added later on. Note that this branch is based on earlier ti-sysc branch for omap36xx glue layer quirk handling. * tag 'omap-for-v5.4/ti-sysc-sgx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: ARM: dts: Configure interconnect target module for am3517sgx ARM: dts: Configure interconnect target module for omap3 sgx ARM: dts: Configure sgx for omap5 clk: ti: add clkctrl data omap5 sgx ARM: OMAP2+: Drop legacy platform data for omap4 gpu Link: https://lore.kernel.org/r/pull-1567016893-318461@atomide.com-4 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
1fb2e59cf5
arch/arm
boot/dts
mach-omap2
drivers/clk/ti
include/dt-bindings/clock
@ -88,6 +88,30 @@
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interrupts = <24>;
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clocks = <&hecc_ck>;
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};
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/*
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* On am3517 the OCP registers do not seem to be accessible
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* similar to the omap34xx. Maybe SGX is permanently set to
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* "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
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* write-only at 0x50000e10. We detect SGX based on the SGX
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* revision register instead of the unreadable OCP revision
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* register.
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*/
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sgx_module: target-module@50000000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x50000014 0x4>;
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reg-names = "rev";
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clocks = <&sgx_fck>, <&sgx_ick>;
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clock-names = "fck", "ick";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x50000000 0x4000>;
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/*
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* Closed source PowerVR driver, no child device
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* binding or driver in mainline
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*/
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};
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};
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};
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@ -100,6 +100,32 @@
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interrupts = <18>;
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};
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};
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/*
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* On omap34xx the OCP registers do not seem to be accessible
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* at all unlike on 36xx. Maybe SGX is permanently set to
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* "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
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* write-only at 0x50000e10. We detect SGX based on the SGX
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* revision register instead of the unreadable OCP revision
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* register. Also note that on early 34xx es1 revision there
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* are also different clocks, but we do not have any dts users
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* for it.
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*/
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sgx_module: target-module@50000000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x50000014 0x4>;
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reg-names = "rev";
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clocks = <&sgx_fck>, <&sgx_ick>;
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clock-names = "fck", "ick";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x50000000 0x4000>;
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/*
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* Closed source PowerVR driver, no child device
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* binding or driver in mainline
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*/
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};
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};
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thermal_zones: thermal-zones {
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@ -139,6 +139,34 @@
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interrupts = <18>;
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};
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};
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/*
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* Note that the sysconfig register layout is a subset of the
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* "ti,sysc-omap4" type register with just sidle and midle bits
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* available while omap34xx has "ti,sysc-omap2" type sysconfig.
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*/
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sgx_module: target-module@50000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x5000fe00 0x4>,
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<0x5000fe10 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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clocks = <&sgx_fck>, <&sgx_ick>;
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clock-names = "fck", "ick";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x50000000 0x2000000>;
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/*
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* Closed source PowerVR driver, no child device
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* binding or driver in mainline
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*/
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};
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};
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thermal_zones: thermal-zones {
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@ -330,7 +330,6 @@
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target-module@56000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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ti,hwmods = "gpu";
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reg = <0x5601fc00 0x4>,
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<0x5601fc10 0x4>;
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reg-names = "rev", "sysc";
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@ -257,6 +257,29 @@
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ports-implemented = <0x1>;
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};
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target-module@56000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x5600fe00 0x4>,
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<0x5600fe10 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x56000000 0x2000000>;
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/*
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* Closed source PowerVR driver, no child device
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* binding or driver in mainline
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*/
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};
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dss: dss@58000000 {
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compatible = "ti,omap5-dss";
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reg = <0x58000000 0x80>;
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@ -1146,6 +1146,20 @@
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};
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};
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gpu_cm: clock-controller@1500 {
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compatible = "ti,omap4-cm";
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reg = <0x1500 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1500 0x100>;
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gpu_clkctrl: clk@20 {
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compatible = "ti,clkctrl";
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reg = <0x20 0x4>;
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#clock-cells = <2>;
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};
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};
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l3init_cm: l3init_cm@1600 {
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compatible = "ti,omap4-cm";
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reg = <0x1600 0x100>;
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@ -1061,41 +1061,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
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},
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};
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/*
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* 'gpu' class
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* 2d/3d graphics accelerator
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*/
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static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
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.rev_offs = 0x1fc00,
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.sysc_offs = 0x1fc10,
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.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
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MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type2,
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};
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static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
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.name = "gpu",
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.sysc = &omap44xx_gpu_sysc,
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};
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/* gpu */
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static struct omap_hwmod omap44xx_gpu_hwmod = {
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.name = "gpu",
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.class = &omap44xx_gpu_hwmod_class,
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.clkdm_name = "l3_gfx_clkdm",
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.main_clk = "sgx_clk_mux",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* 'hdq1w' class
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* hdq / 1-wire serial interface controller
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@ -2517,14 +2482,6 @@ static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* gpu -> l3_main_2 */
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static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
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.master = &omap44xx_gpu_hwmod,
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.slave = &omap44xx_l3_main_2_hwmod,
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.clk = "l3_div_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* hsi -> l3_main_2 */
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static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
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.master = &omap44xx_hsi_hwmod,
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@ -2941,14 +2898,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l3_main_2 -> gpu */
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static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
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.master = &omap44xx_l3_main_2_hwmod,
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.slave = &omap44xx_gpu_hwmod,
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.clk = "l3_div_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per -> hdq1w */
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static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
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.master = &omap44xx_l4_per_hwmod,
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@ -3339,7 +3288,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
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&omap44xx_debugss__l3_main_2,
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&omap44xx_dma_system__l3_main_2,
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&omap44xx_fdif__l3_main_2,
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&omap44xx_gpu__l3_main_2,
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&omap44xx_hsi__l3_main_2,
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&omap44xx_ipu__l3_main_2,
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&omap44xx_iss__l3_main_2,
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@ -3391,7 +3339,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
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&omap44xx_l4_per__elm,
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&omap44xx_l4_cfg__fdif,
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&omap44xx_l3_main_2__gpmc,
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&omap44xx_l3_main_2__gpu,
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&omap44xx_l4_per__hdq1w,
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&omap44xx_l4_cfg__hsi,
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&omap44xx_l3_main_2__ipu,
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@ -314,6 +314,39 @@ static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst =
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{ 0 },
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};
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static const char * const omap5_gpu_core_mux_parents[] __initconst = {
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"dpll_core_h14x2_ck",
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"dpll_per_h14x2_ck",
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NULL,
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};
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static const char * const omap5_gpu_hyd_mux_parents[] __initconst = {
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"dpll_core_h14x2_ck",
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"dpll_per_h14x2_ck",
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NULL,
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};
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static const char * const omap5_gpu_sys_clk_parents[] __initconst = {
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"sys_clkin",
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NULL,
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};
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static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = {
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.max_div = 2,
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};
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static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = {
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{ 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
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{ 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
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{ 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
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{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" },
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{ 0 },
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};
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static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
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"func_128m_clk",
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"dpll_per_m2x2_ck",
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@ -470,6 +503,7 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
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{ 0x4a008e20, omap5_l3instr_clkctrl_regs },
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{ 0x4a009020, omap5_l4per_clkctrl_regs },
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{ 0x4a009420, omap5_dss_clkctrl_regs },
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{ 0x4a009520, omap5_gpu_clkctrl_regs },
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{ 0x4a009620, omap5_l3init_clkctrl_regs },
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{ 0x4ae07920, omap5_wkupaon_clkctrl_regs },
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{ 0 },
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@ -89,6 +89,9 @@
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/* dss clocks */
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#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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/* gpu clocks */
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#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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/* l3init clocks */
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#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
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#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
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