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PCI: amlogic: Use AXG PCIE
Now that PCIE PHY has been introduced for AXG, the whole has_shared_phy logic can be mutualized between AXG and G12A platforms. This new PHY makes use of the shared MIPI/PCIE analog PHY found on AXG platforms, which need to be used in order to have reliable PCIE communications. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Remi Pommarel
Lorenzo Pieralisi
parent
e2463559ff
commit
1e6bbc4688
@ -66,7 +66,6 @@
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#define PORT_CLK_RATE 100000000UL
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#define MAX_PAYLOAD_SIZE 256
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#define MAX_READ_REQ_SIZE 256
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#define MESON_PCIE_PHY_POWERUP 0x1c
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#define PCIE_RESET_DELAY 500
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#define PCIE_SHARED_RESET 1
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#define PCIE_NORMAL_RESET 0
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@ -81,26 +80,19 @@ enum pcie_data_rate {
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struct meson_pcie_mem_res {
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void __iomem *elbi_base;
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void __iomem *cfg_base;
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void __iomem *phy_base;
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};
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struct meson_pcie_clk_res {
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struct clk *clk;
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struct clk *mipi_gate;
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struct clk *port_clk;
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struct clk *general_clk;
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};
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struct meson_pcie_rc_reset {
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struct reset_control *phy;
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struct reset_control *port;
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struct reset_control *apb;
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};
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struct meson_pcie_param {
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bool has_shared_phy;
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};
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struct meson_pcie {
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struct dw_pcie pci;
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struct meson_pcie_mem_res mem_res;
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@ -108,7 +100,6 @@ struct meson_pcie {
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struct meson_pcie_rc_reset mrst;
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struct gpio_desc *reset_gpio;
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struct phy *phy;
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const struct meson_pcie_param *param;
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};
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static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
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@ -130,13 +121,6 @@ static int meson_pcie_get_resets(struct meson_pcie *mp)
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{
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struct meson_pcie_rc_reset *mrst = &mp->mrst;
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if (!mp->param->has_shared_phy) {
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mrst->phy = meson_pcie_get_reset(mp, "phy", PCIE_SHARED_RESET);
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if (IS_ERR(mrst->phy))
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return PTR_ERR(mrst->phy);
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reset_control_deassert(mrst->phy);
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}
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mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
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if (IS_ERR(mrst->port))
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return PTR_ERR(mrst->port);
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@ -162,22 +146,6 @@ static void __iomem *meson_pcie_get_mem(struct platform_device *pdev,
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return devm_ioremap_resource(dev, res);
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}
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static void __iomem *meson_pcie_get_mem_shared(struct platform_device *pdev,
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struct meson_pcie *mp,
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const char *id)
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{
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struct device *dev = mp->pci.dev;
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struct resource *res;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id);
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if (!res) {
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dev_err(dev, "No REG resource %s\n", id);
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return ERR_PTR(-ENXIO);
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}
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return devm_ioremap(dev, res->start, resource_size(res));
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}
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static int meson_pcie_get_mems(struct platform_device *pdev,
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struct meson_pcie *mp)
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{
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@ -189,14 +157,6 @@ static int meson_pcie_get_mems(struct platform_device *pdev,
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if (IS_ERR(mp->mem_res.cfg_base))
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return PTR_ERR(mp->mem_res.cfg_base);
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/* Meson AXG SoC has two PCI controllers use same phy register */
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if (!mp->param->has_shared_phy) {
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mp->mem_res.phy_base =
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meson_pcie_get_mem_shared(pdev, mp, "phy");
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if (IS_ERR(mp->mem_res.phy_base))
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return PTR_ERR(mp->mem_res.phy_base);
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}
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return 0;
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}
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@ -204,37 +164,33 @@ static int meson_pcie_power_on(struct meson_pcie *mp)
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{
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int ret = 0;
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if (mp->param->has_shared_phy) {
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ret = phy_init(mp->phy);
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if (ret)
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return ret;
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ret = phy_init(mp->phy);
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if (ret)
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return ret;
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ret = phy_power_on(mp->phy);
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if (ret) {
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phy_exit(mp->phy);
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return ret;
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}
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} else
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writel(MESON_PCIE_PHY_POWERUP, mp->mem_res.phy_base);
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ret = phy_power_on(mp->phy);
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if (ret) {
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phy_exit(mp->phy);
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return ret;
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}
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return 0;
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}
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static void meson_pcie_power_off(struct meson_pcie *mp)
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{
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phy_power_off(mp->phy);
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phy_exit(mp->phy);
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}
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static int meson_pcie_reset(struct meson_pcie *mp)
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{
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struct meson_pcie_rc_reset *mrst = &mp->mrst;
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int ret = 0;
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if (mp->param->has_shared_phy) {
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ret = phy_reset(mp->phy);
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if (ret)
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return ret;
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} else {
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reset_control_assert(mrst->phy);
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udelay(PCIE_RESET_DELAY);
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reset_control_deassert(mrst->phy);
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udelay(PCIE_RESET_DELAY);
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}
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ret = phy_reset(mp->phy);
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if (ret)
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return ret;
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reset_control_assert(mrst->port);
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reset_control_assert(mrst->apb);
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@ -286,12 +242,6 @@ static int meson_pcie_probe_clocks(struct meson_pcie *mp)
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if (IS_ERR(res->port_clk))
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return PTR_ERR(res->port_clk);
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if (!mp->param->has_shared_phy) {
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res->mipi_gate = meson_pcie_probe_clock(dev, "mipi", 0);
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if (IS_ERR(res->mipi_gate))
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return PTR_ERR(res->mipi_gate);
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}
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res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
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if (IS_ERR(res->general_clk))
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return PTR_ERR(res->general_clk);
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@ -562,7 +512,6 @@ static const struct dw_pcie_ops dw_pcie_ops = {
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static int meson_pcie_probe(struct platform_device *pdev)
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{
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const struct meson_pcie_param *match_data;
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci;
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struct meson_pcie *mp;
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@ -576,17 +525,10 @@ static int meson_pcie_probe(struct platform_device *pdev)
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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match_data = of_device_get_match_data(dev);
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if (!match_data) {
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dev_err(dev, "failed to get match data\n");
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return -ENODEV;
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}
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mp->param = match_data;
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if (mp->param->has_shared_phy) {
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mp->phy = devm_phy_get(dev, "pcie");
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if (IS_ERR(mp->phy))
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return PTR_ERR(mp->phy);
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mp->phy = devm_phy_get(dev, "pcie");
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if (IS_ERR(mp->phy)) {
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dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
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return PTR_ERR(mp->phy);
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}
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mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
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@ -636,30 +578,16 @@ static int meson_pcie_probe(struct platform_device *pdev)
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return 0;
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err_phy:
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if (mp->param->has_shared_phy) {
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phy_power_off(mp->phy);
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phy_exit(mp->phy);
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}
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meson_pcie_power_off(mp);
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return ret;
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}
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static struct meson_pcie_param meson_pcie_axg_param = {
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.has_shared_phy = false,
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};
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static struct meson_pcie_param meson_pcie_g12a_param = {
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.has_shared_phy = true,
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};
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static const struct of_device_id meson_pcie_of_match[] = {
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{
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.compatible = "amlogic,axg-pcie",
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.data = &meson_pcie_axg_param,
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},
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{
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.compatible = "amlogic,g12a-pcie",
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.data = &meson_pcie_g12a_param,
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},
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{},
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};
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