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A fix from Mauro to correct csrow size accounting in sysfs and a sparse
fix from Stephen Hemminger. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJRTC/tAAoJEBLB8Bhh3lVKjGAP/jL6utGeRhctJLrdDqfV9zW0 CD9U3bsTIlVuuKi54VgIOsgPjXx+g3CiIWSfaeNMidrs+WeG8ly/wHblLoWv5EoY 37y2t3uHtWlGDTU5Xg1xUCr/J6xAyiza86bPuw61pQBWeCcv1vxu3hoNRwVN1ZTq lGCy3PtrZ17EuX1mWrwJEmDZvofNm+Tm8jdKSNU1efITrpfnHhSH3dm/SJF9I1of DjP3iHRAVuj+w8uQpKwrPOVIHIOGdjF89pDJwIz+aEHU9ioPgw4dG3230X+RrXpS h7Xr/qdH5x5e0h5GpFnDZUWSGYYQPjL9gAwI2RgxjUvylxGvXLbdlBhBuKMyWQwk tPApVo7EzoIQbaLkjPE0sJ7vVpiZfWGWSKV6edVZtbuP5ns8ikiwNnWpkyZFiRWT jcG1Fgfi76iBbJndz5wVVNHHbsJRU8l7GVb4r+KKXLhsrdr7l+LAT6lfZWFuR/at IojcJlOn3vwtjNuOan6YrBNLTFOMZp2Pi98Tn7KhxshI3SGfqFZ0rtbyW/GnWwnQ bd1gTJLXyGg39Xo/5tRH/dQ378MDCFmT5a+/Z8OX9VYDKWIJ4Tsv1a0OusjjkfSa gOtNUYTGhqgu4InB8ImKDAbf6b1bkSSkAKVnsHZ7PepsuS2xJSEmvF+/IYsXHJVi h0us26JcgJC3woZeQBBP =XVNg -----END PGP SIGNATURE----- Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp Pull EDAC fixes from Borislav Petkov: "A fix from Mauro to correct csrow size accounting in sysfs and a sparse fix from Stephen Hemminger." * tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: EDAC: Merge mci.mem_is_per_rank with mci.csbased amd64_edac: Correct DIMM sizes EDAC: Make sysfs functions static
This commit is contained in:
commit
1e0695cbc8
@ -2048,12 +2048,18 @@ static int init_csrows(struct mem_ctl_info *mci)
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edac_dbg(1, "MC node: %d, csrow: %d\n",
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pvt->mc_node_id, i);
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if (row_dct0)
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if (row_dct0) {
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nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
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csrow->channels[0]->dimm->nr_pages = nr_pages;
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}
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/* K8 has only one DCT */
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if (boot_cpu_data.x86 != 0xf && row_dct1)
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nr_pages += amd64_csrow_nr_pages(pvt, 1, i);
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if (boot_cpu_data.x86 != 0xf && row_dct1) {
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int row_dct1_pages = amd64_csrow_nr_pages(pvt, 1, i);
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csrow->channels[1]->dimm->nr_pages = row_dct1_pages;
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nr_pages += row_dct1_pages;
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}
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mtype = amd64_determine_memory_type(pvt, i);
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@ -2072,9 +2078,7 @@ static int init_csrows(struct mem_ctl_info *mci)
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dimm = csrow->channels[j]->dimm;
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dimm->mtype = mtype;
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dimm->edac_mode = edac_mode;
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dimm->nr_pages = nr_pages;
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}
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csrow->nr_pages = nr_pages;
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}
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return empty;
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@ -2419,7 +2423,6 @@ static int amd64_init_one_instance(struct pci_dev *F2)
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mci->pvt_info = pvt;
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mci->pdev = &pvt->F2->dev;
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mci->csbased = 1;
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setup_mci_misc_attrs(mci, fam_type);
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@ -86,7 +86,7 @@ static void edac_mc_dump_dimm(struct dimm_info *dimm, int number)
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edac_dimm_info_location(dimm, location, sizeof(location));
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edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n",
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dimm->mci->mem_is_per_rank ? "rank" : "dimm",
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dimm->mci->csbased ? "rank" : "dimm",
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number, location, dimm->csrow, dimm->cschannel);
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edac_dbg(4, " dimm = %p\n", dimm);
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edac_dbg(4, " dimm->label = '%s'\n", dimm->label);
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@ -341,7 +341,7 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num,
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memcpy(mci->layers, layers, sizeof(*layer) * n_layers);
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mci->nr_csrows = tot_csrows;
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mci->num_cschannel = tot_channels;
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mci->mem_is_per_rank = per_rank;
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mci->csbased = per_rank;
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/*
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* Alocate and fill the csrow/channels structs
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@ -1235,7 +1235,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type,
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* incrementing the compat API counters
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*/
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edac_dbg(4, "%s csrows map: (%d,%d)\n",
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mci->mem_is_per_rank ? "rank" : "dimm",
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mci->csbased ? "rank" : "dimm",
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dimm->csrow, dimm->cschannel);
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if (row == -1)
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row = dimm->csrow;
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@ -143,7 +143,7 @@ static const char *edac_caps[] = {
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* and the per-dimm/per-rank one
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*/
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#define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \
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struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
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static struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
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struct dev_ch_attribute {
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struct device_attribute attr;
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@ -180,9 +180,6 @@ static ssize_t csrow_size_show(struct device *dev,
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int i;
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u32 nr_pages = 0;
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if (csrow->mci->csbased)
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return sprintf(data, "%u\n", PAGES_TO_MiB(csrow->nr_pages));
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for (i = 0; i < csrow->nr_channels; i++)
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nr_pages += csrow->channels[i]->dimm->nr_pages;
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return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
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@ -612,7 +609,7 @@ static int edac_create_dimm_object(struct mem_ctl_info *mci,
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device_initialize(&dimm->dev);
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dimm->dev.parent = &mci->dev;
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if (mci->mem_is_per_rank)
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if (mci->csbased)
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dev_set_name(&dimm->dev, "rank%d", index);
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else
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dev_set_name(&dimm->dev, "dimm%d", index);
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@ -778,14 +775,10 @@ static ssize_t mci_size_mb_show(struct device *dev,
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for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
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struct csrow_info *csrow = mci->csrows[csrow_idx];
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if (csrow->mci->csbased) {
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total_pages += csrow->nr_pages;
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} else {
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for (j = 0; j < csrow->nr_channels; j++) {
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struct dimm_info *dimm = csrow->channels[j]->dimm;
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for (j = 0; j < csrow->nr_channels; j++) {
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struct dimm_info *dimm = csrow->channels[j]->dimm;
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total_pages += dimm->nr_pages;
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}
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total_pages += dimm->nr_pages;
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}
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}
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@ -561,7 +561,6 @@ struct csrow_info {
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u32 ue_count; /* Uncorrectable Errors for this csrow */
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u32 ce_count; /* Correctable Errors for this csrow */
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u32 nr_pages; /* combined pages count of all channels */
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struct mem_ctl_info *mci; /* the parent */
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@ -676,11 +675,11 @@ struct mem_ctl_info {
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* sees memory sticks ("dimms"), and the ones that sees memory ranks.
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* All old memory controllers enumerate memories per rank, but most
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* of the recent drivers enumerate memories per DIMM, instead.
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* When the memory controller is per rank, mem_is_per_rank is true.
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* When the memory controller is per rank, csbased is true.
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*/
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unsigned n_layers;
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struct edac_mc_layer *layers;
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bool mem_is_per_rank;
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bool csbased;
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/*
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* DIMM info. Will eventually remove the entire csrows_info some day
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@ -741,8 +740,6 @@ struct mem_ctl_info {
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u32 fake_inject_ue;
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u16 fake_inject_count;
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#endif
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__u8 csbased : 1, /* csrow-based memory controller */
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__resv : 7;
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};
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#endif
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