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phy: for 4.20-rc
*) Fix updating HSTX_TRIM tuning parameter in qcom-qusb2 PHY driver *) Fix inconsistencies between dt-bindings and the driver *) Add "Depend on HAS_IOMEM" uniphier-pcie to avoid randconfig errors Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> -----BEGIN PGP SIGNATURE----- iQJCBAABCgAsFiEEUXMr/TfP2p4suIY5Dlx4XIBNgtkFAlv30RYOHGtpc2hvbkB0 aS5jb20ACgkQDlx4XIBNgtkfLBAAm87q/wGduTGZ7MHL1br4/7QcoYe0yJ6iVYGR DXlMPGpYOoT6Lxxj4WnJOS0K/u8j41rg1rlcoPLYTXQwB6oGR/QDd+idSDDy3TAZ 2zsgOUIMGRr6W6Arz6dHU2Ae7ydB6+czJAQuUUf+Qtr6IJxcXJ1FZ4CXmqrmNcHn JLqiWxqSkvxnl1mDZ6+LzLhmaTOT9t59GDwCQrRAZGhZc4kSQE6SOPtB/FGnd47L 0ij0iSn82HuNubCK9QzWurQQ++9qBPd6ws8jWtscos1hxsEdIM05aEWQiyOrijrC aClaEpUn5gSCI2MJcUtuOqgnYkcNtzEgi4bwVlj18vGEeahjiYbmzyulquLs9mli jeBREKHQD7PHoZwdtzDDefur6e92cORzmla8VXW1AXh94mbRXQbcb0bv/+HfeUCy 4OJyg6IaPZoL8YJoHhXzvDmVZLOV1yvrVCqobMHaJMUdyXbtXl3EpplxXDGjkfw8 qi6ZKWQrQ/IbpRd+cSpOB8CsVn4sN2HbfOBA+5wMURika5sTIyr+tpARS2+nBvk1 7RK37pFIi91eTABPxG8ZBS9MlnsgvCnr/rKnnUvuRWok+nqbi2SC+dphdeVFjvZ/ q0JTxfQtVDwzZmxiGu/CN7do6FJZ/9D2uDjZvrj3/hAbXbWA8YX+A9vpaaI/rpXU 9xUoeJI= =wXaJ -----END PGP SIGNATURE----- Merge tag 'phy-for-4.20-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-linus Kishon writes: phy: for 4.20-rc *) Fix updating HSTX_TRIM tuning parameter in qcom-qusb2 PHY driver *) Fix inconsistencies between dt-bindings and the driver *) Add "Depend on HAS_IOMEM" uniphier-pcie to avoid randconfig errors Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-4.20-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: phy: qcom-qusb2: Fix HSTX_TRIM tuning with fused value for SDM845 phy: qcom-qusb2: Use HSTX_TRIM fused value as is dt-bindings: phy-qcom-qmp: Fix several mistakes from prior commits phy: uniphier-pcie: Depend on HAS_IOMEM
This commit is contained in:
Greg Kroah-Hartman
commit
1dbcd8d42c
@ -40,24 +40,36 @@ Required properties:
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"ref" for 19.2 MHz ref clk,
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"com_aux" for phy common block aux clock,
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"ref_aux" for phy reference aux clock,
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For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
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For "qcom,msm8996-qmp-pcie-phy" must contain:
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"aux", "cfg_ahb", "ref".
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For "qcom,msm8996-qmp-usb3-phy" must contain:
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"aux", "cfg_ahb", "ref".
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For "qcom,qmp-v3-usb3-phy" must contain:
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For "qcom,sdm845-qmp-usb3-phy" must contain:
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"aux", "cfg_ahb", "ref", "com_aux".
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For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
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"aux", "cfg_ahb", "ref", "com_aux".
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For "qcom,sdm845-qmp-ufs-phy" must contain:
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"ref", "ref_aux".
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- resets: a list of phandles and reset controller specifier pairs,
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one for each entry in reset-names.
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- reset-names: "phy" for reset of phy block,
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"common" for phy common block reset,
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"cfg" for phy's ahb cfg block reset (Optional).
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For "qcom,msm8996-qmp-pcie-phy" must contain:
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"phy", "common", "cfg".
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For "qcom,msm8996-qmp-usb3-phy" must contain
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"phy", "common".
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"cfg" for phy's ahb cfg block reset.
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For "qcom,ipq8074-qmp-pcie-phy" must contain:
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"phy", "common".
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"phy", "common".
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For "qcom,msm8996-qmp-pcie-phy" must contain:
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"phy", "common", "cfg".
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For "qcom,msm8996-qmp-usb3-phy" must contain
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"phy", "common".
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For "qcom,sdm845-qmp-usb3-phy" must contain:
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"phy", "common".
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For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
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"phy", "common".
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For "qcom,sdm845-qmp-ufs-phy": no resets are listed.
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- vdda-phy-supply: Phandle to a regulator supply to PHY core block.
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- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
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@ -79,9 +91,10 @@ Required properties for child node:
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- #phy-cells: must be 0
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Required properties child node of pcie and usb3 qmp phys:
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- clocks: a list of phandles and clock-specifier pairs,
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one for each entry in clock-names.
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- clock-names: Must contain following for pcie and usb qmp phys:
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- clock-names: Must contain following:
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"pipe<lane-number>" for pipe clock specific to each lane.
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- clock-output-names: Name of the PHY clock that will be the parent for
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the above pipe clock.
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@ -91,9 +104,11 @@ Required properties for child node:
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(or)
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"pcie20_phy1_pipe_clk"
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Required properties for child node of PHYs with lane reset, AKA:
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"qcom,msm8996-qmp-pcie-phy"
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- resets: a list of phandles and reset controller specifier pairs,
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one for each entry in reset-names.
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- reset-names: Must contain following for pcie qmp phys:
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- reset-names: Must contain following:
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"lane<lane-number>" for reset specific to each lane.
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Example:
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@ -231,6 +231,7 @@ static const struct qusb2_phy_cfg sdm845_phy_cfg = {
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.mask_core_ready = CORE_READY_STATUS,
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.has_pll_override = true,
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.autoresume_en = BIT(0),
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.update_tune1_with_efuse = true,
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};
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static const char * const qusb2_phy_vreg_names[] = {
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@ -402,10 +403,10 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
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/*
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* Read efuse register having TUNE2/1 parameter's high nibble.
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* If efuse register shows value as 0x0, or if we fail to find
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* a valid efuse register settings, then use default value
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* as 0xB for high nibble that we have already set while
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* configuring phy.
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* If efuse register shows value as 0x0 (indicating value is not
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* fused), or if we fail to find a valid efuse register setting,
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* then use default value for high nibble that we have already
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* set while configuring the phy.
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*/
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val = nvmem_cell_read(qphy->cell, NULL);
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if (IS_ERR(val) || !val[0]) {
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@ -415,12 +416,13 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
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/* Fused TUNE1/2 value is the higher nibble only */
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if (cfg->update_tune1_with_efuse)
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qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
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val[0] << 0x4);
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qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
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val[0] << HSTX_TRIM_SHIFT,
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HSTX_TRIM_MASK);
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else
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qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
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val[0] << 0x4);
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qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
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val[0] << HSTX_TRIM_SHIFT,
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HSTX_TRIM_MASK);
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}
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static int qusb2_phy_set_mode(struct phy *phy, enum phy_mode mode)
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@ -26,7 +26,8 @@ config PHY_UNIPHIER_USB3
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config PHY_UNIPHIER_PCIE
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tristate "Uniphier PHY driver for PCIe controller"
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depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
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depends on ARCH_UNIPHIER || COMPILE_TEST
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depends on OF && HAS_IOMEM
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default PCIE_UNIPHIER
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select GENERIC_PHY
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help
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