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drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs
The Adreno 508/509/512 GPUs are stripped versions of the Adreno 5xx found in the mid-end SoCs such as SDM630, SDM636, SDM660 and SDA variants; these SoCs are usually provided with ZAP firmwares, but they have no available GPMU. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Tested-by: Martin Botka <martin.botka1@gmail.com> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
AngeloGioacchino Del Regno
Rob Clark
parent
4340b46ad1
commit
1d832ab30c
@ -222,7 +222,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
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a5xx_preempt_trigger(gpu);
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}
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static const struct {
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static const struct adreno_five_hwcg_regs {
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u32 offset;
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u32 value;
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} a5xx_hwcg[] = {
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@ -318,16 +318,124 @@ static const struct {
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{REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
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{REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
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{REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}
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}, a50x_hwcg[] = {
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{REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
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{REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
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{REG_A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
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{REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
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{REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
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{REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
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{REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},
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{REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
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{REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
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{REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},
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{REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
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{REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
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{REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},
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{REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
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{REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
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{REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
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{REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
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{REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00FFFFF4},
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{REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
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{REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
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{REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},
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{REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},
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{REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},
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{REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},
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{REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
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{REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
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{REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},
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{REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
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{REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
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{REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
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{REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
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{REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
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{REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
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{REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
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{REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
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{REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
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{REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
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{REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
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}, a512_hwcg[] = {
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{REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
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{REG_A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},
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{REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
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{REG_A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},
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{REG_A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
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{REG_A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},
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{REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
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{REG_A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
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{REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
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{REG_A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},
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{REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
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{REG_A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
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{REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},
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{REG_A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222},
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{REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
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{REG_A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
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{REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
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{REG_A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
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{REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},
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{REG_A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777},
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{REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
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{REG_A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
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{REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
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{REG_A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
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{REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},
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{REG_A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111},
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{REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
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{REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
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{REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
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{REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
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{REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},
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{REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
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{REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
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{REG_A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
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{REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},
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{REG_A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222},
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{REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},
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{REG_A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},
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{REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},
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{REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},
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{REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
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{REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},
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{REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
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{REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},
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{REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002},
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{REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
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{REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
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{REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
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{REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
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{REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
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{REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
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{REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
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{REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
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{REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
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{REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
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{REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
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};
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void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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unsigned int i;
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const struct adreno_five_hwcg_regs *regs;
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unsigned int i, sz;
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for (i = 0; i < ARRAY_SIZE(a5xx_hwcg); i++)
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gpu_write(gpu, a5xx_hwcg[i].offset,
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state ? a5xx_hwcg[i].value : 0);
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if (adreno_is_a508(adreno_gpu)) {
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regs = a50x_hwcg;
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sz = ARRAY_SIZE(a50x_hwcg);
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} else if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu)) {
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regs = a512_hwcg;
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sz = ARRAY_SIZE(a512_hwcg);
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} else {
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regs = a5xx_hwcg;
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sz = ARRAY_SIZE(a5xx_hwcg);
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}
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for (i = 0; i < sz; i++)
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gpu_write(gpu, regs[i].offset,
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state ? regs[i].value : 0);
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if (adreno_is_a540(adreno_gpu)) {
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gpu_write(gpu, REG_A5XX_RBBM_CLOCK_DELAY_GPMU, state ? 0x00000770 : 0);
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@ -538,11 +646,13 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
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u32 regbit;
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int ret;
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gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);
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if (adreno_is_a540(adreno_gpu))
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if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu) ||
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adreno_is_a540(adreno_gpu))
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gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
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/* Make all blocks contribute to the GPU BUSY perf counter */
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@ -604,22 +714,29 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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0x00100000 + adreno_gpu->gmem - 1);
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gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000);
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if (adreno_is_a510(adreno_gpu)) {
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if (adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu)) {
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gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x20);
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gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20);
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if (adreno_is_a508(adreno_gpu))
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gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
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else
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gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20);
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gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030);
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gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A);
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} else {
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gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40);
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if (adreno_is_a530(adreno_gpu))
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gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40);
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if (adreno_is_a540(adreno_gpu))
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else
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gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
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gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060);
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gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16);
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}
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if (adreno_is_a510(adreno_gpu))
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if (adreno_is_a508(adreno_gpu))
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gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
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(0x100 << 11 | 0x100 << 22));
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else if (adreno_is_a509(adreno_gpu) || adreno_is_a510(adreno_gpu) ||
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adreno_is_a512(adreno_gpu))
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gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
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(0x200 << 11 | 0x200 << 22));
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else
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@ -629,6 +746,14 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI)
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gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8));
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/*
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* Disable the RB sampler datapath DP2 clock gating optimization
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* for 1-SP GPUs, as it is enabled by default.
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*/
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if (adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) ||
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adreno_is_a512(adreno_gpu))
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gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9));
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/* Enable USE_RETENTION_FLOPS */
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gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000);
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@ -654,10 +779,17 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F);
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/* Set the highest bank bit */
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gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, 2 << 7);
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gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, 2 << 1);
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if (adreno_is_a540(adreno_gpu))
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gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, 2);
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regbit = 2;
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else
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regbit = 1;
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gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, regbit << 7);
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gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, regbit << 1);
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if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu) ||
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adreno_is_a540(adreno_gpu))
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gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, regbit);
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/* Protect registers from the CP */
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gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x00000007);
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@ -694,7 +826,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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/* UCHE */
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gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16));
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if (adreno_is_a530(adreno_gpu) || adreno_is_a510(adreno_gpu))
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if (adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) ||
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adreno_is_a510(adreno_gpu) || adreno_is_a512(adreno_gpu) ||
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adreno_is_a530(adreno_gpu))
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gpu_write(gpu, REG_A5XX_CP_PROTECT(17),
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ADRENO_PROTECT_RW(0x10000, 0x8000));
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@ -736,7 +870,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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if (ret)
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return ret;
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if (!adreno_is_a510(adreno_gpu))
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if (!(adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) ||
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adreno_is_a510(adreno_gpu) || adreno_is_a512(adreno_gpu)))
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a5xx_gpmu_ucode_init(gpu);
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ret = a5xx_ucode_init(gpu);
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@ -1169,7 +1304,8 @@ static int a5xx_pm_resume(struct msm_gpu *gpu)
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if (ret)
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return ret;
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if (adreno_is_a510(adreno_gpu)) {
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/* Adreno 508, 509, 510, 512 needs manual RBBM sus/res control */
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if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu))) {
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/* Halt the sp_input_clk at HM level */
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gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0x00000055);
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a5xx_set_hwcg(gpu, true);
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@ -1211,8 +1347,8 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
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u32 mask = 0xf;
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int i, ret;
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/* A510 has 3 XIN ports in VBIF */
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if (adreno_is_a510(adreno_gpu))
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/* A508, A510 have 3 XIN ports in VBIF */
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if (adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu))
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mask = 0x7;
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/* Clear the VBIF pipe before shutting down */
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@ -298,7 +298,7 @@ int a5xx_power_init(struct msm_gpu *gpu)
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int ret;
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/* Not all A5xx chips have a GPMU */
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if (adreno_is_a510(adreno_gpu))
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if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu)))
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return 0;
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/* Set up the limits management */
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@ -330,7 +330,7 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu)
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unsigned int *data, *ptr, *cmds;
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unsigned int cmds_size;
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if (adreno_is_a510(adreno_gpu))
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if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu)))
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return;
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if (a5xx_gpu->gpmu_bo)
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@ -133,6 +133,41 @@ static const struct adreno_info gpulist[] = {
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.gmem = (SZ_1M + SZ_512K),
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a4xx_gpu_init,
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}, {
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.rev = ADRENO_REV(5, 0, 8, ANY_ID),
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.revn = 508,
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.name = "A508",
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.fw = {
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[ADRENO_FW_PM4] = "a530_pm4.fw",
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[ADRENO_FW_PFP] = "a530_pfp.fw",
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},
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.gmem = (SZ_128K + SZ_8K),
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/*
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* Increase inactive period to 250 to avoid bouncing
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* the GDSC which appears to make it grumpy
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*/
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.inactive_period = 250,
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.quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
|
||||
.init = a5xx_gpu_init,
|
||||
.zapfw = "a508_zap.mdt",
|
||||
}, {
|
||||
.rev = ADRENO_REV(5, 0, 9, ANY_ID),
|
||||
.revn = 509,
|
||||
.name = "A509",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a530_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a530_pfp.fw",
|
||||
},
|
||||
.gmem = (SZ_256K + SZ_16K),
|
||||
/*
|
||||
* Increase inactive period to 250 to avoid bouncing
|
||||
* the GDSC which appears to make it grumpy
|
||||
*/
|
||||
.inactive_period = 250,
|
||||
.quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
|
||||
.init = a5xx_gpu_init,
|
||||
/* Adreno 509 uses the same ZAP as 512 */
|
||||
.zapfw = "a512_zap.mdt",
|
||||
}, {
|
||||
.rev = ADRENO_REV(5, 1, 0, ANY_ID),
|
||||
.revn = 510,
|
||||
@ -148,6 +183,23 @@ static const struct adreno_info gpulist[] = {
|
||||
*/
|
||||
.inactive_period = 250,
|
||||
.init = a5xx_gpu_init,
|
||||
}, {
|
||||
.rev = ADRENO_REV(5, 1, 2, ANY_ID),
|
||||
.revn = 512,
|
||||
.name = "A512",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a530_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a530_pfp.fw",
|
||||
},
|
||||
.gmem = (SZ_256K + SZ_16K),
|
||||
/*
|
||||
* Increase inactive period to 250 to avoid bouncing
|
||||
* the GDSC which appears to make it grumpy
|
||||
*/
|
||||
.inactive_period = 250,
|
||||
.quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
|
||||
.init = a5xx_gpu_init,
|
||||
.zapfw = "a512_zap.mdt",
|
||||
}, {
|
||||
.rev = ADRENO_REV(5, 3, 0, 2),
|
||||
.revn = 530,
|
||||
|
||||
@ -197,11 +197,26 @@ static inline int adreno_is_a430(struct adreno_gpu *gpu)
|
||||
return gpu->revn == 430;
|
||||
}
|
||||
|
||||
static inline int adreno_is_a508(struct adreno_gpu *gpu)
|
||||
{
|
||||
return gpu->revn == 508;
|
||||
}
|
||||
|
||||
static inline int adreno_is_a509(struct adreno_gpu *gpu)
|
||||
{
|
||||
return gpu->revn == 509;
|
||||
}
|
||||
|
||||
static inline int adreno_is_a510(struct adreno_gpu *gpu)
|
||||
{
|
||||
return gpu->revn == 510;
|
||||
}
|
||||
|
||||
static inline int adreno_is_a512(struct adreno_gpu *gpu)
|
||||
{
|
||||
return gpu->revn == 512;
|
||||
}
|
||||
|
||||
static inline int adreno_is_a530(struct adreno_gpu *gpu)
|
||||
{
|
||||
return gpu->revn == 530;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user