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SuperH updates for 3.5-rc1 merge window

Browse Source 
- New CPUs: SH7734 (SH-4A), SH7264 and SH7269 (SH-2A)
 - New boards: RSK2+SH7264, RSK2+SH7269
 - Unbreaking kgdb for SMP
 - Consolidation of _32/_64 page fault handling.
 - watchdog and legacy DMA chainsawing, part 1
 - Conversion to evt2irq() hwirq lookup, to support relocation
   of vectored IRQs for irqdomains.
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Merge tag 'sh-for-linus' of git://github.com/pmundt/linux-sh

Pull SuperH updates from Paul Mundt:
 - New CPUs: SH7734 (SH-4A), SH7264 and SH7269 (SH-2A)
 - New boards: RSK2+SH7264, RSK2+SH7269
 - Unbreaking kgdb for SMP
 - Consolidation of _32/_64 page fault handling.
 - watchdog and legacy DMA chainsawing, part 1
 - Conversion to evt2irq() hwirq lookup, to support relocation of
   vectored IRQs for irqdomains.

* tag 'sh-for-linus' of git://github.com/pmundt/linux-sh: (98 commits)
  sh: intc: Kill off special reservation interface.
  sh: Enable PIO API for hp6xx and se770x.
  sh: Kill off machvec IRQ hinting.
  sh: dma: More legacy cpu dma chainsawing.
  sh: Kill off MAX_DMA_ADDRESS leftovers.
  sh: Tidy up some of the cpu legacy dma header mess.
  sh: Move sh4a dma header from cpu-sh4 to cpu-sh4a.
  sh64: Fix up vmalloc fault range check.
  Revert "sh: Ensure fixmap and store queue space can co-exist."
  serial: sh-sci: Fix for port types without BRI interrupts.
  sh: legacy PCI evt2irq migration.
  sh: cpu dma evt2irq migration.
  sh: sh7763rdp evt2irq migration.
  sh: sdk7780 evt2irq migration.
  sh: migor evt2irq migration.
  sh: landisk evt2irq migration.
  sh: kfr2r09 evt2irq migration.
  sh: ecovec24 evt2irq migration.
  sh: ap325rxa evt2irq migration.
  sh: urquell evt2irq migration.
  ...
This commit is contained in:
Linus Torvalds 2012-05-23 09:00:40 -07:00
commit 1d767cae4d
152 changed files with 13244 additions and 2206 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -6573,7 +6573,7 @@ M: Paul Mundt <lethal@linux-sh.org>
L: linux-sh@vger.kernel.org
W: http://www.linux-sh.org
Q: http://patchwork.kernel.org/project/linux-sh/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6.git sh-latest
T: git git://github.com/pmundt/linux-sh.git sh-latest
S: Supported
F: Documentation/sh/
F: arch/sh/

45
arch/sh/Kconfig
View File

@ -155,7 +155,8 @@ config ARCH_HAS_DEFAULT_IDLE
config NO_IOPORT
def_bool !PCI
depends on !SH_CAYMAN && !SH_SH4202_MICRODEV && !SH_SHMIN
depends on !SH_CAYMAN && !SH_SH4202_MICRODEV && !SH_SHMIN && \
!SH_HP6XX && !SH_SOLUTION_ENGINE
config IO_TRAPPED
bool
@ -286,6 +287,20 @@ config CPU_SUBTYPE_SH7263
select SYS_SUPPORTS_CMT
select SYS_SUPPORTS_MTU2
config CPU_SUBTYPE_SH7264
bool "Support SH7264 processor"
select CPU_SH2A
select CPU_HAS_FPU
select SYS_SUPPORTS_CMT
select SYS_SUPPORTS_MTU2
config CPU_SUBTYPE_SH7269
bool "Support SH7269 processor"
select CPU_SH2A
select CPU_HAS_FPU
select SYS_SUPPORTS_CMT
select SYS_SUPPORTS_MTU2
config CPU_SUBTYPE_MXG
bool "Support MX-G processor"
select CPU_SH2A
@ -425,6 +440,16 @@ config CPU_SUBTYPE_SH7724
help
Select SH7724 if you have an SH-MobileR2R CPU.
config CPU_SUBTYPE_SH7734
bool "Support SH7734 processor"
select CPU_SH4A
select CPU_SHX2
select ARCH_WANT_OPTIONAL_GPIOLIB
select USB_ARCH_HAS_OHCI
select USB_ARCH_HAS_EHCI
help
Select SH7734 if you have a SH4A SH7734 CPU.
config CPU_SUBTYPE_SH7757
bool "Support SH7757 processor"
select CPU_SH4A
@ -582,7 +607,9 @@ config SH_CLK_CPG
config SH_CLK_CPG_LEGACY
depends on SH_CLK_CPG
def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
!CPU_SHX3 && !CPU_SUBTYPE_SH7757
!CPU_SHX3 && !CPU_SUBTYPE_SH7757 && \
!CPU_SUBTYPE_SH7734 && !CPU_SUBTYPE_SH7264 && \
!CPU_SUBTYPE_SH7269
source "kernel/time/Kconfig"
@ -683,6 +710,20 @@ config SECCOMP
If unsure, say N.
config CC_STACKPROTECTOR
bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
depends on SUPERH32 && EXPERIMENTAL
help
This option turns on the -fstack-protector GCC feature. This
feature puts, at the beginning of functions, a canary value on
the stack just before the return address, and validates
the value just before actually returning. Stack based buffer
overflows (that need to overwrite this return address) now also
overwrite the canary, which gets detected and the attack is then
neutralized via a kernel panic.
This feature requires gcc version 4.2 or above.
config SMP
bool "Symmetric multi-processing support"
depends on SYS_SUPPORTS_SMP

4
arch/sh/Makefile
View File

@ -199,6 +199,10 @@ ifeq ($(CONFIG_DWARF_UNWINDER),y)
KBUILD_CFLAGS += -fasynchronous-unwind-tables
endif
ifeq ($(CONFIG_CC_STACKPROTECTOR),y)
KBUILD_CFLAGS += -fstack-protector
endif
libs-$(CONFIG_SUPERH32) := arch/sh/lib/ $(libs-y)
libs-$(CONFIG_SUPERH64) := arch/sh/lib64/ $(libs-y)

7
arch/sh/boards/Kconfig
View File

@ -133,7 +133,8 @@ config SH_RTS7751R2D
config SH_RSK
bool "Renesas Starter Kit"
depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203
depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 || \
CPU_SUBTYPE_SH7264 || CPU_SUBTYPE_SH7269
help
Select this option if configuring for any of the RSK+ MCU
evaluation platforms.
@ -338,8 +339,6 @@ config SH_APSH4AD0A
help
Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A.
endmenu
source "arch/sh/boards/mach-r2d/Kconfig"
source "arch/sh/boards/mach-highlander/Kconfig"
source "arch/sh/boards/mach-sdk7780/Kconfig"
@ -359,3 +358,5 @@ config SH_MAGIC_PANEL_R2_VERSION
endmenu
endif
endmenu

4
arch/sh/boards/board-edosk7705.c
View File

@ -13,6 +13,7 @@
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/smc91x.h>
#include <linux/sh_intc.h>
#include <asm/machvec.h>
#include <asm/sizes.h>
@ -20,7 +21,7 @@
#define SMC_IO_OFFSET 0x300
#define SMC_IOADDR (SMC_IOBASE + SMC_IO_OFFSET)
#define ETHERNET_IRQ 0x09
#define ETHERNET_IRQ evt2irq(0x320)
static void __init sh_edosk7705_init_irq(void)
{
@ -73,6 +74,5 @@ device_initcall(init_edosk7705_devices);
*/
static struct sh_machine_vector mv_edosk7705 __initmv = {
.mv_name = "EDOSK7705",
.mv_nr_irqs = 80,
.mv_init_irq = sh_edosk7705_init_irq,
};

16
arch/sh/boards/board-edosk7760.c
View File

@ -23,6 +23,7 @@
#include <linux/platform_device.h>
#include <linux/smc91x.h>
#include <linux/interrupt.h>
#include <linux/sh_intc.h>
#include <linux/i2c.h>
#include <linux/mtd/physmap.h>
#include <asm/machvec.h>
@ -40,8 +41,6 @@
#define SMC_IO_OFFSET 0x300
#define SMC_IOADDR (SMC_IOBASE + SMC_IO_OFFSET)
#define ETHERNET_IRQ 5
/* NOR flash */
static struct mtd_partition edosk7760_nor_flash_partitions[] = {
{
@ -99,8 +98,8 @@ static struct resource sh7760_i2c1_res[] = {
.end = SH7760_I2C1_MMIOEND,
.flags = IORESOURCE_MEM,
},{
.start = SH7760_I2C1_IRQ,
.end = SH7760_I2C1_IRQ,
.start = evt2irq(0x9e0),
.end = evt2irq(0x9e0),
.flags = IORESOURCE_IRQ,
},
};
@ -122,8 +121,8 @@ static struct resource sh7760_i2c0_res[] = {
.end = SH7760_I2C0_MMIOEND,
.flags = IORESOURCE_MEM,
}, {
.start = SH7760_I2C0_IRQ,
.end = SH7760_I2C0_IRQ,
.start = evt2irq(0x9c0),
.end = evt2irq(0x9c0),
.flags = IORESOURCE_IRQ,
},
};
@ -150,8 +149,8 @@ static struct resource smc91x_res[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = ETHERNET_IRQ,
.end = ETHERNET_IRQ,
.start = evt2irq(0x2a0),
.end = evt2irq(0x2a0),
.flags = IORESOURCE_IRQ ,
}
};
@ -189,5 +188,4 @@ device_initcall(init_edosk7760_devices);
*/
struct sh_machine_vector mv_edosk7760 __initmv = {
.mv_name = "EDOSK7760",
.mv_nr_irqs = 128,
};

3
arch/sh/boards/board-espt.c
View File

@ -14,6 +14,7 @@
#include <linux/mtd/physmap.h>
#include <linux/io.h>
#include <linux/sh_eth.h>
#include <linux/sh_intc.h>
#include <asm/machvec.h>
#include <asm/sizes.h>
@ -71,7 +72,7 @@ static struct resource sh_eth_resources[] = {
.flags = IORESOURCE_MEM,
}, {
.start = 57, /* irq number */
.start = evt2irq(0x920), /* irq number */
.flags = IORESOURCE_IRQ,
},
};

25
arch/sh/boards/board-magicpanelr2.c
View File

@ -19,6 +19,7 @@
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/map.h>
#include <linux/sh_intc.h>
#include <mach/magicpanelr2.h>
#include <asm/heartbeat.h>
#include <cpu/sh7720.h>
@ -245,8 +246,8 @@ static struct resource smsc911x_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 35,
.end = 35,
.start = evt2irq(0x660),
.end = evt2irq(0x660),
.flags = IORESOURCE_IRQ,
},
};
@ -358,17 +359,17 @@ static void __init init_mpr2_IRQ(void)
{
plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */
irq_set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */
irq_set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */
irq_set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */
irq_set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */
irq_set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */
irq_set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */
irq_set_irq_type(evt2irq(0x600), IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */
irq_set_irq_type(evt2irq(0x620), IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */
irq_set_irq_type(evt2irq(0x640), IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */
irq_set_irq_type(evt2irq(0x660), IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */
irq_set_irq_type(evt2irq(0x680), IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */
irq_set_irq_type(evt2irq(0x6a0), IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */
intc_set_priority(32, 13); /* IRQ0 CAN1 */
intc_set_priority(33, 13); /* IRQ0 CAN2 */
intc_set_priority(34, 13); /* IRQ0 CAN3 */
intc_set_priority(35, 6); /* IRQ3 SMSC9115 */
intc_set_priority(evt2irq(0x600), 13); /* IRQ0 CAN1 */
intc_set_priority(evt2irq(0x620), 13); /* IRQ0 CAN2 */
intc_set_priority(evt2irq(0x640), 13); /* IRQ0 CAN3 */
intc_set_priority(evt2irq(0x660), 6); /* IRQ3 SMSC9115 */
}
/*

1
arch/sh/boards/board-polaris.c
View File

@ -141,6 +141,5 @@ static void __init init_polaris_irq(void)
static struct sh_machine_vector mv_polaris __initmv = {
.mv_name = "Polaris",
.mv_nr_irqs = 61,
.mv_init_irq = init_polaris_irq,
};

1
arch/sh/boards/board-secureedge5410.c
View File

@ -71,6 +71,5 @@ static void __init init_snapgear_IRQ(void)
*/
static struct sh_machine_vector mv_snapgear __initmv = {
.mv_name = "SnapGear SecureEdge5410",
.mv_nr_irqs = 72,
.mv_init_irq = init_snapgear_IRQ,
};

27
arch/sh/boards/board-sh7757lcr.c
View File

@ -19,6 +19,7 @@
#include <linux/mmc/sh_mmcif.h>
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/sh_eth.h>
#include <linux/sh_intc.h>
#include <linux/usb/renesas_usbhs.h>
#include <cpu/sh7757.h>
#include <asm/heartbeat.h>
@ -65,8 +66,8 @@ static struct resource sh_eth0_resources[] = {
.end = 0xfef001ff,
.flags = IORESOURCE_MEM,
}, {
.start = 84,
.end = 84,
.start = evt2irq(0xc80),
.end = evt2irq(0xc80),
.flags = IORESOURCE_IRQ,
},
};
@ -94,8 +95,8 @@ static struct resource sh_eth1_resources[] = {
.end = 0xfef009ff,
.flags = IORESOURCE_MEM,
}, {
.start = 84,
.end = 84,
.start = evt2irq(0xc80),
.end = evt2irq(0xc80),
.flags = IORESOURCE_IRQ,
},
};
@ -139,8 +140,8 @@ static struct resource sh_eth_giga0_resources[] = {
.end = 0xfee01fff,
.flags = IORESOURCE_MEM,
}, {
.start = 315,
.end = 315,
.start = evt2irq(0x2960),
.end = evt2irq(0x2960),
.flags = IORESOURCE_IRQ,
},
};
@ -174,8 +175,8 @@ static struct resource sh_eth_giga1_resources[] = {
.end = 0xfee01fff,
.flags = IORESOURCE_MEM,
}, {
.start = 316,
.end = 316,
.start = evt2irq(0x2980),
.end = evt2irq(0x2980),
.flags = IORESOURCE_IRQ,
},
};
@ -206,11 +207,11 @@ static struct resource sh_mmcif_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 211,
.start = evt2irq(0x1c60),
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = 212,
.start = evt2irq(0x1c80),
.flags = IORESOURCE_IRQ,
},
};
@ -248,7 +249,7 @@ static struct resource sdhi_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 20,
.start = evt2irq(0x480),
.flags = IORESOURCE_IRQ,
},
};
@ -284,8 +285,8 @@ static struct resource usb0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 50,
.end = 50,
.start = evt2irq(0x840),
.end = evt2irq(0x840),
.flags = IORESOURCE_IRQ,
},
};

15
arch/sh/boards/board-sh7785lcr.c
View File

@ -20,6 +20,7 @@
#include <linux/i2c-pca-platform.h>
#include <linux/i2c-algo-pca.h>
#include <linux/usb/r8a66597.h>
#include <linux/sh_intc.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/clk.h>
@ -105,8 +106,8 @@ static struct resource r8a66597_usb_host_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 2,
.end = 2,
.start = evt2irq(0x240),
.end = evt2irq(0x240),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
@ -135,7 +136,7 @@ static struct resource sm501_resources[] = {
.flags = IORESOURCE_MEM,
},
[2] = {
.start = 10,
.start = evt2irq(0x340),
.flags = IORESOURCE_IRQ,
},
};
@ -223,8 +224,8 @@ static struct resource i2c_proto_resources[] = {
.flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
},
[1] = {
.start = 12,
.end = 12,
.start = evt2irq(0x380),
.end = evt2irq(0x380),
.flags = IORESOURCE_IRQ,
},
};
@ -236,8 +237,8 @@ static struct resource i2c_resources[] = {
.flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
},
[1] = {
.start = 12,
.end = 12,
.start = evt2irq(0x380),
.end = evt2irq(0x380),
.flags = IORESOURCE_IRQ,
},
};

3
arch/sh/boards/board-urquell.c
View File

@ -20,6 +20,7 @@
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/sh_intc.h>
#include <mach/urquell.h>
#include <cpu/sh7786.h>
#include <asm/heartbeat.h>
@ -78,7 +79,7 @@ static struct resource smc91x_eth_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 11,
.start = evt2irq(0x360),
.flags = IORESOURCE_IRQ,
},
};

15
arch/sh/boards/mach-ap325rxa/setup.c
View File

@ -23,6 +23,7 @@
#include <linux/smsc911x.h>
#include <linux/gpio.h>
#include <linux/videodev2.h>
#include <linux/sh_intc.h>
#include <media/ov772x.h>
#include <media/soc_camera.h>
#include <media/soc_camera_platform.h>
@ -47,8 +48,8 @@ static struct resource smsc9118_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 35,
.end = 35,
.start = evt2irq(0x660),
.end = evt2irq(0x660),
.flags = IORESOURCE_IRQ,
}
};
@ -166,7 +167,7 @@ static int ap320_wvga_set_brightness(int brightness)
__raw_writew(0, FPGA_BKLREG);
gpio_set_value(GPIO_PTS3, 1);
}
return 0;
}
@ -236,7 +237,7 @@ static struct resource lcdc_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 28,
.start = evt2irq(0x580),
.flags = IORESOURCE_IRQ,
},
};
@ -404,7 +405,7 @@ static struct resource ceu_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 52,
.start = evt2irq(0x880),
.flags = IORESOURCE_IRQ,
},
[2] = {
@ -430,7 +431,7 @@ static struct resource sdhi0_cn3_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 100,
.start = evt2irq(0xe80),
.flags = IORESOURCE_IRQ,
},
};
@ -457,7 +458,7 @@ static struct resource sdhi1_cn7_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 23,
.start = evt2irq(0x4e0),
.flags = IORESOURCE_IRQ,
},
};

1
arch/sh/boards/mach-cayman/setup.c
View File

@ -181,7 +181,6 @@ extern void init_cayman_irq(void);
static struct sh_machine_vector mv_cayman __initmv = {
.mv_name = "Hitachi Cayman",
.mv_nr_irqs = 64,
.mv_ioport_map = cayman_ioport_map,
.mv_init_irq = init_cayman_irq,
};

44
arch/sh/boards/mach-ecovec24/setup.c
View File

@ -29,6 +29,7 @@
#include <linux/input.h>
#include <linux/input/sh_keysc.h>
#include <linux/sh_eth.h>
#include <linux/sh_intc.h>
#include <linux/videodev2.h>
#include <video/sh_mobile_lcdc.h>
#include <sound/sh_fsi.h>
@ -137,7 +138,7 @@ static struct resource sh_eth_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 91,
.start = evt2irq(0xd60),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
@ -178,8 +179,8 @@ static struct resource usb0_host_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 65,
.end = 65,
.start = evt2irq(0xa20),
.end = evt2irq(0xa20),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
@ -214,8 +215,8 @@ static struct resource usb1_common_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 66,
.end = 66,
.start = evt2irq(0xa40),
.end = evt2irq(0xa40),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
@ -261,8 +262,8 @@ static struct resource usbhs_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 66,
.end = 66,
.start = evt2irq(0xa40),
.end = evt2irq(0xa40),
.flags = IORESOURCE_IRQ,
},
};
@ -348,7 +349,7 @@ static struct resource lcdc_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 106,
.start = evt2irq(0xf40),
.flags = IORESOURCE_IRQ,
},
};
@ -375,7 +376,7 @@ static struct resource ceu0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 52,
.start = evt2irq(0x880),
.flags = IORESOURCE_IRQ,
},
[2] = {
@ -406,7 +407,7 @@ static struct resource ceu1_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 63,
.start = evt2irq(0x9e0),
.flags = IORESOURCE_IRQ,
},
[2] = {
@ -437,7 +438,7 @@ static struct i2c_board_info i2c1_devices[] = {
},
{
I2C_BOARD_INFO("lis3lv02d", 0x1c),
.irq = 33,
.irq = evt2irq(0x620),
}
};
@ -463,7 +464,7 @@ static struct resource keysc_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 79,
.start = evt2irq(0xbe0),
.flags = IORESOURCE_IRQ,
},
};
@ -479,7 +480,8 @@ static struct platform_device keysc_device = {
};
/* TouchScreen */
#define IRQ0 32
#define IRQ0 evt2irq(0x600)
static int ts_get_pendown_state(void)
{
int val = 0;
@ -544,7 +546,7 @@ static struct resource sdhi0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 100,
.start = evt2irq(0xe80),
.flags = IORESOURCE_IRQ,
},
};
@ -588,7 +590,7 @@ static struct resource sdhi1_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 23,
.start = evt2irq(0x4e0),
.flags = IORESOURCE_IRQ,
},
};
@ -653,7 +655,7 @@ static struct resource msiof0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 84,
.start = evt2irq(0xc80),
.flags = IORESOURCE_IRQ,
},
};
@ -794,7 +796,7 @@ static struct resource fsi_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 108,
.start = evt2irq(0xf80),
.flags = IORESOURCE_IRQ,
},
};
@ -818,7 +820,7 @@ static struct resource irda_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 20,
.start = evt2irq(0x480),
.flags = IORESOURCE_IRQ,
},
};
@ -855,7 +857,7 @@ static struct resource sh_vou_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 55,
.start = evt2irq(0x8e0),
.flags = IORESOURCE_IRQ,
},
};
@ -891,12 +893,12 @@ static struct resource sh_mmcif_resources[] = {
},
[1] = {
/* MMC2I */
.start = 29,
.start = evt2irq(0x5a0),
.flags = IORESOURCE_IRQ,
},
[2] = {
/* MMC3I */
.start = 30,
.start = evt2irq(0x5c0),
.flags = IORESOURCE_IRQ,
},
};

5
arch/sh/boards/mach-hp6xx/setup.c
View File

@ -13,6 +13,7 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/sh_intc.h>
#include <sound/sh_dac_audio.h>
#include <asm/hd64461.h>
#include <asm/io.h>
@ -35,7 +36,7 @@ static struct resource cf_ide_resources[] = {
.flags = IORESOURCE_MEM,
},
[2] = {
.start = 77,
.start = evt2irq(0xba0),
.flags = IORESOURCE_IRQ,
},
};
@ -168,8 +169,6 @@ device_initcall(hp6xx_devices_setup);
static struct sh_machine_vector mv_hp6xx __initmv = {
.mv_name = "hp6xx",
.mv_setup = hp6xx_setup,
/* IRQ's : CPU(64) + CCHIP(16) + FREE_TO_USE(6) */
.mv_nr_irqs = HD64461_IRQBASE + HD64461_IRQ_NUM + 6,
/* Enable IRQ0 -> IRQ3 in IRQ_MODE */
.mv_init_irq = hp6xx_init_irq,
};

15
arch/sh/boards/mach-kfr2r09/setup.c
View File

@ -23,6 +23,7 @@
#include <linux/i2c.h>
#include <linux/usb/r8a66597.h>
#include <linux/videodev2.h>
#include <linux/sh_intc.h>
#include <media/rj54n1cb0c.h>
#include <media/soc_camera.h>
#include <media/sh_mobile_ceu.h>
@ -110,7 +111,7 @@ static struct resource kfr2r09_sh_keysc_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 79,
.start = evt2irq(0xbe0),
.flags = IORESOURCE_IRQ,
},
};
@ -175,7 +176,7 @@ static struct resource kfr2r09_sh_lcdc_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 106,
.start = evt2irq(0xf40),
.flags = IORESOURCE_IRQ,
},
};
@ -200,8 +201,8 @@ static struct resource kfr2r09_usb0_gadget_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 65,
.end = 65,
.start = evtirq(0xa20),
.end = evtirq(0xa20),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
@ -230,8 +231,8 @@ static struct resource kfr2r09_ceu_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 52,
.end = 52,
.start = evt2irq(0x880),
.end = evt2irq(0x880),
.flags = IORESOURCE_IRQ,
},
[2] = {
@ -348,7 +349,7 @@ static struct resource kfr2r09_sh_sdhi0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 100,
.start = evt2irq(0xe80),
.flags = IORESOURCE_IRQ,
},
};

1
arch/sh/boards/mach-lboxre2/setup.c
View File

@ -79,6 +79,5 @@ device_initcall(lboxre2_devices_setup);
*/
static struct sh_machine_vector mv_lboxre2 __initmv = {
.mv_name = "L-BOX RE2",
.mv_nr_irqs = 72,
.mv_init_irq = init_lboxre2_IRQ,
};

1
arch/sh/boards/mach-microdev/setup.c
View File

@ -194,7 +194,6 @@ device_initcall(microdev_devices_setup);
*/
static struct sh_machine_vector mv_sh4202_microdev __initmv = {
.mv_name = "SH4-202 MicroDev",
.mv_nr_irqs = 72,
.mv_ioport_map = microdev_ioport_map,
.mv_init_irq = init_microdev_irq,
};

13
arch/sh/boards/mach-migor/setup.c
View File

@ -22,6 +22,7 @@
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/videodev2.h>
#include <linux/sh_intc.h>
#include <video/sh_mobile_lcdc.h>
#include <media/sh_mobile_ceu.h>
#include <media/ov772x.h>
@ -54,7 +55,7 @@ static struct resource smc91x_eth_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 32, /* IRQ0 */
.start = evt2irq(0x600), /* IRQ0 */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
@ -88,7 +89,7 @@ static struct resource sh_keysc_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 79,
.start = evt2irq(0xbe0),
.flags = IORESOURCE_IRQ,
},
};
@ -285,7 +286,7 @@ static struct resource migor_lcdc_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 28,
.start = evt2irq(0x580),
.flags = IORESOURCE_IRQ,
},
};
@ -368,7 +369,7 @@ static struct resource migor_ceu_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 52,
.start = evt2irq(0x880),
.flags = IORESOURCE_IRQ,
},
[2] = {
@ -394,7 +395,7 @@ static struct resource sdhi_cn9_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 100,
.start = evt2irq(0xe80),
.flags = IORESOURCE_IRQ,
},
};
@ -420,7 +421,7 @@ static struct i2c_board_info migor_i2c_devices[] = {
},
{
I2C_BOARD_INFO("migor_ts", 0x51),
.irq = 38, /* IRQ6 */
.irq = evt2irq(0x6c0), /* IRQ6 */
},
{
I2C_BOARD_INFO("wm8978", 0x1a),

10
arch/sh/boards/mach-rsk/Kconfig
View File

@ -13,6 +13,16 @@ config SH_RSK7203
select ARCH_REQUIRE_GPIOLIB
depends on CPU_SUBTYPE_SH7203
config SH_RSK7264
bool "RSK2+SH7264"
select ARCH_REQUIRE_GPIOLIB
depends on CPU_SUBTYPE_SH7264
config SH_RSK7269
bool "RSK2+SH7269"
select ARCH_REQUIRE_GPIOLIB
depends on CPU_SUBTYPE_SH7269
endchoice
endif

2
arch/sh/boards/mach-rsk/Makefile
View File

@ -1,2 +1,4 @@
obj-y := setup.o
obj-$(CONFIG_SH_RSK7203) += devices-rsk7203.o
obj-$(CONFIG_SH_RSK7264) += devices-rsk7264.o
obj-$(CONFIG_SH_RSK7269) += devices-rsk7269.o

58
arch/sh/boards/mach-rsk/devices-rsk7264.c Normal file
View File

@ -0,0 +1,58 @@
/*
* RSK+SH7264 Support.
*
* Copyright (C) 2012 Renesas Electronics Europe
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/input.h>
#include <linux/smsc911x.h>
#include <asm/machvec.h>
#include <asm/io.h>
static struct smsc911x_platform_config smsc911x_config = {
.phy_interface = PHY_INTERFACE_MODE_MII,
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
.flags = SMSC911X_USE_16BIT | SMSC911X_SWAP_FIFO,
};
static struct resource smsc911x_resources[] = {
[0] = {
.start = 0x28000000,
.end = 0x280000ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 65,
.end = 65,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smsc911x_device = {
.name = "smsc911x",
.id = -1,
.num_resources = ARRAY_SIZE(smsc911x_resources),
.resource = smsc911x_resources,
.dev = {
.platform_data = &smsc911x_config,
},
};
static struct platform_device *rsk7264_devices[] __initdata = {
&smsc911x_device,
};
static int __init rsk7264_devices_setup(void)
{
return platform_add_devices(rsk7264_devices,
ARRAY_SIZE(rsk7264_devices));
}
device_initcall(rsk7264_devices_setup);

60
arch/sh/boards/mach-rsk/devices-rsk7269.c Normal file
View File

@ -0,0 +1,60 @@
/*
* RSK+SH7269 Support
*
* Copyright (C) 2012 Renesas Electronics Europe Ltd
* Copyright (C) 2012 Phil Edworthy
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/input.h>
#include <linux/smsc911x.h>
#include <linux/gpio.h>
#include <asm/machvec.h>
#include <asm/io.h>
static struct smsc911x_platform_config smsc911x_config = {
.phy_interface = PHY_INTERFACE_MODE_MII,
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
.flags = SMSC911X_USE_16BIT | SMSC911X_SWAP_FIFO,
};
static struct resource smsc911x_resources[] = {
[0] = {
.start = 0x24000000,
.end = 0x240000ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 85,
.end = 85,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smsc911x_device = {
.name = "smsc911x",
.id = -1,
.num_resources = ARRAY_SIZE(smsc911x_resources),
.resource = smsc911x_resources,
.dev = {
.platform_data = &smsc911x_config,
},
};
static struct platform_device *rsk7269_devices[] __initdata = {
&smsc911x_device,
};
static int __init rsk7269_devices_setup(void)
{
return platform_add_devices(rsk7269_devices,
ARRAY_SIZE(rsk7269_devices));
}
device_initcall(rsk7269_devices_setup);

1
arch/sh/boards/mach-sdk7780/setup.c
View File

@ -94,7 +94,6 @@ static void __init sdk7780_setup(char **cmdline_p)
static struct sh_machine_vector mv_se7780 __initmv = {
.mv_name = "Renesas SDK7780-R3" ,
.mv_setup = sdk7780_setup,
.mv_nr_irqs = 111,
.mv_init_irq = init_sdk7780_IRQ,
};

1
arch/sh/boards/mach-se/7206/setup.c
View File

@ -90,7 +90,6 @@ static int se7206_mode_pins(void)
static struct sh_machine_vector mv_se __initmv = {
.mv_name = "SolutionEngine",
.mv_nr_irqs = 256,
.mv_init_irq = init_se7206_IRQ,
.mv_mode_pins = se7206_mode_pins,
};

11
arch/sh/boards/mach-se/770x/setup.c
View File

@ -184,16 +184,5 @@ device_initcall(se_devices_setup);
static struct sh_machine_vector mv_se __initmv = {
.mv_name = "SolutionEngine",
.mv_setup = smsc_setup,
#if defined(CONFIG_CPU_SH4)
.mv_nr_irqs = 48,
#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
.mv_nr_irqs = 32,
#elif defined(CONFIG_CPU_SUBTYPE_SH7709)
.mv_nr_irqs = 61,
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
.mv_nr_irqs = 86,
#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
.mv_nr_irqs = 104,
#endif
.mv_init_irq = init_se_IRQ,
};

1
arch/sh/boards/mach-se/7721/setup.c
View File

@ -92,6 +92,5 @@ static void __init se7721_setup(char **cmdline_p)
struct sh_machine_vector mv_se7721 __initmv = {
.mv_name = "Solution Engine 7721",
.mv_setup = se7721_setup,
.mv_nr_irqs = 109,
.mv_init_irq = init_se7721_IRQ,
};

3
arch/sh/boards/mach-se/7722/setup.c
View File

@ -16,6 +16,7 @@
#include <linux/input.h>
#include <linux/input/sh_keysc.h>
#include <linux/smc91x.h>
#include <linux/sh_intc.h>
#include <mach-se/mach/se7722.h>
#include <mach-se/mach/mrshpc.h>
#include <asm/machvec.h>
@ -114,7 +115,7 @@ static struct resource sh_keysc_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 79,
.start = evt2irq(0xbe0),
.flags = IORESOURCE_IRQ,
},
};

32
arch/sh/boards/mach-se/7724/setup.c
View File

@ -24,6 +24,7 @@
#include <linux/input/sh_keysc.h>
#include <linux/usb/r8a66597.h>
#include <linux/sh_eth.h>
#include <linux/sh_intc.h>
#include <linux/videodev2.h>
#include <video/sh_mobile_lcdc.h>
#include <media/sh_mobile_ceu.h>
@ -197,7 +198,7 @@ static struct resource lcdc_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 106,
.start = evt2irq(0xf40),
.flags = IORESOURCE_IRQ,
},
};
@ -224,7 +225,7 @@ static struct resource ceu0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 52,
.start = evt2irq(0x880),
.flags = IORESOURCE_IRQ,
},
[2] = {
@ -255,7 +256,7 @@ static struct resource ceu1_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 63,
.start = evt2irq(0x9e0),
.flags = IORESOURCE_IRQ,
},
[2] = {
@ -289,7 +290,7 @@ static struct resource fsi_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 108,
.start = evt2irq(0xf80),
.flags = IORESOURCE_IRQ,
},
};
@ -343,7 +344,7 @@ static struct resource keysc_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 79,
.start = evt2irq(0xbe0),
.flags = IORESOURCE_IRQ,
},
};
@ -366,7 +367,7 @@ static struct resource sh_eth_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 91,
.start = evt2irq(0xd60),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
@ -397,8 +398,8 @@ static struct resource sh7724_usb0_host_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 65,
.end = 65,
.start = evt2irq(0xa20),
.end = evt2irq(0xa20),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
@ -426,8 +427,8 @@ static struct resource sh7724_usb1_gadget_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 66,
.end = 66,
.start = evt2irq(0xa40),
.end = evt2irq(0xa40),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
@ -452,7 +453,7 @@ static struct resource sdhi0_cn7_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 100,
.start = evt2irq(0xe80),
.flags = IORESOURCE_IRQ,
},
};
@ -481,7 +482,7 @@ static struct resource sdhi1_cn8_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 23,
.start = evt2irq(0x4e0),
.flags = IORESOURCE_IRQ,
},
};
@ -511,7 +512,7 @@ static struct resource irda_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 20,
.start = evt2irq(0x480),
.flags = IORESOURCE_IRQ,
},
};
@ -549,7 +550,7 @@ static struct resource sh_vou_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 55,
.start = evt2irq(0x8e0),
.flags = IORESOURCE_IRQ,
},
};
@ -595,6 +596,7 @@ static struct i2c_board_info i2c0_devices[] = {
#define EEPROM_DATA 0xBA20600C
#define EEPROM_STAT 0xBA206010
#define EEPROM_STRT 0xBA206014
static int __init sh_eth_is_eeprom_ready(void)
{
int t = 10000;
@ -651,7 +653,6 @@ extern char ms7724se_sdram_enter_end;
extern char ms7724se_sdram_leave_start;
extern char ms7724se_sdram_leave_end;
static int __init arch_setup(void)
{
/* enable I2C device */
@ -928,5 +929,4 @@ device_initcall(devices_setup);
static struct sh_machine_vector mv_ms7724se __initmv = {
.mv_name = "ms7724se",
.mv_init_irq = init_se7724_IRQ,
.mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR,
};

1
arch/sh/boards/mach-se/7751/setup.c
View File

@ -55,6 +55,5 @@ device_initcall(se7751_devices_setup);
*/
static struct sh_machine_vector mv_7751se __initmv = {
.mv_name = "7751 SolutionEngine",
.mv_nr_irqs = 72,
.mv_init_irq = init_7751se_IRQ,
};

1
arch/sh/boards/mach-se/7780/setup.c
View File

@ -110,6 +110,5 @@ static void __init se7780_setup(char **cmdline_p)
static struct sh_machine_vector mv_se7780 __initmv = {
.mv_name = "Solution Engine 7780" ,
.mv_setup = se7780_setup ,
.mv_nr_irqs = 111 ,
.mv_init_irq = init_se7780_IRQ,
};

1
arch/sh/boards/mach-se/board-se7619.c
View File

@ -22,6 +22,5 @@ static int se7619_mode_pins(void)
static struct sh_machine_vector mv_se __initmv = {
.mv_name = "SolutionEngine",
.mv_nr_irqs = 108,
.mv_mode_pins = se7619_mode_pins,
};

1
arch/sh/boards/mach-sh03/setup.c
View File

@ -101,6 +101,5 @@ device_initcall(sh03_devices_setup);
static struct sh_machine_vector mv_sh03 __initmv = {
.mv_name = "Interface (CTP/PCI-SH03)",
.mv_setup = sh03_setup,
.mv_nr_irqs = 48,
.mv_init_irq = init_sh03_IRQ,
};

6
arch/sh/boards/mach-sh7763rdp/setup.c
View File

@ -18,6 +18,7 @@
#include <linux/fb.h>
#include <linux/io.h>
#include <linux/sh_eth.h>
#include <linux/sh_intc.h>
#include <mach/sh7763rdp.h>
#include <asm/sh7760fb.h>
@ -67,7 +68,7 @@ static struct platform_device sh7763rdp_nor_flash_device = {
* SH-Ether
*
* SH Ether of SH7763 has multi IRQ handling.
* (57,58,59 -> 57)
* (0x920,0x940,0x960 -> 0x920)
*/
static struct resource sh_eth_resources[] = {
{
@ -79,7 +80,7 @@ static struct resource sh_eth_resources[] = {
.end = 0xFEE01FFF,
.flags = IORESOURCE_MEM,
}, {
.start = 57, /* irq number */
.start = evt2irq(0x920), /* irq number */
.flags = IORESOURCE_IRQ,
},
};
@ -213,6 +214,5 @@ static void __init sh7763rdp_setup(char **cmdline_p)
static struct sh_machine_vector mv_sh7763rdp __initmv = {
.mv_name = "sh7763drp",
.mv_setup = sh7763rdp_setup,
.mv_nr_irqs = 112,
.mv_init_irq = init_sh7763rdp_IRQ,
};

80
arch/sh/configs/rsk7264_defconfig Normal file
View File

@ -0,0 +1,80 @@
CONFIG_LOCALVERSION="uClinux RSK2+SH7264"
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_NAMESPACES=y
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_COUNTERS=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_SLAB=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
CONFIG_PROFILING=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_CPU_SUBTYPE_SH7264=y
CONFIG_MEMORY_START=0x0c000000
CONFIG_FLATMEM_MANUAL=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_SH_RSK=y
# CONFIG_SH_TIMER_MTU2 is not set
CONFIG_BINFMT_FLAT=y
CONFIG_NET=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_FW_LOADER is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_SMSC911X=y
CONFIG_SMSC_PHY=y
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=8
CONFIG_SERIAL_SH_SCI_CONSOLE=y
# CONFIG_HWMON is not set
CONFIG_USB=y
CONFIG_USB_DEBUG=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_R8A66597_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_DEBUG=y
CONFIG_USB_LIBUSUAL=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_VFAT_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_FTRACE is not set

65
arch/sh/configs/rsk7269_defconfig Normal file
View File

@ -0,0 +1,65 @@
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_SLAB=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_SWAP_IO_SPACE=y
CONFIG_CPU_SUBTYPE_SH7269=y
CONFIG_MEMORY_START=0x0c000000
CONFIG_MEMORY_SIZE=0x02000000
CONFIG_FLATMEM_MANUAL=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_SH_RSK=y
# CONFIG_SH_TIMER_MTU2 is not set
CONFIG_SH_PCLK_FREQ=66700000
CONFIG_BINFMT_FLAT=y
CONFIG_NET=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_SMSC911X=y
CONFIG_SMSC_PHY=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=8
CONFIG_SERIAL_SH_SCI_CONSOLE=y
# CONFIG_HWMON is not set
CONFIG_USB=y
CONFIG_USB_DEBUG=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_R8A66597_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_DEBUG=y
CONFIG_USB_LIBUSUAL=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_VFAT_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_FTRACE is not set

17
arch/sh/drivers/dma/Kconfig
View File

@ -40,23 +40,6 @@ config NR_ONCHIP_DMA_CHANNELS
DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the
SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, default is 6.
config NR_DMA_CHANNELS_BOOL
depends on SH_DMA
bool "Override default number of maximum DMA channels"
help
This allows you to forcibly update the maximum number of supported
DMA channels for a given board. If this is unset, this will default
to the number of channels that the on-chip DMAC has.
config NR_DMA_CHANNELS
int "Maximum number of DMA channels"
depends on SH_DMA && NR_DMA_CHANNELS_BOOL
default NR_ONCHIP_DMA_CHANNELS
help
This allows you to specify the maximum number of DMA channels to
support. Setting this to a higher value allows for cascading DMACs
with additional channels.
config SH_DMABRG
bool "SH7760 DMABRG support"
depends on CPU_SUBTYPE_SH7760

294
arch/sh/drivers/dma/dma-sh.c
View File

@ -14,35 +14,72 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/io.h>
#include <mach-dreamcast/mach/dma.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/dma-sh.h>
#include <asm/dma-register.h>
#include <cpu/dma-register.h>
#include <cpu/dma.h>
#if defined(DMAE1_IRQ)
#define NR_DMAE 2
#else
#define NR_DMAE 1
/*
* Define the default configuration for dual address memory-memory transfer.
* The 0x400 value represents auto-request, external->external.
*/
#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT))
static unsigned long dma_find_base(unsigned int chan)
{
unsigned long base = SH_DMAC_BASE0;
#ifdef SH_DMAC_BASE1
if (chan >= 6)
base = SH_DMAC_BASE1;
#endif
static const char *dmae_name[] = {
"DMAC Address Error0", "DMAC Address Error1"
return base;
}
static unsigned long dma_base_addr(unsigned int chan)
{
unsigned long base = dma_find_base(chan);
/* Normalize offset calculation */
if (chan >= 9)
chan -= 6;
if (chan >= 4)
base += 0x10;
return base + (chan * 0x10);
}
#ifdef CONFIG_SH_DMA_IRQ_MULTI
static inline unsigned int get_dmte_irq(unsigned int chan)
{
return chan >= 6 ? DMTE6_IRQ : DMTE0_IRQ;
}
#else
static unsigned int dmte_irq_map[] = {
DMTE0_IRQ, DMTE0_IRQ + 1, DMTE0_IRQ + 2, DMTE0_IRQ + 3,
#ifdef DMTE4_IRQ
DMTE4_IRQ, DMTE4_IRQ + 1,
#endif
#ifdef DMTE6_IRQ
DMTE6_IRQ, DMTE6_IRQ + 1,
#endif
#ifdef DMTE8_IRQ
DMTE8_IRQ, DMTE9_IRQ, DMTE10_IRQ, DMTE11_IRQ,
#endif
};
static inline unsigned int get_dmte_irq(unsigned int chan)
{
unsigned int irq = 0;
if (chan < ARRAY_SIZE(dmte_irq_map))
irq = dmte_irq_map[chan];
#if defined(CONFIG_SH_DMA_IRQ_MULTI)
if (irq > DMTE6_IRQ)
return DMTE6_IRQ;
return DMTE0_IRQ;
#else
return irq;
#endif
return dmte_irq_map[chan];
}
#endif
/*
* We determine the correct shift size based off of the CHCR transmit size
@ -53,9 +90,10 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
* iterations to complete the transfer.
*/
static unsigned int ts_shift[] = TS_SHIFT;
static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
{
u32 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
u32 chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
@ -73,13 +111,13 @@ static irqreturn_t dma_tei(int irq, void *dev_id)
struct dma_channel *chan = dev_id;
u32 chcr;
chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
if (!(chcr & CHCR_TE))
return IRQ_NONE;
chcr &= ~(CHCR_IE | CHCR_DE);
__raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
wake_up(&chan->wait_queue);
@ -91,13 +129,8 @@ static int sh_dmac_request_dma(struct dma_channel *chan)
if (unlikely(!(chan->flags & DMA_TEI_CAPABLE)))
return 0;
return request_irq(get_dmte_irq(chan->chan), dma_tei,
#if defined(CONFIG_SH_DMA_IRQ_MULTI)
IRQF_SHARED,
#else
0,
#endif
chan->dev_id, chan);
return request_irq(get_dmte_irq(chan->chan), dma_tei, IRQF_SHARED,
chan->dev_id, chan);
}
static void sh_dmac_free_dma(struct dma_channel *chan)
@ -118,7 +151,7 @@ sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
chan->flags &= ~DMA_TEI_CAPABLE;
}
__raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
chan->flags |= DMA_CONFIGURED;
return 0;
@ -129,13 +162,13 @@ static void sh_dmac_enable_dma(struct dma_channel *chan)
int irq;
u32 chcr;
chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
chcr |= CHCR_DE;
if (chan->flags & DMA_TEI_CAPABLE)
chcr |= CHCR_IE;
__raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
if (chan->flags & DMA_TEI_CAPABLE) {
irq = get_dmte_irq(chan->chan);
@ -153,9 +186,9 @@ static void sh_dmac_disable_dma(struct dma_channel *chan)
disable_irq(irq);
}
chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
__raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
}
static int sh_dmac_xfer_dma(struct dma_channel *chan)
@ -186,13 +219,13 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
*/
if (chan->sar || (mach_is_dreamcast() &&
chan->chan == PVR2_CASCADE_CHAN))
__raw_writel(chan->sar, (dma_base_addr[chan->chan]+SAR));
__raw_writel(chan->sar, (dma_base_addr(chan->chan) + SAR));
if (chan->dar || (mach_is_dreamcast() &&
chan->chan == PVR2_CASCADE_CHAN))
__raw_writel(chan->dar, (dma_base_addr[chan->chan] + DAR));
__raw_writel(chan->dar, (dma_base_addr(chan->chan) + DAR));
__raw_writel(chan->count >> calc_xmit_shift(chan),
(dma_base_addr[chan->chan] + TCR));
(dma_base_addr(chan->chan) + TCR));
sh_dmac_enable_dma(chan);
@ -201,13 +234,32 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
static int sh_dmac_get_dma_residue(struct dma_channel *chan)
{
if (!(__raw_readl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
if (!(__raw_readl(dma_base_addr(chan->chan) + CHCR) & CHCR_DE))
return 0;
return __raw_readl(dma_base_addr[chan->chan] + TCR)
return __raw_readl(dma_base_addr(chan->chan) + TCR)
<< calc_xmit_shift(chan);
}
/*
* DMAOR handling
*/
#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
defined(CONFIG_CPU_SUBTYPE_SH7724) || \
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785)
#define NR_DMAOR 2
#else
#define NR_DMAOR 1
#endif
/*
* DMAOR bases are broken out amongst channel groups. DMAOR0 manages
* channels 0 - 5, DMAOR1 6 - 11 (optional).
*/
#define dmaor_read_reg(n) __raw_readw(dma_find_base((n)*6))
#define dmaor_write_reg(n, data) __raw_writew(data, dma_find_base(n)*6)
static inline int dmaor_reset(int no)
{
unsigned long dmaor = dmaor_read_reg(no);
@ -228,36 +280,86 @@ static inline int dmaor_reset(int no)
return 0;
}
#if defined(CONFIG_CPU_SH4)
/*
* DMAE handling
*/
#ifdef CONFIG_CPU_SH4
#if defined(DMAE1_IRQ)
#define NR_DMAE 2
#else
#define NR_DMAE 1
#endif
static const char *dmae_name[] = {
"DMAC Address Error0",
"DMAC Address Error1"
};
#ifdef CONFIG_SH_DMA_IRQ_MULTI
static inline unsigned int get_dma_error_irq(int n)
{
return get_dmte_irq(n * 6);
}
#else
static unsigned int dmae_irq_map[] = {
DMAE0_IRQ,
#ifdef DMAE1_IRQ
DMAE1_IRQ,
#endif
};
static inline unsigned int get_dma_error_irq(int n)
{
return dmae_irq_map[n];
}
#endif
static irqreturn_t dma_err(int irq, void *dummy)
{
#if defined(CONFIG_SH_DMA_IRQ_MULTI)
int cnt = 0;
switch (irq) {
#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
case DMTE6_IRQ:
cnt++;
#endif
case DMTE0_IRQ:
if (dmaor_read_reg(cnt) & (DMAOR_NMIF | DMAOR_AE)) {
disable_irq(irq);
/* DMA multi and error IRQ */
return IRQ_HANDLED;
}
default:
return IRQ_NONE;
}
#else
dmaor_reset(0);
#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785)
dmaor_reset(1);
#endif
int i;
for (i = 0; i < NR_DMAOR; i++)
dmaor_reset(i);
disable_irq(irq);
return IRQ_HANDLED;
#endif
}
static int dmae_irq_init(void)
{
int n;
for (n = 0; n < NR_DMAE; n++) {
int i = request_irq(get_dma_error_irq(n), dma_err,
IRQF_SHARED, dmae_name[n], NULL);
if (unlikely(i < 0)) {
printk(KERN_ERR "%s request_irq fail\n", dmae_name[n]);
return i;
}
}
return 0;
}
static void dmae_irq_free(void)
{
int n;
for (n = 0; n < NR_DMAE; n++)
free_irq(get_dma_error_irq(n), NULL);
}
#else
static inline int dmae_irq_init(void)
{
return 0;
}
static void dmae_irq_free(void)
{
}
#endif
@ -276,72 +378,34 @@ static struct dma_info sh_dmac_info = {
.flags = DMAC_CHANNELS_TEI_CAPABLE,
};
#ifdef CONFIG_CPU_SH4
static unsigned int get_dma_error_irq(int n)
{
#if defined(CONFIG_SH_DMA_IRQ_MULTI)
return (n == 0) ? get_dmte_irq(0) : get_dmte_irq(6);
#else
return (n == 0) ? DMAE0_IRQ :
#if defined(DMAE1_IRQ)
DMAE1_IRQ;
#else
-1;
#endif
#endif
}
#endif
static int __init sh_dmac_init(void)
{
struct dma_info *info = &sh_dmac_info;
int i;
int i, rc;
#ifdef CONFIG_CPU_SH4
int n;
for (n = 0; n < NR_DMAE; n++) {
i = request_irq(get_dma_error_irq(n), dma_err,
#if defined(CONFIG_SH_DMA_IRQ_MULTI)
IRQF_SHARED,
#else
0,
#endif
dmae_name[n], (void *)dmae_name[n]);
if (unlikely(i < 0)) {
printk(KERN_ERR "%s request_irq fail\n", dmae_name[n]);
return i;
}
}
#endif /* CONFIG_CPU_SH4 */
/*
* Initialize DMAE, for parts that support it.
*/
rc = dmae_irq_init();
if (unlikely(rc != 0))
return rc;
/*
* Initialize DMAOR, and clean up any error flags that may have
* been set.
*/
i = dmaor_reset(0);
if (unlikely(i != 0))
return i;
#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785)
i = dmaor_reset(1);
if (unlikely(i != 0))
return i;
#endif
for (i = 0; i < NR_DMAOR; i++) {
rc = dmaor_reset(i);
if (unlikely(rc != 0))
return rc;
}
return register_dmac(info);
}
static void __exit sh_dmac_exit(void)
{
#ifdef CONFIG_CPU_SH4
int n;
for (n = 0; n < NR_DMAE; n++) {
free_irq(get_dma_error_irq(n), (void *)dmae_name[n]);
}
#endif /* CONFIG_CPU_SH4 */
dmae_irq_free();
unregister_dmac(&sh_dmac_info);
}

2
arch/sh/drivers/dma/dma-sysfs.c
View File

@ -29,7 +29,7 @@ static ssize_t dma_show_devices(struct device *dev,
ssize_t len = 0;
int i;
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
for (i = 0; i < 16; i++) {
struct dma_info *info = get_dma_info(i);
struct dma_channel *channel = get_dma_channel(i);

3
arch/sh/drivers/pci/fixups-landisk.c
View File

@ -14,6 +14,7 @@
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/sh_intc.h>
#include "pci-sh4.h"
#define PCIMCR_MRSET_OFF 0xBFFFFFFF
@ -27,7 +28,7 @@ int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
* slot2: pin1-4 = irq7,8,5,6
* slot3: pin1-4 = irq8,5,6,7
*/
int irq = ((slot + pin - 1) & 0x3) + 5;
int irq = ((slot + pin - 1) & 0x3) + evt2irq(0x2a0);
if ((slot | (pin - 1)) > 0x3) {
printk(KERN_WARNING "PCI: Bad IRQ mapping request for slot %d pin %c\n",

7
arch/sh/drivers/pci/fixups-r7780rp.c
View File

@ -12,13 +12,10 @@
*/
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/sh_intc.h>
#include "pci-sh4.h"
static char irq_tab[] __initdata = {
65, 66, 67, 68,
};
int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
{
return irq_tab[slot];
return evt2irq(0xa20) + slot;
}

18
arch/sh/drivers/pci/fixups-sdk7780.c
View File

@ -13,18 +13,28 @@
*/
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/sh_intc.h>
#include "pci-sh4.h"
#define IRQ_INTA evt2irq(0xa20)
#define IRQ_INTB evt2irq(0xa40)
#define IRQ_INTC evt2irq(0xa60)
#define IRQ_INTD evt2irq(0xa80)
/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
static char sdk7780_irq_tab[4][16] __initdata = {
/* INTA */
{ 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
{ IRQ_INTA, IRQ_INTD, IRQ_INTC, IRQ_INTD, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1 },
/* INTB */
{ 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
{ IRQ_INTB, IRQ_INTA, -1, IRQ_INTA, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1 },
/* INTC */
{ 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
{ IRQ_INTC, IRQ_INTB, -1, IRQ_INTB, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1 },
/* INTD */
{ 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
{ IRQ_INTD, IRQ_INTC, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1 },
};
int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)

5
arch/sh/drivers/pci/fixups-se7751.c
View File

@ -4,13 +4,14 @@
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/sh_intc.h>
#include "pci-sh4.h"
int __init pcibios_map_platform_irq(const struct pci_dev *, u8 slot, u8 pin)
{
switch (slot) {
case 0: return 13;
case 1: return 13; /* AMD Ethernet controller */
case 0: return evt2irq(0x3a0);
case 1: return evt2irq(0x3a0); /* AMD Ethernet controller */
case 2: return -1;
case 3: return -1;
case 4: return -1;

19
arch/sh/drivers/pci/fixups-sh03.c
View File

@ -2,6 +2,7 @@
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/sh_intc.h>
int __init pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
@ -9,21 +10,21 @@ int __init pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin)
if (dev->bus->number == 0) {
switch (slot) {
case 4: return 5; /* eth0 */
case 8: return 5; /* eth1 */
case 6: return 2; /* PCI bridge */
case 4: return evt2irq(0x2a0); /* eth0 */
case 8: return evt2irq(0x2a0); /* eth1 */
case 6: return evt2irq(0x240); /* PCI bridge */
default:
printk(KERN_ERR "PCI: Bad IRQ mapping request "
"for slot %d\n", slot);
return 2;
return evt2irq(0x240);
}
} else {
switch (pin) {
case 0: irq = 2; break;
case 1: irq = 2; break;
case 2: irq = 2; break;
case 3: irq = 2; break;
case 4: irq = 2; break;
case 0: irq = evt2irq(0x240); break;
case 1: irq = evt2irq(0x240); break;
case 2: irq = evt2irq(0x240); break;
case 3: irq = evt2irq(0x240); break;
case 4: irq = evt2irq(0x240); break;
default: irq = -1; break;
}
}

11
arch/sh/drivers/pci/fixups-snapgear.c
View File

@ -16,6 +16,7 @@
#include <linux/types.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/sh_intc.h>
#include "pci-sh4.h"
int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
@ -24,11 +25,11 @@ int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
switch (slot) {
case 8: /* the PCI bridge */ break;
case 11: irq = 8; break; /* USB */
case 12: irq = 11; break; /* PCMCIA */
case 13: irq = 5; break; /* eth0 */
case 14: irq = 8; break; /* eth1 */
case 15: irq = 11; break; /* safenet (unused) */
case 11: irq = evt2irq(0x300); break; /* USB */
case 12: irq = evt2irq(0x360); break; /* PCMCIA */
case 13: irq = evt2irq(0x2a0); break; /* eth0 */
case 14: irq = evt2irq(0x300); break; /* eth1 */
case 15: irq = evt2irq(0x360); break; /* safenet (unused) */
}
printk("PCI: Mapping SnapGear IRQ for slot %d, pin %c to irq %d\n",

3
arch/sh/drivers/pci/pcie-sh7786.c
View File

@ -18,6 +18,7 @@
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/sh_clk.h>
#include <linux/sh_intc.h>
#include "pcie-sh7786.h"
#include <asm/sizes.h>
@ -468,7 +469,7 @@ static int __init pcie_init(struct sh7786_pcie_port *port)
int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
{
return 71;
return evt2irq(0xae0);
}
static int __init sh7786_pcie_core_init(void)

87
arch/sh/include/asm/dma-sh.h
View File

@ -1,87 +0,0 @@
/*
* arch/sh/include/asm/dma-sh.h
*
* Copyright (C) 2000 Takashi YOSHII
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __DMA_SH_H
#define __DMA_SH_H
#include <asm/dma-register.h>
#include <cpu/dma-register.h>
#include <cpu/dma.h>
/* DMAOR contorl: The DMAOR access size is different by CPU.*/
#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
defined(CONFIG_CPU_SUBTYPE_SH7724) || \
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785)
#define dmaor_read_reg(n) \
(n ? __raw_readw(SH_DMAC_BASE1 + DMAOR) \
: __raw_readw(SH_DMAC_BASE0 + DMAOR))
#define dmaor_write_reg(n, data) \
(n ? __raw_writew(data, SH_DMAC_BASE1 + DMAOR) \
: __raw_writew(data, SH_DMAC_BASE0 + DMAOR))
#else /* Other CPU */
#define dmaor_read_reg(n) __raw_readw(SH_DMAC_BASE0 + DMAOR)
#define dmaor_write_reg(n, data) __raw_writew(data, SH_DMAC_BASE0 + DMAOR)
#endif
static int dmte_irq_map[] __maybe_unused = {
#if (MAX_DMA_CHANNELS >= 4)
DMTE0_IRQ,
DMTE0_IRQ + 1,
DMTE0_IRQ + 2,
DMTE0_IRQ + 3,
#endif
#if (MAX_DMA_CHANNELS >= 6)
DMTE4_IRQ,
DMTE4_IRQ + 1,
#endif
#if (MAX_DMA_CHANNELS >= 8)
DMTE6_IRQ,
DMTE6_IRQ + 1,
#endif
#if (MAX_DMA_CHANNELS >= 12)
DMTE8_IRQ,
DMTE9_IRQ,
DMTE10_IRQ,
DMTE11_IRQ,
#endif
};
/*
* Define the default configuration for dual address memory-memory transfer.
* The 0x400 value represents auto-request, external->external.
*/
#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT))
/* DMA base address */
static u32 dma_base_addr[] __maybe_unused = {
#if (MAX_DMA_CHANNELS >= 4)
SH_DMAC_BASE0 + 0x00, /* channel 0 */
SH_DMAC_BASE0 + 0x10,
SH_DMAC_BASE0 + 0x20,
SH_DMAC_BASE0 + 0x30,
#endif
#if (MAX_DMA_CHANNELS >= 6)
SH_DMAC_BASE0 + 0x50,
SH_DMAC_BASE0 + 0x60,
#endif
#if (MAX_DMA_CHANNELS >= 8)
SH_DMAC_BASE1 + 0x00,
SH_DMAC_BASE1 + 0x10,
#endif
#if (MAX_DMA_CHANNELS >= 12)
SH_DMAC_BASE1 + 0x20,
SH_DMAC_BASE1 + 0x30,
SH_DMAC_BASE1 + 0x50,
SH_DMAC_BASE1 + 0x60, /* channel 11 */
#endif
};
#endif /* __DMA_SH_H */

9
arch/sh/include/asm/dma.h
View File

@ -15,17 +15,8 @@
#include <linux/wait.h>
#include <linux/sched.h>
#include <linux/device.h>
#include <cpu/dma.h>
#include <asm-generic/dma.h>
#ifdef CONFIG_NR_DMA_CHANNELS
# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
#elif defined(CONFIG_NR_ONCHIP_DMA_CHANNELS)
# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
#else
# define MAX_DMA_CHANNELS 0
#endif
/*
* Read and write modes can mean drastically different things depending on the
* channel configuration. Consult your DMAC documentation and module

2
arch/sh/include/asm/fixmap.h
View File

@ -96,7 +96,7 @@ extern void __clear_fixmap(enum fixed_addresses idx, pgprot_t flags);
#ifdef CONFIG_SUPERH32
#define FIXADDR_TOP (P4SEG - PAGE_SIZE)
#else
#define FIXADDR_TOP (0xff000000 - PAGE_SIZE)
#define FIXADDR_TOP ((unsigned long)(-PAGE_SIZE))
#endif
#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)

2
arch/sh/include/asm/i2c-sh7760.h
View File

@ -9,11 +9,9 @@
#define SH7760_I2C0_MMIO 0xFE140000
#define SH7760_I2C0_MMIOEND 0xFE14003B
#define SH7760_I2C0_IRQ 62
#define SH7760_I2C1_MMIO 0xFE150000
#define SH7760_I2C1_MMIOEND 0xFE15003B
#define SH7760_I2C1_IRQ 63
struct sh7760_i2c_platdata {
unsigned int speed_khz;

5
arch/sh/include/asm/io.h
View File

@ -218,8 +218,13 @@ __BUILD_IOPORT_STRING(w, u16)
__BUILD_IOPORT_STRING(l, u32)
__BUILD_IOPORT_STRING(q, u64)
#else /* !CONFIG_HAS_IOPORT */
#include <asm/io_noioport.h>
#endif
#define IO_SPACE_LIMIT 0xffffffff
/* synco on SH-4A, otherwise a nop */

41
arch/sh/include/asm/io_noioport.h Normal file
View File

@ -0,0 +1,41 @@
#ifndef __ASM_SH_IO_NOIOPORT_H
#define __ASM_SH_IO_NOIOPORT_H
static inline u8 inb(unsigned long addr)
{
BUG();
return -1;
}
static inline u16 inw(unsigned long addr)
{
BUG();
return -1;
}
static inline u32 inl(unsigned long addr)
{
BUG();
return -1;
}
#define outb(x, y) BUG()
#define outw(x, y) BUG()
#define outl(x, y) BUG()
#define inb_p(addr) inb(addr)
#define inw_p(addr) inw(addr)
#define inl_p(addr) inl(addr)
#define outb_p(x, addr) outb((x), (addr))
#define outw_p(x, addr) outw((x), (addr))
#define outl_p(x, addr) outl((x), (addr))
#define insb(a, b, c) BUG()
#define insw(a, b, c) BUG()
#define insl(a, b, c) BUG()
#define outsb(a, b, c) BUG()
#define outsw(a, b, c) BUG()
#define outsl(a, b, c) BUG()
#endif /* __ASM_SH_IO_NOIOPORT_H */

13
arch/sh/include/asm/irq.h
View File

@ -5,12 +5,15 @@
#include <asm/machvec.h>
/*
* A sane default based on a reasonable vector table size, platforms are
* advised to cap this at the hard limit that they're interested in
* through the machvec.
* Only legacy non-sparseirq platforms have to set a reasonably sane
* value here. sparseirq platforms allocate their irq_descs on the fly,
* so will expand automatically based on the number of registered IRQs.
*/
#define NR_IRQS 512
#define NR_IRQS_LEGACY 8 /* Legacy external IRQ0-7 */
#ifdef CONFIG_SPARSE_IRQ
# define NR_IRQS 8
#else
# define NR_IRQS 512
#endif
/*
* This is a special IRQ number for indicating that no IRQ has been

2
arch/sh/include/asm/kdebug.h
View File

@ -10,4 +10,6 @@ enum die_val {
DIE_SSTEP,
};
extern void printk_address(unsigned long address, int reliable);
#endif /* __ASM_SH_KDEBUG_H */

30
arch/sh/include/asm/kgdb.h
View File

@ -4,18 +4,6 @@
#include <asm/cacheflush.h>
#include <asm/ptrace.h>
/* Same as pt_regs but has vbr in place of syscall_nr */
struct kgdb_regs {
unsigned long regs[16];
unsigned long pc;
unsigned long pr;
unsigned long sr;
unsigned long gbr;
unsigned long mach;
unsigned long macl;
unsigned long vbr;
};
enum regnames {
GDB_R0, GDB_R1, GDB_R2, GDB_R3, GDB_R4, GDB_R5, GDB_R6, GDB_R7,
GDB_R8, GDB_R9, GDB_R10, GDB_R11, GDB_R12, GDB_R13, GDB_R14, GDB_R15,
@ -23,17 +11,27 @@ enum regnames {
GDB_PC, GDB_PR, GDB_SR, GDB_GBR, GDB_MACH, GDB_MACL, GDB_VBR,
};
#define NUMREGBYTES ((GDB_VBR + 1) * 4)
#define _GP_REGS 16
#define _EXTRA_REGS 7
#define GDB_SIZEOF_REG sizeof(u32)
#define DBG_MAX_REG_NUM (_GP_REGS + _EXTRA_REGS)
#define NUMREGBYTES (DBG_MAX_REG_NUM * sizeof(GDB_SIZEOF_REG))
static inline void arch_kgdb_breakpoint(void)
{
__asm__ __volatile__ ("trapa #0x3c\n");
}
#define BUFMAX 2048
#define CACHE_FLUSH_IS_SAFE 1
#define BREAK_INSTR_SIZE 2
#define BUFMAX 2048
#ifdef CONFIG_SMP
# define CACHE_FLUSH_IS_SAFE 0
#else
# define CACHE_FLUSH_IS_SAFE 1
#endif
#define GDB_ADJUSTS_BREAK_OFFSET
#endif /* __ASM_SH_KGDB_H */

1
arch/sh/include/asm/machvec.h
View File

@ -17,7 +17,6 @@
struct sh_machine_vector {
void (*mv_setup)(char **cmdline_p);
const char *mv_name;
int mv_nr_irqs;
int (*mv_irq_demux)(int irq);
void (*mv_init_irq)(void);

3
arch/sh/include/asm/pgtable_64.h
View File

@ -87,9 +87,6 @@ static __inline__ void set_pte(pte_t *pteptr, pte_t pteval)
#define pte_unmap(pte) do { } while (0)
#ifndef __ASSEMBLY__
#define IOBASE_VADDR 0xff000000
#define IOBASE_END 0xffffffff
/*
* PTEL coherent flags.
* See Chapter 17 ST50 CPU Core Volume 1, Architecture.

5
arch/sh/include/asm/processor.h
View File

@ -18,7 +18,8 @@ enum cpu_type {
CPU_SH7619,
/* SH-2A types */
CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269,
CPU_MXG,
/* SH-3 types */
CPU_SH7705, CPU_SH7706, CPU_SH7707,
@ -32,7 +33,7 @@ enum cpu_type {
/* SH-4A types */
CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3,
CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SH7734, CPU_SHX3,
/* SH4AL-DSP types */
CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372,

3
arch/sh/include/asm/processor_64.h
View File

@ -121,7 +121,6 @@ struct thread_struct {
NULL for a kernel thread. */
struct pt_regs *uregs;
unsigned long trap_no, error_code;
unsigned long address;
/* Hardware debugging registers may come here */
@ -138,8 +137,6 @@ struct thread_struct {
.pc = 0, \
.kregs = &fake_swapper_regs, \
.uregs = NULL, \
.trap_no = 0, \
.error_code = 0, \
.address = 0, \
.flags = 0, \
}

27
arch/sh/include/asm/stackprotector.h Normal file
View File

@ -0,0 +1,27 @@
#ifndef __ASM_SH_STACKPROTECTOR_H
#define __ASM_SH_STACKPROTECTOR_H
#include <linux/random.h>
#include <linux/version.h>
extern unsigned long __stack_chk_guard;
/*
* Initialize the stackprotector canary value.
*
* NOTE: this must only be called from functions that never return,
* and it must always be inlined.
*/
static __always_inline void boot_init_stack_canary(void)
{
unsigned long canary;
/* Try to get a semi random initial value. */
get_random_bytes(&canary, sizeof(canary));
canary ^= LINUX_VERSION_CODE;
current->stack_canary = canary;
__stack_chk_guard = current->stack_canary;
}
#endif /* __ASM_SH_STACKPROTECTOR_H */

46
arch/sh/include/asm/thread_info.h
View File

@ -10,8 +10,18 @@
* - Incorporating suggestions made by Linus Torvalds and Dave Miller
*/
#ifdef __KERNEL__
#include <asm/page.h>
/*
* Page fault error code bits
*/
#define FAULT_CODE_WRITE (1 << 0) /* write access */
#define FAULT_CODE_INITIAL (1 << 1) /* initial page write */
#define FAULT_CODE_ITLB (1 << 2) /* ITLB miss */
#define FAULT_CODE_PROT (1 << 3) /* protection fault */
#define FAULT_CODE_USER (1 << 4) /* user-mode access */
#ifndef __ASSEMBLY__
#include <asm/processor.h>
@ -98,10 +108,13 @@ extern void init_thread_xstate(void);
#endif /* __ASSEMBLY__ */
/*
* thread information flags
* - these are process state flags that various assembly files may need to access
* - pending work-to-be-done flags are in LSW
* - other flags in MSW
* Thread information flags
*
* - Limited to 24 bits, upper byte used for fault code encoding.
*
* - _TIF_ALLWORK_MASK and _TIF_WORK_MASK need to fit within 2 bytes, or
* we blow the tst immediate size constraints and need to fix up
* arch/sh/kernel/entry-common.S.
*/
#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
#define TIF_SIGPENDING 1 /* signal pending */
@ -124,12 +137,6 @@ extern void init_thread_xstate(void);
#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG)
/*
* _TIF_ALLWORK_MASK and _TIF_WORK_MASK need to fit within 2 bytes, or we
* blow the tst immediate size constraints and need to fix up
* arch/sh/kernel/entry-common.S.
*/
/* work to do in syscall trace */
#define _TIF_WORK_SYSCALL_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \
_TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
@ -156,6 +163,7 @@ extern void init_thread_xstate(void);
#define TS_USEDFPU 0x0002 /* FPU used by this task this quantum */
#ifndef __ASSEMBLY__
#define HAVE_SET_RESTORE_SIGMASK 1
static inline void set_restore_sigmask(void)
{
@ -163,6 +171,24 @@ static inline void set_restore_sigmask(void)
ti->status |= TS_RESTORE_SIGMASK;
set_bit(TIF_SIGPENDING, (unsigned long *)&ti->flags);
}
#define TI_FLAG_FAULT_CODE_SHIFT 24
/*
* Additional thread flag encoding
*/
static inline void set_thread_fault_code(unsigned int val)
{
struct thread_info *ti = current_thread_info();
ti->flags = (ti->flags & (~0 >> (32 - TI_FLAG_FAULT_CODE_SHIFT)))
| (val << TI_FLAG_FAULT_CODE_SHIFT);
}
static inline unsigned int get_thread_fault_code(void)
{
struct thread_info *ti = current_thread_info();
return ti->flags >> TI_FLAG_FAULT_CODE_SHIFT;
}
#endif /* !__ASSEMBLY__ */
#endif /* __KERNEL__ */

14
arch/sh/include/asm/traps_64.h
View File

@ -10,8 +10,22 @@
#ifndef __ASM_SH_TRAPS_64_H
#define __ASM_SH_TRAPS_64_H
#include <cpu/registers.h>
extern void phys_stext(void);
#define lookup_exception_vector() \
({ \
unsigned long _vec; \
\
__asm__ __volatile__ ( \
"getcon " __EXPEVT ", %0\n\t" \
: "=r" (_vec) \
); \
\
_vec; \
})
static inline void trigger_address_error(void)
{
phys_stext();

23
arch/sh/include/cpu-sh2/cpu/dma.h
View File

@ -1,23 +0,0 @@
/*
* Definitions for the SH-2 DMAC.
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_DMA_H
#define __ASM_CPU_SH2_DMA_H
#define SH_MAX_DMA_CHANNELS 2
#define SAR ((unsigned long[]){ 0xffffff80, 0xffffff90 })
#define DAR ((unsigned long[]){ 0xffffff84, 0xffffff94 })
#define DMATCR ((unsigned long[]){ 0xffffff88, 0xffffff98 })
#define CHCR ((unsigned long[]){ 0xfffffffc, 0xffffff9c })
#define DMAOR 0xffffffb0
#endif /* __ASM_CPU_SH2_DMA_H */

1
arch/sh/include/cpu-sh2a/cpu/dma.h
View File

@ -1 +0,0 @@
#include <cpu-sh2/cpu/dma.h>

176
arch/sh/include/cpu-sh2a/cpu/sh7264.h Normal file
View File

@ -0,0 +1,176 @@
#ifndef __ASM_SH7264_H__
#define __ASM_SH7264_H__
enum {
/* Port A */
GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
/* Port B */
GPIO_PB22, GPIO_PB21, GPIO_PB20,
GPIO_PB19, GPIO_PB18, GPIO_PB17, GPIO_PB16,
GPIO_PB15, GPIO_PB14, GPIO_PB13, GPIO_PB12,
GPIO_PB11, GPIO_PB10, GPIO_PB9, GPIO_PB8,
GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
GPIO_PB3, GPIO_PB2, GPIO_PB1,
/* Port C */
GPIO_PC10, GPIO_PC9, GPIO_PC8,
GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
/* Port D */
GPIO_PD15, GPIO_PD14, GPIO_PD13, GPIO_PD12,
GPIO_PD11, GPIO_PD10, GPIO_PD9, GPIO_PD8,
GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
/* Port E */
GPIO_PE5, GPIO_PE4,
GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0,
/* Port F */
GPIO_PF12,
GPIO_PF11, GPIO_PF10, GPIO_PF9, GPIO_PF8,
GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
/* Port G */
GPIO_PG24,
GPIO_PG23, GPIO_PG22, GPIO_PG21, GPIO_PG20,
GPIO_PG19, GPIO_PG18, GPIO_PG17, GPIO_PG16,
GPIO_PG15, GPIO_PG14, GPIO_PG13, GPIO_PG12,
GPIO_PG11, GPIO_PG10, GPIO_PG9, GPIO_PG8,
GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
/* Port H */
GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
/* Port I - not on device */
/* Port J */
GPIO_PJ11, GPIO_PJ10, GPIO_PJ9, GPIO_PJ8,
GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
/* Port K */
GPIO_PK11, GPIO_PK10, GPIO_PK9, GPIO_PK8,
GPIO_PK7, GPIO_PK6, GPIO_PK5, GPIO_PK4,
GPIO_PK3, GPIO_PK2, GPIO_PK1, GPIO_PK0,
/* INTC: IRQ and PINT on PB/PD/PE */
GPIO_FN_PINT7_PG, GPIO_FN_PINT6_PG, GPIO_FN_PINT5_PG, GPIO_FN_PINT4_PG,
GPIO_FN_PINT3_PG, GPIO_FN_PINT2_PG, GPIO_FN_PINT1_PG,
GPIO_FN_IRQ7_PC, GPIO_FN_IRQ6_PC, GPIO_FN_IRQ5_PC, GPIO_FN_IRQ4_PC,
GPIO_FN_IRQ3_PG, GPIO_FN_IRQ2_PG, GPIO_FN_IRQ1_PJ, GPIO_FN_IRQ0_PJ,
GPIO_FN_IRQ3_PE, GPIO_FN_IRQ2_PE, GPIO_FN_IRQ1_PE, GPIO_FN_IRQ0_PE,
/* WDT */
GPIO_FN_WDTOVF,
/* CAN */
GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,
GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1,
/* DMAC */
GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,
GPIO_FN_TEND1, GPIO_FN_DACK1, GPIO_FN_DREQ1,
/* ADC */
GPIO_FN_ADTRG,
/* BSC */
GPIO_FN_A25, GPIO_FN_A24,
GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
GPIO_FN_BS,
GPIO_FN_CS4, GPIO_FN_CS3, GPIO_FN_CS2, GPIO_FN_CS1, GPIO_FN_CS0,
GPIO_FN_CS6CE1B, GPIO_FN_CS5CE1A,
GPIO_FN_CE2A, GPIO_FN_CE2B,
GPIO_FN_RD, GPIO_FN_RDWR,
GPIO_FN_ICIOWRAH, GPIO_FN_ICIORD,
GPIO_FN_WE1DQMUWE, GPIO_FN_WE0DQML,
GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE,
GPIO_FN_WAIT, GPIO_FN_BREQ, GPIO_FN_BACK,
GPIO_FN_IOIS16,
/* TMU */
GPIO_FN_TIOC4D, GPIO_FN_TIOC4C, GPIO_FN_TIOC4B, GPIO_FN_TIOC4A,
GPIO_FN_TIOC3D, GPIO_FN_TIOC3C, GPIO_FN_TIOC3B, GPIO_FN_TIOC3A,
GPIO_FN_TIOC2B, GPIO_FN_TIOC1B, GPIO_FN_TIOC2A, GPIO_FN_TIOC1A,
GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
/* SSU */
GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
/* SCIF */
GPIO_FN_SCK0, GPIO_FN_SCK1, GPIO_FN_SCK2, GPIO_FN_SCK3,
GPIO_FN_RXD0, GPIO_FN_RXD1, GPIO_FN_RXD2, GPIO_FN_RXD3,
GPIO_FN_TXD0, GPIO_FN_TXD1, GPIO_FN_TXD2, GPIO_FN_TXD3,
GPIO_FN_RXD4, GPIO_FN_RXD5, GPIO_FN_RXD6, GPIO_FN_RXD7,
GPIO_FN_TXD4, GPIO_FN_TXD5, GPIO_FN_TXD6, GPIO_FN_TXD7,
GPIO_FN_RTS1, GPIO_FN_RTS3, GPIO_FN_CTS1, GPIO_FN_CTS3,
/* RSPI */
GPIO_FN_RSPCK0, GPIO_FN_MOSI0,
GPIO_FN_MISO0_PF12, GPIO_FN_MISO1,
GPIO_FN_SSL00,
GPIO_FN_RSPCK1, GPIO_FN_MOSI1,
GPIO_FN_MISO1_PG19, GPIO_FN_SSL10,
/* IIC3 */
GPIO_FN_SCL0, GPIO_FN_SCL1, GPIO_FN_SCL2,
GPIO_FN_SDA2, GPIO_FN_SDA1, GPIO_FN_SDA0,
/* SSI */
GPIO_FN_SSISCK0, GPIO_FN_SSIWS0, GPIO_FN_SSITXD0, GPIO_FN_SSIRXD0,
GPIO_FN_SSIWS1, GPIO_FN_SSIWS2, GPIO_FN_SSIWS3,
GPIO_FN_SSISCK1, GPIO_FN_SSISCK2, GPIO_FN_SSISCK3,
GPIO_FN_SSIDATA1, GPIO_FN_SSIDATA2, GPIO_FN_SSIDATA3,
GPIO_FN_AUDIO_CLK,
/* SIOF */
GPIO_FN_SIOFTXD, GPIO_FN_SIOFRXD, GPIO_FN_SIOFSYNC, GPIO_FN_SIOFSCK,
/* SPDIF */
GPIO_FN_SPDIF_IN,
GPIO_FN_SPDIF_OUT,
/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
GPIO_FN_FCE,
GPIO_FN_FRB,
/* VDC3 */
GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC,
GPIO_FN_DV_DATA7, GPIO_FN_DV_DATA6, GPIO_FN_DV_DATA5, GPIO_FN_DV_DATA4,
GPIO_FN_DV_DATA3, GPIO_FN_DV_DATA2, GPIO_FN_DV_DATA1, GPIO_FN_DV_DATA0,
GPIO_FN_LCD_CLK, GPIO_FN_LCD_EXTCLK,
GPIO_FN_LCD_VSYNC, GPIO_FN_LCD_HSYNC, GPIO_FN_LCD_DE,
GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14,
GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12,
GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10,
GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8,
GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6,
GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4,
GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2,
GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0,
GPIO_FN_LCD_M_DISP,
};
#endif /* __ASM_SH7264_H__ */

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arch/sh/include/cpu-sh2a/cpu/sh7269.h Normal file
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@ -0,0 +1,201 @@
#ifndef __ASM_SH7269_H__
#define __ASM_SH7269_H__
enum {
/* Port A */
GPIO_PA1, GPIO_PA0,
/* Port B */
GPIO_PB22, GPIO_PB21, GPIO_PB20,
GPIO_PB19, GPIO_PB18, GPIO_PB17, GPIO_PB16,
GPIO_PB15, GPIO_PB14, GPIO_PB13, GPIO_PB12,
GPIO_PB11, GPIO_PB10, GPIO_PB9, GPIO_PB8,
GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
GPIO_PB3, GPIO_PB2, GPIO_PB1,
/* Port C */
GPIO_PC8,
GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
/* Port D */
GPIO_PD15, GPIO_PD14, GPIO_PD13, GPIO_PD12,
GPIO_PD11, GPIO_PD10, GPIO_PD9, GPIO_PD8,
GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
/* Port E */
GPIO_PE7, GPIO_PE6, GPIO_PE5, GPIO_PE4,
GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0,
/* Port F */
GPIO_PF23, GPIO_PF22, GPIO_PF21, GPIO_PF20,
GPIO_PF19, GPIO_PF18, GPIO_PF17, GPIO_PF16,
GPIO_PF15, GPIO_PF14, GPIO_PF13, GPIO_PF12,
GPIO_PF11, GPIO_PF10, GPIO_PF9, GPIO_PF8,
GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
/* Port G */
GPIO_PG27, GPIO_PG26, GPIO_PG25, GPIO_PG24,
GPIO_PG23, GPIO_PG22, GPIO_PG21, GPIO_PG20,
GPIO_PG19, GPIO_PG18, GPIO_PG17, GPIO_PG16,
GPIO_PG15, GPIO_PG14, GPIO_PG13, GPIO_PG12,
GPIO_PG11, GPIO_PG10, GPIO_PG9, GPIO_PG8,
GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
/* Port H */
GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
/* Port I - not on device */
/* Port J */
GPIO_PJ31, GPIO_PJ30, GPIO_PJ29, GPIO_PJ28,
GPIO_PJ27, GPIO_PJ26, GPIO_PJ25, GPIO_PJ24,
GPIO_PJ23, GPIO_PJ22, GPIO_PJ21, GPIO_PJ20,
GPIO_PJ19, GPIO_PJ18, GPIO_PJ17, GPIO_PJ16,
GPIO_PJ15, GPIO_PJ14, GPIO_PJ13, GPIO_PJ12,
GPIO_PJ11, GPIO_PJ10, GPIO_PJ9, GPIO_PJ8,
GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
/* INTC: IRQ and PINT */
GPIO_FN_IRQ7_PG, GPIO_FN_IRQ6_PG, GPIO_FN_IRQ5_PG, GPIO_FN_IRQ4_PG,
GPIO_FN_IRQ3_PG, GPIO_FN_IRQ2_PG, GPIO_FN_IRQ1_PG, GPIO_FN_IRQ0_PG,
GPIO_FN_IRQ7_PF, GPIO_FN_IRQ6_PF, GPIO_FN_IRQ5_PF, GPIO_FN_IRQ4_PF,
GPIO_FN_IRQ3_PJ, GPIO_FN_IRQ2_PJ, GPIO_FN_IRQ1_PJ, GPIO_FN_IRQ0_PJ,
GPIO_FN_IRQ1_PC, GPIO_FN_IRQ0_PC,
GPIO_FN_PINT7_PG, GPIO_FN_PINT6_PG, GPIO_FN_PINT5_PG, GPIO_FN_PINT4_PG,
GPIO_FN_PINT3_PG, GPIO_FN_PINT2_PG, GPIO_FN_PINT1_PG, GPIO_FN_PINT0_PG,
GPIO_FN_PINT7_PH, GPIO_FN_PINT6_PH, GPIO_FN_PINT5_PH, GPIO_FN_PINT4_PH,
GPIO_FN_PINT3_PH, GPIO_FN_PINT2_PH, GPIO_FN_PINT1_PH, GPIO_FN_PINT0_PH,
GPIO_FN_PINT7_PJ, GPIO_FN_PINT6_PJ, GPIO_FN_PINT5_PJ, GPIO_FN_PINT4_PJ,
GPIO_FN_PINT3_PJ, GPIO_FN_PINT2_PJ, GPIO_FN_PINT1_PJ, GPIO_FN_PINT0_PJ,
/* WDT */
GPIO_FN_WDTOVF,
/* CAN */
GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,
GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, GPIO_FN_CRX0_CRX1_CRX2,
/* DMAC */
GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,
GPIO_FN_TEND1, GPIO_FN_DACK1, GPIO_FN_DREQ1,
/* ADC */
GPIO_FN_ADTRG,
/* BSC */
GPIO_FN_A25, GPIO_FN_A24,
GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
GPIO_FN_BS,
GPIO_FN_CS4, GPIO_FN_CS3, GPIO_FN_CS2, GPIO_FN_CS1, GPIO_FN_CS0,
GPIO_FN_CS5CE1A,
GPIO_FN_CE2A, GPIO_FN_CE2B,
GPIO_FN_RD, GPIO_FN_RDWR,
GPIO_FN_WE3ICIOWRAHDQMUU, GPIO_FN_WE2ICIORDDQMUL,
GPIO_FN_WE1DQMUWE, GPIO_FN_WE0DQML,
GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE,
GPIO_FN_WAIT, GPIO_FN_BREQ, GPIO_FN_BACK,
GPIO_FN_IOIS16,
/* TMU */
GPIO_FN_TIOC4D, GPIO_FN_TIOC4C, GPIO_FN_TIOC4B, GPIO_FN_TIOC4A,
GPIO_FN_TIOC3D, GPIO_FN_TIOC3C, GPIO_FN_TIOC3B, GPIO_FN_TIOC3A,
GPIO_FN_TIOC2B, GPIO_FN_TIOC1B, GPIO_FN_TIOC2A, GPIO_FN_TIOC1A,
GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
/* SSU */
GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
/* SCIF */
GPIO_FN_SCK0, GPIO_FN_RXD0, GPIO_FN_TXD0,
GPIO_FN_SCK1, GPIO_FN_RXD1, GPIO_FN_TXD1, GPIO_FN_RTS1, GPIO_FN_CTS1,
GPIO_FN_SCK2, GPIO_FN_RXD2, GPIO_FN_TXD2,
GPIO_FN_SCK3, GPIO_FN_RXD3, GPIO_FN_TXD3,
GPIO_FN_SCK4, GPIO_FN_RXD4, GPIO_FN_TXD4,
GPIO_FN_SCK5, GPIO_FN_RXD5, GPIO_FN_TXD5, GPIO_FN_RTS5, GPIO_FN_CTS5,
GPIO_FN_SCK6, GPIO_FN_RXD6, GPIO_FN_TXD6,
GPIO_FN_SCK7, GPIO_FN_RXD7, GPIO_FN_TXD7, GPIO_FN_RTS7, GPIO_FN_CTS7,
/* RSPI */
GPIO_FN_MISO0_PJ19, GPIO_FN_MISO0_PB20,
GPIO_FN_MOSI0_PJ18, GPIO_FN_MOSI0_PB19,
GPIO_FN_SSL00_PJ17, GPIO_FN_SSL00_PB18,
GPIO_FN_RSPCK0_PJ16, GPIO_FN_RSPCK0_PB17,
GPIO_FN_RSPCK1, GPIO_FN_MOSI1,
GPIO_FN_MISO1, GPIO_FN_SSL10,
/* IIC3 */
GPIO_FN_SCL0, GPIO_FN_SCL1, GPIO_FN_SCL2,
GPIO_FN_SDA2, GPIO_FN_SDA1, GPIO_FN_SDA0,
/* SSI */
GPIO_FN_SSISCK0, GPIO_FN_SSIWS0, GPIO_FN_SSITXD0, GPIO_FN_SSIRXD0,
GPIO_FN_SSIWS1, GPIO_FN_SSIWS2, GPIO_FN_SSIWS3,
GPIO_FN_SSISCK1, GPIO_FN_SSISCK2, GPIO_FN_SSISCK3,
GPIO_FN_SSIDATA1, GPIO_FN_SSIDATA2, GPIO_FN_SSIDATA3,
GPIO_FN_AUDIO_CLK,
GPIO_FN_AUDIO_XOUT,
/* SIOF */
GPIO_FN_SIOFTXD, GPIO_FN_SIOFRXD, GPIO_FN_SIOFSYNC, GPIO_FN_SIOFSCK,
/* SPDIF */
GPIO_FN_SPDIF_IN,
GPIO_FN_SPDIF_OUT,
/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
GPIO_FN_FCE,
GPIO_FN_FRB,
/* VDC */
GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC,
GPIO_FN_DV_DATA23, GPIO_FN_DV_DATA22,
GPIO_FN_DV_DATA21, GPIO_FN_DV_DATA20,
GPIO_FN_DV_DATA19, GPIO_FN_DV_DATA18,
GPIO_FN_DV_DATA17, GPIO_FN_DV_DATA16,
GPIO_FN_DV_DATA15, GPIO_FN_DV_DATA14,
GPIO_FN_DV_DATA13, GPIO_FN_DV_DATA12,
GPIO_FN_DV_DATA11, GPIO_FN_DV_DATA10,
GPIO_FN_DV_DATA9, GPIO_FN_DV_DATA8,
GPIO_FN_DV_DATA7, GPIO_FN_DV_DATA6,
GPIO_FN_DV_DATA5, GPIO_FN_DV_DATA4,
GPIO_FN_DV_DATA3, GPIO_FN_DV_DATA2,
GPIO_FN_DV_DATA1, GPIO_FN_DV_DATA0,
GPIO_FN_LCD_CLK, GPIO_FN_LCD_EXTCLK,
GPIO_FN_LCD_VSYNC, GPIO_FN_LCD_HSYNC, GPIO_FN_LCD_DE,
GPIO_FN_LCD_DATA23, GPIO_FN_LCD_DATA22,
GPIO_FN_LCD_DATA21, GPIO_FN_LCD_DATA20,
GPIO_FN_LCD_DATA19, GPIO_FN_LCD_DATA18,
GPIO_FN_LCD_DATA17, GPIO_FN_LCD_DATA16,
GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14,
GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12,
GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10,
GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8,
GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6,
GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4,
GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2,
GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0,
GPIO_FN_LCD_M_DISP,
};
#endif /* __ASM_SH7269_H__ */

13
arch/sh/include/cpu-sh3/cpu/dma.h
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@ -1,6 +1,8 @@
#ifndef __ASM_CPU_SH3_DMA_H
#define __ASM_CPU_SH3_DMA_H
#include <linux/sh_intc.h>
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
defined(CONFIG_CPU_SUBTYPE_SH7710) || \
@ -10,14 +12,7 @@
#define SH_DMAC_BASE0 0xa4000020
#endif
#define DMTE0_IRQ 48
#define DMTE4_IRQ 76
/* Definitions for the SuperH DMAC */
#define TM_BURST 0x00000020
#define TS_8 0x00000000
#define TS_16 0x00000008
#define TS_32 0x00000010
#define TS_128 0x00000018
#define DMTE0_IRQ evt2irq(0x800)
#define DMTE4_IRQ evt2irq(0xb80)
#endif /* __ASM_CPU_SH3_DMA_H */

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arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
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@ -1,83 +0,0 @@
#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
#define __ASM_SH_CPU_SH4_DMA_SH7780_H
#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
defined(CONFIG_CPU_SUBTYPE_SH7730)
#define DMTE0_IRQ 48
#define DMTE4_IRQ 76
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
#define SH_DMAC_BASE0 0xFE008020
#define SH_DMARS_BASE0 0xFE009000
#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
#define DMTE0_IRQ 48
#define DMTE4_IRQ 76
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
#define SH_DMAC_BASE0 0xFE008020
#define SH_DMARS_BASE0 0xFE009000
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7764)
#define DMTE0_IRQ 34
#define DMTE4_IRQ 44
#define DMAE0_IRQ 38
#define SH_DMAC_BASE0 0xFF608020
#define SH_DMARS_BASE0 0xFF609000
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
#define DMTE0_IRQ 48 /* DMAC0A*/
#define DMTE4_IRQ 76 /* DMAC0B */
#define DMTE6_IRQ 40
#define DMTE8_IRQ 42 /* DMAC1A */
#define DMTE9_IRQ 43
#define DMTE10_IRQ 72 /* DMAC1B */
#define DMTE11_IRQ 73
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
#define DMAE1_IRQ 74 /* DMA Error IRQ*/
#define SH_DMAC_BASE0 0xFE008020
#define SH_DMAC_BASE1 0xFDC08020
#define SH_DMARS_BASE0 0xFDC09000
#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
#define DMTE0_IRQ 48 /* DMAC0A*/
#define DMTE4_IRQ 76 /* DMAC0B */
#define DMTE6_IRQ 40
#define DMTE8_IRQ 42 /* DMAC1A */
#define DMTE9_IRQ 43
#define DMTE10_IRQ 72 /* DMAC1B */
#define DMTE11_IRQ 73
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
#define DMAE1_IRQ 74 /* DMA Error IRQ*/
#define SH_DMAC_BASE0 0xFE008020
#define SH_DMAC_BASE1 0xFDC08020
#define SH_DMARS_BASE0 0xFE009000
#define SH_DMARS_BASE1 0xFDC09000
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
#define DMTE0_IRQ 34
#define DMTE4_IRQ 44
#define DMTE6_IRQ 46
#define DMTE8_IRQ 92
#define DMTE9_IRQ 93
#define DMTE10_IRQ 94
#define DMTE11_IRQ 95
#define DMAE0_IRQ 38 /* DMA Error IRQ */
#define SH_DMAC_BASE0 0xFC808020
#define SH_DMAC_BASE1 0xFC818020
#define SH_DMARS_BASE0 0xFC809000
#else /* SH7785 */
#define DMTE0_IRQ 33
#define DMTE4_IRQ 37
#define DMTE6_IRQ 52
#define DMTE8_IRQ 54
#define DMTE9_IRQ 55
#define DMTE10_IRQ 56
#define DMTE11_IRQ 57
#define DMAE0_IRQ 39 /* DMA Error IRQ0 */
#define DMAE1_IRQ 58 /* DMA Error IRQ1 */
#define SH_DMAC_BASE0 0xFC808020
#define SH_DMAC_BASE1 0xFCC08020
#define SH_DMARS_BASE0 0xFC809000
#endif
#define REQ_HE 0x000000C0
#define REQ_H 0x00000080
#define REQ_LE 0x00000040
#define TM_BURST 0x00000020
#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */

25
arch/sh/include/cpu-sh4/cpu/dma.h
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@ -1,32 +1,17 @@
#ifndef __ASM_CPU_SH4_DMA_H
#define __ASM_CPU_SH4_DMA_H
/* SH7751/7760/7780 DMA IRQ sources */
#include <linux/sh_intc.h>
#ifdef CONFIG_CPU_SH4A
#include <cpu/dma-sh4a.h>
#else /* CONFIG_CPU_SH4A */
/*
* SH7750/SH7751/SH7760
*/
#define DMTE0_IRQ 34
#define DMTE4_IRQ 44
#define DMTE6_IRQ 46
#define DMAE0_IRQ 38
#define DMTE0_IRQ evt2irq(0x640)
#define DMTE4_IRQ evt2irq(0x780)
#define DMTE6_IRQ evt2irq(0x7c0)
#define DMAE0_IRQ evt2irq(0x6c0)
#define SH_DMAC_BASE0 0xffa00000
#define SH_DMAC_BASE1 0xffa00070
/* Definitions for the SuperH DMAC */
#define TM_BURST 0x00000080
#define TS_8 0x00000010
#define TS_16 0x00000020
#define TS_32 0x00000030
#define TS_64 0x00000000
#define DMAOR_COD 0x00000008
#endif
#endif /* __ASM_CPU_SH4_DMA_H */

5
arch/sh/include/cpu-sh4/cpu/freq.h
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@ -47,6 +47,11 @@
#define MSTPCR1 0xa4150034
#define MSTPCR2 0xa4150038
#elif defined(CONFIG_CPU_SUBTYPE_SH7734)
#define FRQCR0 0xffc80000
#define FRQCR2 0xffc80008
#define FRQMR1 0xffc80014
#define FRQMR2 0xffc80018
#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
#define FRQCR0 0xffc80000
#define FRQCR1 0xffc80004

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arch/sh/include/cpu-sh4/cpu/sh7734.h Normal file
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#ifndef __ASM_SH7734_H__
#define __ASM_SH7734_H__
/* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
* GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
*/
enum {
GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
GPIO_FN_CLKOUT, GPIO_FN_BS, GPIO_FN_CS0, GPIO_FN_EX_CS0, GPIO_FN_RD,
GPIO_FN_WE0, GPIO_FN_WE1,
GPIO_FN_SCL0, GPIO_FN_PENC0, GPIO_FN_USB_OVC0,
GPIO_FN_IRQ2_B, GPIO_FN_IRQ3_B,
/* IPSR0 */
GPIO_FN_A15, GPIO_FN_ST0_VCO_CLKIN, GPIO_FN_LCD_DATA15_A,
GPIO_FN_TIOC3D_C,
GPIO_FN_A14, GPIO_FN_LCD_DATA14_A, GPIO_FN_TIOC3C_C,
GPIO_FN_A13, GPIO_FN_LCD_DATA13_A, GPIO_FN_TIOC3B_C,
GPIO_FN_A12, GPIO_FN_LCD_DATA12_A, GPIO_FN_TIOC3A_C,
GPIO_FN_A11, GPIO_FN_ST0_D7, GPIO_FN_LCD_DATA11_A,
GPIO_FN_TIOC2B_C,
GPIO_FN_A10, GPIO_FN_ST0_D6, GPIO_FN_LCD_DATA10_A,
GPIO_FN_TIOC2A_C,
GPIO_FN_A9, GPIO_FN_ST0_D5, GPIO_FN_LCD_DATA9_A,
GPIO_FN_TIOC1B_C,
GPIO_FN_A8, GPIO_FN_ST0_D4, GPIO_FN_LCD_DATA8_A,
GPIO_FN_TIOC1A_C,
GPIO_FN_A7, GPIO_FN_ST0_D3, GPIO_FN_LCD_DATA7_A, GPIO_FN_TIOC0D_C,
GPIO_FN_A6, GPIO_FN_ST0_D2, GPIO_FN_LCD_DATA6_A, GPIO_FN_TIOC0C_C,
GPIO_FN_A5, GPIO_FN_ST0_D1, GPIO_FN_LCD_DATA5_A, GPIO_FN_TIOC0B_C,
GPIO_FN_A4, GPIO_FN_ST0_D0, GPIO_FN_LCD_DATA4_A, GPIO_FN_TIOC0A_C,
GPIO_FN_A3, GPIO_FN_ST0_VLD, GPIO_FN_LCD_DATA3_A, GPIO_FN_TCLKD_C,
GPIO_FN_A2, GPIO_FN_ST0_SYC, GPIO_FN_LCD_DATA2_A, GPIO_FN_TCLKC_C,
GPIO_FN_A1, GPIO_FN_ST0_REQ, GPIO_FN_LCD_DATA1_A, GPIO_FN_TCLKB_C,
GPIO_FN_A0, GPIO_FN_ST0_CLKIN, GPIO_FN_LCD_DATA0_A, GPIO_FN_TCLKA_C,
/* IPSR1 */
GPIO_FN_D3, GPIO_FN_SD0_DAT3_A, GPIO_FN_MMC_D3_A, GPIO_FN_ST1_D6,
GPIO_FN_FD3_A,
GPIO_FN_D2, GPIO_FN_SD0_DAT2_A, GPIO_FN_MMC_D2_A, GPIO_FN_ST1_D5,
GPIO_FN_FD2_A,
GPIO_FN_D1, GPIO_FN_SD0_DAT1_A, GPIO_FN_MMC_D1_A, GPIO_FN_ST1_D4,
GPIO_FN_FD1_A,
GPIO_FN_D0, GPIO_FN_SD0_DAT0_A, GPIO_FN_MMC_D0_A, GPIO_FN_ST1_D3,
GPIO_FN_FD0_A,
GPIO_FN_A25, GPIO_FN_TX2_D, GPIO_FN_ST1_D2,
GPIO_FN_A24, GPIO_FN_RX2_D, GPIO_FN_ST1_D1,
GPIO_FN_A23, GPIO_FN_ST1_D0, GPIO_FN_LCD_M_DISP_A,
GPIO_FN_A22, GPIO_FN_ST1_VLD, GPIO_FN_LCD_VEPWC_A,
GPIO_FN_A21, GPIO_FN_ST1_SYC, GPIO_FN_LCD_VCPWC_A,
GPIO_FN_A20, GPIO_FN_ST1_REQ, GPIO_FN_LCD_FLM_A,
GPIO_FN_A19, GPIO_FN_ST1_CLKIN, GPIO_FN_LCD_CLK_A, GPIO_FN_TIOC4D_C,
GPIO_FN_A18, GPIO_FN_ST1_PWM, GPIO_FN_LCD_CL2_A, GPIO_FN_TIOC4C_C,
GPIO_FN_A17, GPIO_FN_ST1_VCO_CLKIN, GPIO_FN_LCD_CL1_A, GPIO_FN_TIOC4B_C,
GPIO_FN_A16, GPIO_FN_ST0_PWM, GPIO_FN_LCD_DON_A, GPIO_FN_TIOC4A_C,
/* IPSR2 */
GPIO_FN_D14, GPIO_FN_TX2_B, GPIO_FN_FSE_A, GPIO_FN_ET0_TX_CLK_B,
GPIO_FN_D13, GPIO_FN_RX2_B, GPIO_FN_FRB_A, GPIO_FN_ET0_ETXD6_B,
GPIO_FN_D12, GPIO_FN_FWE_A, GPIO_FN_ET0_ETXD5_B,
GPIO_FN_D11, GPIO_FN_RSPI_MISO_A, GPIO_FN_QMI_QIO1_A,
GPIO_FN_FRE_A, GPIO_FN_ET0_ETXD3_B,
GPIO_FN_D10, GPIO_FN_RSPI_MOSI_A, GPIO_FN_QMO_QIO0_A,
GPIO_FN_FALE_A, GPIO_FN_ET0_ETXD2_B,
GPIO_FN_D9, GPIO_FN_SD0_CMD_A, GPIO_FN_MMC_CMD_A, GPIO_FN_QIO3_A,
GPIO_FN_FCLE_A, GPIO_FN_ET0_ETXD1_B,
GPIO_FN_D8, GPIO_FN_SD0_CLK_A, GPIO_FN_MMC_CLK_A, GPIO_FN_QIO2_A,
GPIO_FN_FCE_A, GPIO_FN_ET0_GTX_CLK_B,
GPIO_FN_D7, GPIO_FN_RSPI_SSL_A, GPIO_FN_MMC_D7_A, GPIO_FN_QSSL_A,
GPIO_FN_FD7_A,
GPIO_FN_D6, GPIO_FN_RSPI_RSPCK_A, GPIO_FN_MMC_D6_A, GPIO_FN_QSPCLK_A,
GPIO_FN_FD6_A,
GPIO_FN_D5, GPIO_FN_SD0_WP_A, GPIO_FN_MMC_D5_A, GPIO_FN_FD5_A,
GPIO_FN_D4, GPIO_FN_SD0_CD_A, GPIO_FN_MMC_D4_A, GPIO_FN_ST1_D7,
GPIO_FN_FD4_A,
/* IPSR3 */
GPIO_FN_DRACK0, GPIO_FN_SD1_DAT2_A, GPIO_FN_ATAG, GPIO_FN_TCLK1_A,
GPIO_FN_ET0_ETXD7,
GPIO_FN_EX_WAIT2, GPIO_FN_SD1_DAT1_A, GPIO_FN_DACK2, GPIO_FN_CAN1_RX_C,
GPIO_FN_ET0_MAGIC_C, GPIO_FN_ET0_ETXD6_A,
GPIO_FN_EX_WAIT1, GPIO_FN_SD1_DAT0_A, GPIO_FN_DREQ2, GPIO_FN_CAN1_TX_C,
GPIO_FN_ET0_LINK_C, GPIO_FN_ET0_ETXD5_A,
GPIO_FN_EX_WAIT0, GPIO_FN_TCLK1_B,
GPIO_FN_RD_WR, GPIO_FN_TCLK0,
GPIO_FN_EX_CS5, GPIO_FN_SD1_CMD_A, GPIO_FN_ATADIR, GPIO_FN_QSSL_B,
GPIO_FN_ET0_ETXD3_A,
GPIO_FN_EX_CS4, GPIO_FN_SD1_WP_A, GPIO_FN_ATAWR, GPIO_FN_QMI_QIO1_B,
GPIO_FN_ET0_ETXD2_A,
GPIO_FN_EX_CS3, GPIO_FN_SD1_CD_A, GPIO_FN_ATARD, GPIO_FN_QMO_QIO0_B,
GPIO_FN_ET0_ETXD1_A,
GPIO_FN_EX_CS2, GPIO_FN_TX3_B, GPIO_FN_ATACS1, GPIO_FN_QSPCLK_B,
GPIO_FN_ET0_GTX_CLK_A,
GPIO_FN_EX_CS1, GPIO_FN_RX3_B, GPIO_FN_ATACS0, GPIO_FN_QIO2_B,
GPIO_FN_ET0_ETXD0,
GPIO_FN_CS1_A26, GPIO_FN_QIO3_B,
GPIO_FN_D15, GPIO_FN_SCK2_B,
/* IPSR4 */
GPIO_FN_SCK2_A, GPIO_FN_VI0_G3,
GPIO_FN_RTS1_B, GPIO_FN_VI0_G2,
GPIO_FN_CTS1_B, GPIO_FN_VI0_DATA7_VI0_G1,
GPIO_FN_TX1_B, GPIO_FN_VI0_DATA6_VI0_G0, GPIO_FN_ET0_PHY_INT_A,
GPIO_FN_RX1_B, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_ET0_MAGIC_A,
GPIO_FN_SCK1_B, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ET0_LINK_A,
GPIO_FN_RTS0_B, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ET0_MDIO_A,
GPIO_FN_CTS0_B, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_RMII0_MDIO_A,
GPIO_FN_ET0_MDC,
GPIO_FN_HTX0_A, GPIO_FN_TX1_A, GPIO_FN_VI0_DATA1_VI0_B1,
GPIO_FN_RMII0_MDC_A, GPIO_FN_ET0_COL,
GPIO_FN_HRX0_A, GPIO_FN_RX1_A, GPIO_FN_VI0_DATA0_VI0_B0,
GPIO_FN_RMII0_CRS_DV_A, GPIO_FN_ET0_CRS,
GPIO_FN_HSCK0_A, GPIO_FN_SCK1_A, GPIO_FN_VI0_VSYNC,
GPIO_FN_RMII0_RX_ER_A, GPIO_FN_ET0_RX_ER,
GPIO_FN_HRTS0_A, GPIO_FN_RTS1_A, GPIO_FN_VI0_HSYNC,
GPIO_FN_RMII0_TXD_EN_A, GPIO_FN_ET0_RX_DV,
GPIO_FN_HCTS0_A, GPIO_FN_CTS1_A, GPIO_FN_VI0_FIELD,
GPIO_FN_RMII0_RXD1_A, GPIO_FN_ET0_ERXD7,
/* IPSR5 */
GPIO_FN_SD2_CLK_A, GPIO_FN_RX2_A, GPIO_FN_VI0_G4, GPIO_FN_ET0_RX_CLK_B,
GPIO_FN_SD2_CMD_A, GPIO_FN_TX2_A, GPIO_FN_VI0_G5, GPIO_FN_ET0_ERXD2_B,
GPIO_FN_SD2_DAT0_A, GPIO_FN_RX3_A, GPIO_FN_VI0_R0, GPIO_FN_ET0_ERXD3_B,
GPIO_FN_SD2_DAT1_A, GPIO_FN_TX3_A, GPIO_FN_VI0_R1, GPIO_FN_ET0_MDIO_B,
GPIO_FN_SD2_DAT2_A, GPIO_FN_RX4_A, GPIO_FN_VI0_R2, GPIO_FN_ET0_LINK_B,
GPIO_FN_SD2_DAT3_A, GPIO_FN_TX4_A, GPIO_FN_VI0_R3, GPIO_FN_ET0_MAGIC_B,
GPIO_FN_SD2_CD_A, GPIO_FN_RX5_A, GPIO_FN_VI0_R4, GPIO_FN_ET0_PHY_INT_B,
GPIO_FN_SD2_WP_A, GPIO_FN_TX5_A, GPIO_FN_VI0_R5,
GPIO_FN_REF125CK, GPIO_FN_ADTRG, GPIO_FN_RX5_C,
GPIO_FN_REF50CK, GPIO_FN_CTS1_E, GPIO_FN_HCTS0_D,
/* IPSR6 */
GPIO_FN_DU0_DR0, GPIO_FN_SCIF_CLK_B, GPIO_FN_HRX0_D, GPIO_FN_IETX_A,
GPIO_FN_TCLKA_A, GPIO_FN_HIFD00,
GPIO_FN_DU0_DR1, GPIO_FN_SCK0_B, GPIO_FN_HTX0_D, GPIO_FN_IERX_A,
GPIO_FN_TCLKB_A, GPIO_FN_HIFD01,
GPIO_FN_DU0_DR2, GPIO_FN_RX0_B, GPIO_FN_TCLKC_A, GPIO_FN_HIFD02,
GPIO_FN_DU0_DR3, GPIO_FN_TX0_B, GPIO_FN_TCLKD_A, GPIO_FN_HIFD03,
GPIO_FN_DU0_DR4, GPIO_FN_CTS0_C, GPIO_FN_TIOC0A_A, GPIO_FN_HIFD04,
GPIO_FN_DU0_DR5, GPIO_FN_RTS0_C, GPIO_FN_TIOC0B_A, GPIO_FN_HIFD05,
GPIO_FN_DU0_DR6, GPIO_FN_SCK1_C, GPIO_FN_TIOC0C_A, GPIO_FN_HIFD06,
GPIO_FN_DU0_DR7, GPIO_FN_RX1_C, GPIO_FN_TIOC0D_A, GPIO_FN_HIFD07,
GPIO_FN_DU0_DG0, GPIO_FN_TX1_C, GPIO_FN_HSCK0_D, GPIO_FN_IECLK_A,
GPIO_FN_TIOC1A_A, GPIO_FN_HIFD08,
GPIO_FN_DU0_DG1, GPIO_FN_CTS1_C, GPIO_FN_HRTS0_D, GPIO_FN_TIOC1B_A,
GPIO_FN_HIFD09,
/* IPSR7 */
GPIO_FN_DU0_DG2, GPIO_FN_RTS1_C, GPIO_FN_RMII0_MDC_B, GPIO_FN_TIOC2A_A,
GPIO_FN_HIFD10,
GPIO_FN_DU0_DG3, GPIO_FN_SCK2_C, GPIO_FN_RMII0_MDIO_B, GPIO_FN_TIOC2B_A,
GPIO_FN_HIFD11,
GPIO_FN_DU0_DG4, GPIO_FN_RX2_C, GPIO_FN_RMII0_CRS_DV_B,
GPIO_FN_TIOC3A_A, GPIO_FN_HIFD12,
GPIO_FN_DU0_DG5, GPIO_FN_TX2_C, GPIO_FN_RMII0_RX_ER_B,
GPIO_FN_TIOC3B_A, GPIO_FN_HIFD13,
GPIO_FN_DU0_DG6, GPIO_FN_RX3_C, GPIO_FN_RMII0_RXD0_B,
GPIO_FN_TIOC3C_A, GPIO_FN_HIFD14,
GPIO_FN_DU0_DG7, GPIO_FN_TX3_C, GPIO_FN_RMII0_RXD1_B,
GPIO_FN_TIOC3D_A, GPIO_FN_HIFD15,
GPIO_FN_DU0_DB0, GPIO_FN_RX4_C, GPIO_FN_RMII0_TXD_EN_B,
GPIO_FN_TIOC4A_A, GPIO_FN_HIFCS,
GPIO_FN_DU0_DB1, GPIO_FN_TX4_C, GPIO_FN_RMII0_TXD0_B,
GPIO_FN_TIOC4B_A, GPIO_FN_HIFRS,
GPIO_FN_DU0_DB2, GPIO_FN_RX5_B, GPIO_FN_RMII0_TXD1_B,
GPIO_FN_TIOC4C_A, GPIO_FN_HIFWR,
GPIO_FN_DU0_DB3, GPIO_FN_TX5_B, GPIO_FN_TIOC4D_A, GPIO_FN_HIFRD,
GPIO_FN_DU0_DB4, GPIO_FN_HIFINT,
/* IPSR8 */
GPIO_FN_DU0_DB5, GPIO_FN_HIFDREQ,
GPIO_FN_DU0_DB6, GPIO_FN_HIFRDY,
GPIO_FN_DU0_DB7, GPIO_FN_SSI_SCK0_B, GPIO_FN_HIFEBL_B,
GPIO_FN_DU0_DOTCLKIN, GPIO_FN_HSPI_CS0_C, GPIO_FN_SSI_WS0_B,
GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_HSPI_CLK0_C, GPIO_FN_SSI_SDATA0_B,
GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_HSPI_TX0_C, GPIO_FN_SSI_SCK1_B,
GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_HSPI_RX0_C, GPIO_FN_SSI_WS1_B,
GPIO_FN_DU0_EXODDF_DU0_ODDF, GPIO_FN_CAN0_RX_B, GPIO_FN_HSCK0_B,
GPIO_FN_SSI_SDATA1_B,
GPIO_FN_DU0_DISP, GPIO_FN_CAN0_TX_B, GPIO_FN_HRX0_B,
GPIO_FN_AUDIO_CLKA_B,
GPIO_FN_DU0_CDE, GPIO_FN_HTX0_B, GPIO_FN_AUDIO_CLKB_B,
GPIO_FN_LCD_VCPWC_B,
GPIO_FN_IRQ0_A, GPIO_FN_HSPI_TX_B, GPIO_FN_RX3_E, GPIO_FN_ET0_ERXD0,
GPIO_FN_IRQ1_A, GPIO_FN_HSPI_RX_B, GPIO_FN_TX3_E, GPIO_FN_ET0_ERXD1,
GPIO_FN_IRQ2_A, GPIO_FN_CTS0_A, GPIO_FN_HCTS0_B, GPIO_FN_ET0_ERXD2_A,
GPIO_FN_IRQ3_A, GPIO_FN_RTS0_A, GPIO_FN_HRTS0_B, GPIO_FN_ET0_ERXD3_A,
/* IPSR9 */
GPIO_FN_VI1_CLK_A, GPIO_FN_FD0_B, GPIO_FN_LCD_DATA0_B,
GPIO_FN_VI1_0_A, GPIO_FN_FD1_B, GPIO_FN_LCD_DATA1_B,
GPIO_FN_VI1_1_A, GPIO_FN_FD2_B, GPIO_FN_LCD_DATA2_B,
GPIO_FN_VI1_2_A, GPIO_FN_FD3_B, GPIO_FN_LCD_DATA3_B,
GPIO_FN_VI1_3_A, GPIO_FN_FD4_B, GPIO_FN_LCD_DATA4_B,
GPIO_FN_VI1_4_A, GPIO_FN_FD5_B, GPIO_FN_LCD_DATA5_B,
GPIO_FN_VI1_5_A, GPIO_FN_FD6_B, GPIO_FN_LCD_DATA6_B,
GPIO_FN_VI1_6_A, GPIO_FN_FD7_B, GPIO_FN_LCD_DATA7_B,
GPIO_FN_VI1_7_A, GPIO_FN_FCE_B, GPIO_FN_LCD_DATA8_B,
GPIO_FN_SSI_SCK0_A, GPIO_FN_TIOC1A_B, GPIO_FN_LCD_DATA9_B,
GPIO_FN_SSI_WS0_A, GPIO_FN_TIOC1B_B, GPIO_FN_LCD_DATA10_B,
GPIO_FN_SSI_SDATA0_A, GPIO_FN_VI1_0_B, GPIO_FN_TIOC2A_B,
GPIO_FN_LCD_DATA11_B,
GPIO_FN_SSI_SCK1_A, GPIO_FN_VI1_1_B, GPIO_FN_TIOC2B_B,
GPIO_FN_LCD_DATA12_B,
GPIO_FN_SSI_WS1_A, GPIO_FN_VI1_2_B, GPIO_FN_LCD_DATA13_B,
GPIO_FN_SSI_SDATA1_A, GPIO_FN_VI1_3_B, GPIO_FN_LCD_DATA14_B,
/* IPSR10 */
GPIO_FN_SSI_SCK23, GPIO_FN_VI1_4_B, GPIO_FN_RX1_D, GPIO_FN_FCLE_B,
GPIO_FN_LCD_DATA15_B,
GPIO_FN_SSI_WS23, GPIO_FN_VI1_5_B, GPIO_FN_TX1_D, GPIO_FN_HSCK0_C,
GPIO_FN_FALE_B, GPIO_FN_LCD_DON_B,
GPIO_FN_SSI_SDATA2, GPIO_FN_VI1_6_B, GPIO_FN_HRX0_C, GPIO_FN_FRE_B,
GPIO_FN_LCD_CL1_B,
GPIO_FN_SSI_SDATA3, GPIO_FN_VI1_7_B, GPIO_FN_HTX0_C, GPIO_FN_FWE_B,
GPIO_FN_LCD_CL2_B,
GPIO_FN_AUDIO_CLKA_A, GPIO_FN_VI1_CLK_B, GPIO_FN_SCK1_D,
GPIO_FN_IECLK_B, GPIO_FN_LCD_FLM_B,
GPIO_FN_AUDIO_CLKB_A, GPIO_FN_LCD_CLK_B,
GPIO_FN_AUDIO_CLKC, GPIO_FN_SCK1_E, GPIO_FN_HCTS0_C, GPIO_FN_FRB_B,
GPIO_FN_LCD_VEPWC_B,
GPIO_FN_AUDIO_CLKOUT, GPIO_FN_TX1_E, GPIO_FN_HRTS0_C, GPIO_FN_FSE_B,
GPIO_FN_LCD_M_DISP_B,
GPIO_FN_CAN_CLK_A, GPIO_FN_RX4_D,
GPIO_FN_CAN0_TX_A, GPIO_FN_TX4_D, GPIO_FN_MLB_CLK,
GPIO_FN_CAN1_RX_A, GPIO_FN_IRQ1_B,
GPIO_FN_CAN0_RX_A, GPIO_FN_IRQ0_B, GPIO_FN_MLB_SIG,
GPIO_FN_CAN1_TX_A, GPIO_FN_TX5_C, GPIO_FN_MLB_DAT,
/* IPSR11 */
GPIO_FN_SCL1, GPIO_FN_SCIF_CLK_C,
GPIO_FN_SDA1, GPIO_FN_RX1_E,
GPIO_FN_SDA0, GPIO_FN_HIFEBL_A,
GPIO_FN_SDSELF, GPIO_FN_RTS1_E,
GPIO_FN_SCIF_CLK_A, GPIO_FN_HSPI_CLK_A, GPIO_FN_VI0_CLK,
GPIO_FN_RMII0_TXD0_A, GPIO_FN_ET0_ERXD4,
GPIO_FN_SCK0_A, GPIO_FN_HSPI_CS_A, GPIO_FN_VI0_CLKENB,
GPIO_FN_RMII0_TXD1_A, GPIO_FN_ET0_ERXD5,
GPIO_FN_RX0_A, GPIO_FN_HSPI_RX_A, GPIO_FN_RMII0_RXD0_A,
GPIO_FN_ET0_ERXD6,
GPIO_FN_TX0_A, GPIO_FN_HSPI_TX_A,
GPIO_FN_PENC1, GPIO_FN_TX3_D, GPIO_FN_CAN1_TX_B, GPIO_FN_TX5_D,
GPIO_FN_IETX_B,
GPIO_FN_USB_OVC1, GPIO_FN_RX3_D, GPIO_FN_CAN1_RX_B, GPIO_FN_RX5_D,
GPIO_FN_IERX_B,
GPIO_FN_DREQ0, GPIO_FN_SD1_CLK_A, GPIO_FN_ET0_TX_EN,
GPIO_FN_DACK0, GPIO_FN_SD1_DAT3_A, GPIO_FN_ET0_TX_ER,
GPIO_FN_DREQ1, GPIO_FN_HSPI_CLK_B, GPIO_FN_RX4_B, GPIO_FN_ET0_PHY_INT_C,
GPIO_FN_ET0_TX_CLK_A,
GPIO_FN_DACK1, GPIO_FN_HSPI_CS_B, GPIO_FN_TX4_B, GPIO_FN_ET0_RX_CLK_A,
GPIO_FN_PRESETOUT, GPIO_FN_ST_CLKOUT,
};
#endif /* __ASM_SH7734_H__ */

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arch/sh/include/cpu-sh4a/cpu/dma.h Normal file
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#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
#define __ASM_SH_CPU_SH4_DMA_SH7780_H
#include <linux/sh_intc.h>
#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
defined(CONFIG_CPU_SUBTYPE_SH7730)
#define DMTE0_IRQ evt2irq(0x800)
#define DMTE4_IRQ evt2irq(0xb80)
#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
#define SH_DMAC_BASE0 0xFE008020
#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
#define DMTE0_IRQ evt2irq(0x800)
#define DMTE4_IRQ evt2irq(0xb80)
#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
#define SH_DMAC_BASE0 0xFE008020
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7764)
#define DMTE0_IRQ evt2irq(0x640)
#define DMTE4_IRQ evt2irq(0x780)
#define DMAE0_IRQ evt2irq(0x6c0)
#define SH_DMAC_BASE0 0xFF608020
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
#define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
#define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */
#define DMTE6_IRQ evt2irq(0x700)
#define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */
#define DMTE9_IRQ evt2irq(0x760)
#define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */
#define DMTE11_IRQ evt2irq(0xb20)
#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
#define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/
#define SH_DMAC_BASE0 0xFE008020
#define SH_DMAC_BASE1 0xFDC08020
#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
#define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
#define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */
#define DMTE6_IRQ evt2irq(0x700)
#define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */
#define DMTE9_IRQ evt2irq(0x760)
#define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */
#define DMTE11_IRQ evt2irq(0xb20)
#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
#define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/
#define SH_DMAC_BASE0 0xFE008020
#define SH_DMAC_BASE1 0xFDC08020
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
#define DMTE0_IRQ evt2irq(0x640)
#define DMTE4_IRQ evt2irq(0x780)
#define DMTE6_IRQ evt2irq(0x7c0)
#define DMTE8_IRQ evt2irq(0xd80)
#define DMTE9_IRQ evt2irq(0xda0)
#define DMTE10_IRQ evt2irq(0xdc0)
#define DMTE11_IRQ evt2irq(0xde0)
#define DMAE0_IRQ evt2irq(0x6c0) /* DMA Error IRQ */
#define SH_DMAC_BASE0 0xFC808020
#define SH_DMAC_BASE1 0xFC818020
#else /* SH7785 */
#define DMTE0_IRQ evt2irq(0x620)
#define DMTE4_IRQ evt2irq(0x6a0)
#define DMTE6_IRQ evt2irq(0x880)
#define DMTE8_IRQ evt2irq(0x8c0)
#define DMTE9_IRQ evt2irq(0x8e0)
#define DMTE10_IRQ evt2irq(0x900)
#define DMTE11_IRQ evt2irq(0x920)
#define DMAE0_IRQ evt2irq(0x6e0) /* DMA Error IRQ0 */
#define DMAE1_IRQ evt2irq(0x940) /* DMA Error IRQ1 */
#define SH_DMAC_BASE0 0xFC808020
#define SH_DMAC_BASE1 0xFCC08020
#endif
#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */

6
arch/sh/include/cpu-sh5/cpu/dma.h
View File

@ -1,6 +0,0 @@
#ifndef __ASM_SH_CPU_SH5_DMA_H
#define __ASM_SH_CPU_SH5_DMA_H
/* Nothing yet */
#endif /* __ASM_SH_CPU_SH5_DMA_H */

7
arch/sh/include/mach-common/mach/hp6xx.h
View File

@ -9,10 +9,11 @@
* for more details.
*
*/
#include <linux/sh_intc.h>
#define HP680_BTN_IRQ 32 /* IRQ0_IRQ */
#define HP680_TS_IRQ 35 /* IRQ3_IRQ */
#define HP680_HD64461_IRQ 36 /* IRQ4_IRQ */
#define HP680_BTN_IRQ evt2irq(0x600) /* IRQ0_IRQ */
#define HP680_TS_IRQ evt2irq(0x660) /* IRQ3_IRQ */
#define HP680_HD64461_IRQ evt2irq(0x680) /* IRQ4_IRQ */
#define DAC_LCD_BRIGHTNESS 0
#define DAC_SPEAKER_VOLUME 1

13
arch/sh/include/mach-common/mach/lboxre2.h
View File

@ -11,13 +11,14 @@
* for more details.
*
*/
#include <linux/sh_intc.h>
#define IRQ_CF1 9 /* CF1 */
#define IRQ_CF0 10 /* CF0 */
#define IRQ_INTD 11 /* INTD */
#define IRQ_ETH1 12 /* Ether1 */
#define IRQ_ETH0 13 /* Ether0 */
#define IRQ_INTA 14 /* INTA */
#define IRQ_CF1 evt2irq(0x320) /* CF1 */
#define IRQ_CF0 evt2irq(0x340) /* CF0 */
#define IRQ_INTD evt2irq(0x360) /* INTD */
#define IRQ_ETH1 evt2irq(0x380) /* Ether1 */
#define IRQ_ETH0 evt2irq(0x3a0) /* Ether0 */
#define IRQ_INTA evt2irq(0x3c0) /* INTA */
void init_lboxre2_IRQ(void);

5
arch/sh/include/mach-common/mach/sdk7780.h
View File

@ -11,6 +11,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/sh_intc.h>
#include <asm/addrspace.h>
/* Box specific addresses. */
@ -67,9 +68,9 @@
#define SDK7780_NR_IRL 15
/* IDE/ATA interrupt */
#define IRQ_CFCARD 14
#define IRQ_CFCARD evt2irq(0x3c0)
/* SMC interrupt */
#define IRQ_ETHERNET 6
#define IRQ_ETHERNET evt2irq(0x2c0)
/* arch/sh/boards/renesas/sdk7780/irq.c */

12
arch/sh/include/mach-common/mach/titan.h
View File

@ -4,14 +4,16 @@
#ifndef _ASM_SH_TITAN_H
#define _ASM_SH_TITAN_H
#include <linux/sh_intc.h>
#define __IO_PREFIX titan
#include <asm/io_generic.h>
/* IRQ assignments */
#define TITAN_IRQ_WAN 2 /* eth0 (WAN) */
#define TITAN_IRQ_LAN 5 /* eth1 (LAN) */
#define TITAN_IRQ_MPCIA 8 /* mPCI A */
#define TITAN_IRQ_MPCIB 11 /* mPCI B */
#define TITAN_IRQ_USB 11 /* USB */
#define TITAN_IRQ_WAN evt2irq(0x240) /* eth0 (WAN) */
#define TITAN_IRQ_LAN evt2irq(0x2a0) /* eth1 (LAN) */
#define TITAN_IRQ_MPCIA evt2irq(0x300) /* mPCI A */
#define TITAN_IRQ_MPCIB evt2irq(0x360) /* mPCI B */
#define TITAN_IRQ_USB evt2irq(0x360) /* USB */
#endif /* __ASM_SH_TITAN_H */

2
arch/sh/include/mach-dreamcast/mach/dma.h
View File

@ -11,9 +11,7 @@
#define __ASM_SH_DREAMCAST_DMA_H
/* Number of DMA channels */
#define ONCHIP_NR_DMA_CHANNELS 4
#define G2_NR_DMA_CHANNELS 4
#define PVR2_NR_DMA_CHANNELS 1
/* Channels for cascading */
#define PVR2_CASCADE_CHAN 2

19
arch/sh/include/mach-landisk/mach/iodata_landisk.h
View File

@ -8,6 +8,7 @@
*
* IO-DATA LANDISK support
*/
#include <linux/sh_intc.h>
/* Box specific addresses. */
@ -25,15 +26,15 @@
#define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */
#define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */
#define IRQ_PCIINTA 5 /* PCI INTA IRQ */
#define IRQ_PCIINTB 6 /* PCI INTB IRQ */
#define IRQ_PCIINTC 7 /* PCI INTC IRQ */
#define IRQ_PCIINTD 8 /* PCI INTD IRQ */
#define IRQ_ATA 9 /* ATA IRQ */
#define IRQ_FATA 10 /* FATA IRQ */
#define IRQ_POWER 11 /* Power Switch IRQ */
#define IRQ_BUTTON 12 /* USL-5P Button IRQ */
#define IRQ_FAULT 13 /* USL-5P Fault IRQ */
#define IRQ_PCIINTA evt2irq(0x2a0) /* PCI INTA IRQ */
#define IRQ_PCIINTB evt2irq(0x2c0) /* PCI INTB IRQ */
#define IRQ_PCIINTC evt2irq(0x2e0) /* PCI INTC IRQ */
#define IRQ_PCIINTD evt2irq(0x300) /* PCI INTD IRQ */
#define IRQ_ATA evt2irq(0x320) /* ATA IRQ */
#define IRQ_FATA evt2irq(0x340) /* FATA IRQ */
#define IRQ_POWER evt2irq(0x360) /* Power Switch IRQ */
#define IRQ_BUTTON evt2irq(0x380) /* USL-5P Button IRQ */
#define IRQ_FAULT evt2irq(0x3a0) /* USL-5P Fault IRQ */
void init_landisk_IRQ(void);

19
arch/sh/include/mach-se/mach/se.h
View File

@ -8,6 +8,7 @@
*
* Hitachi SolutionEngine support
*/
#include <linux/sh_intc.h>
/* Box specific addresses. */
@ -82,16 +83,16 @@
#define INTC_IPRD 0xa4000018UL
#define INTC_IPRE 0xa400001aUL
#define IRQ0_IRQ 32
#define IRQ1_IRQ 33
#define IRQ0_IRQ evt2irq(0x600)
#define IRQ1_IRQ evt2irq(0x620)
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
#define IRQ_STNIC 12
#define IRQ_CFCARD 14
#define IRQ_STNIC evt2irq(0x380)
#define IRQ_CFCARD evt2irq(0x3c0)
#else
#define IRQ_STNIC 10
#define IRQ_CFCARD 7
#define IRQ_STNIC evt2irq(0x340)
#define IRQ_CFCARD evt2irq(0x2e0)
#endif
/* SH Ether support (SH7710/SH7712) */
@ -105,9 +106,9 @@
# define PHY_ID 0x01
#endif
/* Ether IRQ */
#define SH_ETH0_IRQ 80
#define SH_ETH1_IRQ 81
#define SH_TSU_IRQ 82
#define SH_ETH0_IRQ evt2irq(0xc00)
#define SH_ETH1_IRQ evt2irq(0xc20)
#define SH_TSU_IRQ evt2irq(0xc40)
void init_se_IRQ(void);

9
arch/sh/include/mach-se/mach/se7343.h
View File

@ -8,6 +8,7 @@
*
* SH-Mobile SolutionEngine 7343 support
*/
#include <linux/sh_intc.h>
/* Box specific addresses. */
@ -118,10 +119,10 @@
#define FPGA_IN 0xb1400000
#define FPGA_OUT 0xb1400002
#define IRQ0_IRQ 32
#define IRQ1_IRQ 33
#define IRQ4_IRQ 36
#define IRQ5_IRQ 37
#define IRQ0_IRQ evt2irq(0x600)
#define IRQ1_IRQ evt2irq(0x620)
#define IRQ4_IRQ evt2irq(0x680)
#define IRQ5_IRQ evt2irq(0x6a0)
#define SE7343_FPGA_IRQ_MRSHPC0 0
#define SE7343_FPGA_IRQ_MRSHPC1 1

6
arch/sh/include/mach-se/mach/se7721.h
View File

@ -11,6 +11,8 @@
#ifndef __ASM_SH_SE7721_H
#define __ASM_SH_SE7721_H
#include <linux/sh_intc.h>
#include <asm/addrspace.h>
/* Box specific addresses. */
@ -49,9 +51,9 @@
#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
#define PA_LED 0xB6800000 /* 8bit LED */
#define PA_FPGA 0xB7000000 /* FPGA base address */
#define PA_FPGA 0xB7000000 /* FPGA base address */
#define MRSHPC_IRQ0 10
#define MRSHPC_IRQ0 evt2irq(0x340)
#define FPGA_ILSR1 (PA_FPGA + 0x02)
#define FPGA_ILSR2 (PA_FPGA + 0x03)

9
arch/sh/include/mach-se/mach/se7722.h
View File

@ -13,6 +13,7 @@
* for more details.
*
*/
#include <linux/sh_intc.h>
#include <asm/addrspace.h>
/* Box specific addresses. */
@ -31,7 +32,7 @@
#define PA_PERIPHERAL 0xB0000000
#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */
#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */
#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */
#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */
#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */
@ -51,7 +52,7 @@
#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
#define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */
#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */
#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */
#define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */
/* GPIO */
@ -77,8 +78,8 @@
#define PORT_HIZCRC 0xA405015CUL
/* IRQ */
#define IRQ0_IRQ 32
#define IRQ1_IRQ 33
#define IRQ0_IRQ evt2irq(0x600)
#define IRQ1_IRQ evt2irq(0x620)
#define IRQ01_MODE 0xb1800000
#define IRQ01_STS 0xb1800004

7
arch/sh/include/mach-se/mach/se7724.h
View File

@ -18,6 +18,7 @@
* for more details.
*
*/
#include <linux/sh_intc.h>
#include <asm/addrspace.h>
/* SH Eth */
@ -35,9 +36,9 @@
#define IRQ2_MR (0xba200028)
/* IRQ */
#define IRQ0_IRQ 32
#define IRQ1_IRQ 33
#define IRQ2_IRQ 34
#define IRQ0_IRQ evt2irq(0x600)
#define IRQ1_IRQ evt2irq(0x620)
#define IRQ2_IRQ evt2irq(0x640)
/* Bits in IRQ012 registers */
#define SE7724_FPGA_IRQ_BASE 220

3
arch/sh/include/mach-se/mach/se7751.h
View File

@ -11,6 +11,7 @@
* Modified for 7751 Solution Engine by
* Ian da Silva and Jeremy Siegel, 2001.
*/
#include <linux/sh_intc.h>
/* Box specific addresses. */
@ -63,7 +64,7 @@
#define BCR_ILCRF (PA_BCR + 10)
#define BCR_ILCRG (PA_BCR + 12)
#define IRQ_79C973 13
#define IRQ_79C973 evt2irq(0x3a0)
void init_7751se_IRQ(void);

7
arch/sh/include/mach-se/mach/se7780.h
View File

@ -12,6 +12,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/sh_intc.h>
#include <asm/addrspace.h>
/* Box specific addresses. */
@ -80,13 +81,13 @@
#define IRQPOS_PCCPW (0 * 4)
/* IDE interrupt */
#define IRQ_IDE0 67 /* iVDR */
#define IRQ_IDE0 evt2irq(0xa60) /* iVDR */
/* SMC interrupt */
#define SMC_IRQ 8
#define SMC_IRQ evt2irq(0x300)
/* SM501 interrupt */
#define SM501_IRQ 0
#define SM501_IRQ evt2irq(0x200)
/* interrupt pin */
#define IRQPIN_EXTINT1 0 /* IRQ0 pin */

4
arch/sh/kernel/cpu/proc.c
View File

@ -7,6 +7,7 @@
static const char *cpu_name[] = {
[CPU_SH7201] = "SH7201",
[CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263",
[CPU_SH7264] = "SH7264", [CPU_SH7269] = "SH7269",
[CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619",
[CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
[CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
@ -25,7 +26,8 @@ static const char *cpu_name[] = {
[CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
[CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
[CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724",
[CPU_SH7372] = "SH7372", [CPU_SH_NONE] = "Unknown"
[CPU_SH7372] = "SH7372", [CPU_SH7734] = "SH7734",
[CPU_SH_NONE] = "Unknown"
};
const char *get_cpu_subtype(struct sh_cpuinfo *c)

6
arch/sh/kernel/cpu/sh2/setup-sh7619.c
View File

@ -65,7 +65,7 @@ static struct plat_sci_port scif0_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 88, 88, 88, 88 },
.irqs = SCIx_IRQ_MUXED(88),
};
static struct platform_device scif0_device = {
@ -82,7 +82,7 @@ static struct plat_sci_port scif1_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 92, 92, 92, 92 },
.irqs = SCIx_IRQ_MUXED(92),
};
static struct platform_device scif1_device = {
@ -99,7 +99,7 @@ static struct plat_sci_port scif2_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 96, 96, 96, 96 },
.irqs = SCIx_IRQ_MUXED(96),
};
static struct platform_device scif2_device = {

4
arch/sh/kernel/cpu/sh2a/Makefile
View File

@ -11,10 +11,14 @@ obj-$(CONFIG_SH_FPU) += fpu.o
obj-$(CONFIG_CPU_SUBTYPE_SH7201) += setup-sh7201.o clock-sh7201.o
obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
obj-$(CONFIG_CPU_SUBTYPE_SH7264) += setup-sh7264.o clock-sh7264.o
obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
obj-$(CONFIG_CPU_SUBTYPE_SH7269) += setup-sh7269.o clock-sh7269.o
obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o
# Pinmux setup
pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o
pinmux-$(CONFIG_CPU_SUBTYPE_SH7264) := pinmux-sh7264.o
pinmux-$(CONFIG_CPU_SUBTYPE_SH7269) := pinmux-sh7269.o
obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y)

153
arch/sh/kernel/cpu/sh2a/clock-sh7264.c Normal file
View File

@ -0,0 +1,153 @@
/*
* arch/sh/kernel/cpu/sh2a/clock-sh7264.c
*
* SH7264 clock framework support
*
* Copyright (C) 2012 Phil Edworthy
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <asm/clock.h>
/* SH7264 registers */
#define FRQCR 0xfffe0010
#define STBCR3 0xfffe0408
#define STBCR4 0xfffe040c
#define STBCR5 0xfffe0410
#define STBCR6 0xfffe0414
#define STBCR7 0xfffe0418
#define STBCR8 0xfffe041c
static const unsigned int pll1rate[] = {8, 12};
static unsigned int pll1_div;
/* Fixed 32 KHz root clock for RTC */
static struct clk r_clk = {
.rate = 32768,
};
/*
* Default rate for the root input clock, reset this with clk_set_rate()
* from the platform code.
*/
static struct clk extal_clk = {
.rate = 18000000,
};
static unsigned long pll_recalc(struct clk *clk)
{
unsigned long rate = clk->parent->rate / pll1_div;
return rate * pll1rate[(__raw_readw(FRQCR) >> 8) & 1];
}
static struct sh_clk_ops pll_clk_ops = {
.recalc = pll_recalc,
};
static struct clk pll_clk = {
.ops = &pll_clk_ops,
.parent = &extal_clk,
.flags = CLK_ENABLE_ON_INIT,
};
struct clk *main_clks[] = {
&r_clk,
&extal_clk,
&pll_clk,
};
static int div2[] = { 1, 2, 3, 4, 6, 8, 12 };
static struct clk_div_mult_table div4_div_mult_table = {
.divisors = div2,
.nr_divisors = ARRAY_SIZE(div2),
};
static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
};
enum { DIV4_I, DIV4_P,
DIV4_NR };
#define DIV4(_reg, _bit, _mask, _flags) \
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
/* The mask field specifies the div2 entries that are valid */
struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT
| CLK_ENABLE_ON_INIT),
[DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),
};
enum { MSTP77, MSTP74, MSTP72,
MSTP60,
MSTP35, MSTP34, MSTP33, MSTP32, MSTP30,
MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
[MSTP77] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 7, 0), /* SCIF */
[MSTP74] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 4, 0), /* VDC */
[MSTP72] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 2, 0), /* CMT */
[MSTP60] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR6, 0, 0), /* USB */
[MSTP35] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 6, 0), /* MTU2 */
[MSTP34] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 4, 0), /* SDHI0 */
[MSTP33] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 3, 0), /* SDHI1 */
[MSTP32] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 2, 0), /* ADC */
[MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
};
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("rclk", &r_clk),
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("pll_clk", &pll_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
/* MSTP clocks */
CLKDEV_CON_ID("sci_ick", &mstp_clks[MSTP77]),
CLKDEV_CON_ID("vdc3", &mstp_clks[MSTP74]),
CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP72]),
CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP35]),
CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP34]),
CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP33]),
CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]),
CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]),
};
int __init arch_clk_init(void)
{
int k, ret = 0;
if (test_mode_pin(MODE_PIN0)) {
if (test_mode_pin(MODE_PIN1))
pll1_div = 3;
else
pll1_div = 4;
} else
pll1_div = 1;
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
return ret;
}

184
arch/sh/kernel/cpu/sh2a/clock-sh7269.c Normal file
View File

@ -0,0 +1,184 @@
/*
* arch/sh/kernel/cpu/sh2a/clock-sh7269.c
*
* SH7269 clock framework support
*
* Copyright (C) 2012 Phil Edworthy
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <asm/clock.h>
/* SH7269 registers */
#define FRQCR 0xfffe0010
#define STBCR3 0xfffe0408
#define STBCR4 0xfffe040c
#define STBCR5 0xfffe0410
#define STBCR6 0xfffe0414
#define STBCR7 0xfffe0418
#define PLL_RATE 20
/* Fixed 32 KHz root clock for RTC */
static struct clk r_clk = {
.rate = 32768,
};
/*
* Default rate for the root input clock, reset this with clk_set_rate()
* from the platform code.
*/
static struct clk extal_clk = {
.rate = 13340000,
};
static unsigned long pll_recalc(struct clk *clk)
{
return clk->parent->rate * PLL_RATE;
}
static struct sh_clk_ops pll_clk_ops = {
.recalc = pll_recalc,
};
static struct clk pll_clk = {
.ops = &pll_clk_ops,
.parent = &extal_clk,
.flags = CLK_ENABLE_ON_INIT,
};
static unsigned long peripheral0_recalc(struct clk *clk)
{
return clk->parent->rate / 8;
}
static struct sh_clk_ops peripheral0_clk_ops = {
.recalc = peripheral0_recalc,
};
static struct clk peripheral0_clk = {
.ops = &peripheral0_clk_ops,
.parent = &pll_clk,
.flags = CLK_ENABLE_ON_INIT,
};
static unsigned long peripheral1_recalc(struct clk *clk)
{
return clk->parent->rate / 4;
}
static struct sh_clk_ops peripheral1_clk_ops = {
.recalc = peripheral1_recalc,
};
static struct clk peripheral1_clk = {
.ops = &peripheral1_clk_ops,
.parent = &pll_clk,
.flags = CLK_ENABLE_ON_INIT,
};
struct clk *main_clks[] = {
&r_clk,
&extal_clk,
&pll_clk,
&peripheral0_clk,
&peripheral1_clk,
};
static int div2[] = { 1, 2, 0, 4 };
static struct clk_div_mult_table div4_div_mult_table = {
.divisors = div2,
.nr_divisors = ARRAY_SIZE(div2),
};
static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
};
enum { DIV4_I, DIV4_B,
DIV4_NR };
#define DIV4(_reg, _bit, _mask, _flags) \
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
/* The mask field specifies the div2 entries that are valid */
struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
| CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT
| CLK_ENABLE_ON_INIT),
};
enum { MSTP72,
MSTP60,
MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
MSTP35, MSTP32, MSTP30,
MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
[MSTP72] = SH_CLK_MSTP8(&peripheral0_clk, STBCR7, 2, 0), /* CMT */
[MSTP60] = SH_CLK_MSTP8(&peripheral1_clk, STBCR6, 0, 0), /* USB */
[MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
[MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
[MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
[MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
[MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
[MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
[MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
[MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
[MSTP35] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 5, 0), /* MTU2 */
[MSTP32] = SH_CLK_MSTP8(&peripheral1_clk, STBCR3, 2, 0), /* ADC */
[MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
};
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("rclk", &r_clk),
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("pll_clk", &pll_clk),
CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
/* MSTP clocks */
CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP72]),
CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP35]),
CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]),
CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]),
};
int __init arch_clk_init(void)
{
int k, ret = 0;
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
return ret;
}

2136
arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c Normal file
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File diff suppressed because it is too large Load Diff

2800
arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c Normal file
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File diff suppressed because it is too large Load Diff

6
arch/sh/kernel/cpu/sh2a/probe.c
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@ -29,6 +29,12 @@ void __cpuinit cpu_probe(void)
#elif defined(CONFIG_CPU_SUBTYPE_SH7263)
boot_cpu_data.type = CPU_SH7263;
boot_cpu_data.flags |= CPU_HAS_FPU;
#elif defined(CONFIG_CPU_SUBTYPE_SH7264)
boot_cpu_data.type = CPU_SH7264;
boot_cpu_data.flags |= CPU_HAS_FPU;
#elif defined(CONFIG_CPU_SUBTYPE_SH7269)
boot_cpu_data.type = CPU_SH7269;
boot_cpu_data.flags |= CPU_HAS_FPU;
#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
boot_cpu_data.type = CPU_SH7206;
boot_cpu_data.flags |= CPU_HAS_DSP;

2
arch/sh/kernel/cpu/sh2a/setup-mxg.c
View File

@ -204,7 +204,7 @@ static struct plat_sci_port scif0_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 220, 220, 220, 220 },
.irqs = SCIx_IRQ_MUXED(220),
};
static struct platform_device scif0_device = {

16
arch/sh/kernel/cpu/sh2a/setup-sh7201.c
View File

@ -183,7 +183,7 @@ static struct plat_sci_port scif0_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 180, 180, 180, 180 }
.irqs = SCIx_IRQ_MUXED(180),
};
static struct platform_device scif0_device = {
@ -200,7 +200,7 @@ static struct plat_sci_port scif1_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 184, 184, 184, 184 }
.irqs = SCIx_IRQ_MUXED(184),
};
static struct platform_device scif1_device = {
@ -217,7 +217,7 @@ static struct plat_sci_port scif2_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 188, 188, 188, 188 }
.irqs = SCIx_IRQ_MUXED(188),
};
static struct platform_device scif2_device = {
@ -234,7 +234,7 @@ static struct plat_sci_port scif3_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 192, 192, 192, 192 }
.irqs = SCIx_IRQ_MUXED(192),
};
static struct platform_device scif3_device = {
@ -251,7 +251,7 @@ static struct plat_sci_port scif4_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 196, 196, 196, 196 }
.irqs = SCIx_IRQ_MUXED(196),
};
static struct platform_device scif4_device = {
@ -268,7 +268,7 @@ static struct plat_sci_port scif5_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 200, 200, 200, 200 }
.irqs = SCIx_IRQ_MUXED(200),
};
static struct platform_device scif5_device = {
@ -285,7 +285,7 @@ static struct plat_sci_port scif6_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 204, 204, 204, 204 }
.irqs = SCIx_IRQ_MUXED(204),
};
static struct platform_device scif6_device = {
@ -302,7 +302,7 @@ static struct plat_sci_port scif7_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 208, 208, 208, 208 }
.irqs = SCIx_IRQ_MUXED(208),
};
static struct platform_device scif7_device = {

8
arch/sh/kernel/cpu/sh2a/setup-sh7203.c
View File

@ -180,7 +180,7 @@ static struct plat_sci_port scif0_platform_data = {
SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 192, 192, 192, 192 },
.irqs = SCIx_IRQ_MUXED(192),
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
@ -199,7 +199,7 @@ static struct plat_sci_port scif1_platform_data = {
SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 196, 196, 196, 196 },
.irqs = SCIx_IRQ_MUXED(196),
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
@ -218,7 +218,7 @@ static struct plat_sci_port scif2_platform_data = {
SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 200, 200, 200, 200 },
.irqs = SCIx_IRQ_MUXED(200),
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};
@ -237,7 +237,7 @@ static struct plat_sci_port scif3_platform_data = {
SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 204, 204, 204, 204 },
.irqs = SCIx_IRQ_MUXED(204),
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
};

8
arch/sh/kernel/cpu/sh2a/setup-sh7206.c
View File

@ -139,7 +139,7 @@ static struct plat_sci_port scif0_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 240, 240, 240, 240 },
.irqs = SCIx_IRQ_MUXED(240),
};
static struct platform_device scif0_device = {
@ -156,7 +156,7 @@ static struct plat_sci_port scif1_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 244, 244, 244, 244 },
.irqs = SCIx_IRQ_MUXED(244),
};
static struct platform_device scif1_device = {
@ -173,7 +173,7 @@ static struct plat_sci_port scif2_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 248, 248, 248, 248 },
.irqs = SCIx_IRQ_MUXED(248),
};
static struct platform_device scif2_device = {
@ -190,7 +190,7 @@ static struct plat_sci_port scif3_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 252, 252, 252, 252 },
.irqs = SCIx_IRQ_MUXED(252),
};
static struct platform_device scif3_device = {

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